Front-end sampling circuit and signal sampling method

Abstract

The application discloses a front-end sampling circuit and a signal sampling method. The front-end sampling circuit includes a global switch, a local switch and an auxiliary switch. The global switch is used to selectively conduct according to a first control signal to transmit an input signal. The local switch is used to selectively conduct according to a second control signal to transmit the input signal from the global switch to a node, wherein a storage circuit is coupled to the node to store the input signal. The auxiliary switch is used to selectively conduct according to a third control signal to transmit the input signal to the node, wherein the turn-off time point of the auxiliary switch is set to be earlier than or the same as the turn-off time point of the global switch.

Description

TECHNICAL FIELD

[0001] The present application relates to a front-end sampling circuit applied to an analog-to-digital converter, in particular, a front-end sampling circuit and a signal sampling method for setting an additional path to improve the speed of tracking an input signal. BACKGROUND

[0002] Analog-to-digital converters are commonly used in various electronic devices to convert analog signals into corresponding digital signals for subsequent signal processing. As the operating speed becomes faster and faster, the operational period of the analog-to-digital converter for converting signals becomes shorter and shorter. For example, a sampling circuit must sample an input signal within a limited sampling period. When the frequency of the input signal is very high, the input signal will generate a certain amount of voltage difference in a very short time. In this case, the sampling circuit in the prior art needs a longer processing time to obtain the corresponding signal value. If the sampling circuit cannot track the input signal within the limited sampling period, the sampled signal value may be distorted and insufficient to restore the input signal, resulting in a decrease in the resolution of the analog-to-digital converter. SUMMARY

[0003] In some embodiments, one of the purposes of the present application is (but not limited to) to provide a front-end sampling circuit and a signal conversion method applicable to a time-interleaved analog-to-digital converter.

[0004] In some embodiments, the front-end sampling circuit includes a global switch, a local switch, and an auxiliary switch. The global switch is used to selectively conduct according to a first control signal to transmit an input signal. The local switch is used to selectively conduct according to a second control signal to transmit the input signal from the global switch to a node, wherein a storage circuit is coupled to the node to store the input signal. The auxiliary switch is used to selectively conduct according to a third control signal to transmit the input signal to the node, wherein the turn-off point of the auxiliary switch is set to be earlier than or the same as the turn-off point of the global switch.

[0005] In some embodiments, the signal sampling method includes the following operations: selectively conducting a global switch according to a first control signal to transmit an input signal; selectively conducting a local switch according to a second control signal to transmit the input signal from the global switch to a node, wherein a storage circuit is coupled to the node to store the input signal; and selectively conducting an auxiliary switch according to a third control signal to transmit the input signal to the node, wherein the turn-off point of the auxiliary switch is set to be earlier than or the same as the turn-off point of the global switch.

[0006] The features, implementations, and effects of the present application are described in detail below with reference to the preferred embodiments and the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 a schematic diagram of a front-end sampling circuit according to some embodiments of the present application;

[0008] Figure 2 a schematic diagram of a front-end sampling circuit according to some embodiments of the present application;

[0009] Figure 3A a timing diagram of a plurality of control signals in Figure 1 or Figure 2 according to some embodiments of the present application;

[0010] Figure 3B a timing diagram of a plurality of control signals in Figure 1 or Figure 2 according to some embodiments of the present application;

[0011] Figure 4 a timing diagram of a plurality of control signals in Figure 1 or Figure 2 according to some embodiments of the present application;

[0012] Figure 5 a timing diagram of a plurality of control signals in Figure 2 according to some embodiments of the present application; and

[0013] Figure 6 a flowchart of a signal sampling method according to some embodiments of the present application.

[0014] Symbol explanation:

[0015] 100, 200: front-end sampling circuit

[0016] 110[0]~110[n]: storage circuit

[0017] 210: buffer circuit

[0018] 600: signal sampling method

[0019] C G : capacitor

[0020] E1~E3: falling edge

[0021] N0~Nn: node

[0022] P[0]~P[n], S[0]~S[n], S0: control signal

[0023] S1: sampling signal

[0024] S610, S620, S630: operation

[0025] SW A0 SW An : auxiliary switch

[0026] SW G : global switch

[0027] SW L0 SW Ln : local switch

[0028] VIN: input signal

[0029] t01-t06, t11-t16, t21-t26: time points DETAILED DESCRIPTION

[0030] All words used herein are to be interpreted according to their normal meaning. The definitions of the above words in the generally accepted dictionaries are to be included in the content of this application, and the use of any of the words discussed herein in this specification is merely an example and should not limit the scope and meaning of this application. Similarly, this application is not limited to the various embodiments shown in this specification.

[0031] As used herein, "coupled" or "connected" can mean either a direct electrical or physical contact between two or more components or an indirect electrical or physical contact between two or more components through another component. As used herein, the term "circuitry" can mean a single system formed from at least one circuit, and the term "circuit" can mean a device that processes signals by means of at least one transistor and / or at least one passive component in a certain manner.

[0032] As used herein, "about," "approximately," or "substantially" generally refers to an error or range of error of about 20%, preferably about 10%, and more preferably about 5% of a value. If not explicitly stated otherwise, the values mentioned herein are to be considered as approximate values, i.e., as values within an error or range as indicated by "about," "approximately," or "substantially."

[0033] As used herein, the term "and / or" includes any combination of one or more of the associated listed items. In this document, the terms first, second, and third, etc. are used to describe various components. Thus, the first component can also be referred to as the second component, without departing from the spirit of this application.

[0034] Figure 1 A schematic diagram of a front-end sampling circuit 100 according to some embodiments of the application. In some embodiments, the front-end sampling circuit 100 can be applied to (but not limited to) a time-interleaved analog-to-digital converter to configure multiple channels in the time-interleaved analog-to-digital converter to sample an input signal VIN alternately.

[0035] The front-end sampling circuit 100 includes a global switch SW G , a plurality of local switches SW L0 ~SW Ln , a plurality of auxiliary switches SW A0 ~SW An , and a plurality of storage circuits 110[0]~110[n] (some of which are omitted in the figure). In some embodiments, the plurality of storage circuits 110[0]~110[n] can be a plurality of sample-and-hold circuits in a plurality of channels of a time-interleaved analog-to-digital converter, where n can be a positive integer greater than or equal to 1. For example, each of the plurality of storage circuits 110[0]~110[n] can be implemented by, but not limited to, a capacitor array circuit or a capacitor-based digital-to-analog converter circuit.

[0036] The global switch SW G is configured to be selectively turned on according to a control signal S0 to transmit the input signal VIN. Each of the plurality of local switches SW L0 ~SW Ln is configured to be turned on according to a corresponding one of a plurality of control signals S[0]~S[n] to transmit the input signal VIN from the global switch SW G to a corresponding one of a plurality of nodes N0~Nn (some of which are omitted in the figure). The plurality of storage circuits 110[0]~110[n] are coupled to the plurality of nodes N0~Nn to store the input signal VIN for subsequent signal conversion. In detail, taking the local switch SW L0 and the storage circuit 110[0] as an example, a first terminal of the global switch SW G receives the input signal VIN, a second terminal of the global switch SW G is coupled to the node N0 via the local switch SW L0 , and a control terminal of the global switch SW G receives the control signal S0. The local switch SW L0 is turned on according to the control signal S[0] to transmit the input signal VIN from the global switch SW G to the node N0. In other words, when the global switch SW G and the local switch SW L0 are both turned on, the input signal VIN can be transmitted to the node N0 to cause the storage circuit 110[0] to store the input signal VIN. By analogy, the corresponding relationships between the remaining plurality of local switches SW L1 ~SW Ln , the plurality of control signals S[1]~S[n], the plurality of storage circuits 110[1]~110[n], and the plurality of nodes N1~Nn can be understood. By setting the global switch SW GThe connection between the storage circuits 110[0] to 110[n] and the input signal VIN can be disconnected during the period when the input signal VIN is not sampled, thereby reducing the effect of timing skew from multiple control signals S[1] to S[n].

[0037] Multiple auxiliary switches SW A0 ~SW An Each of the multiple control signals P[0] to P[n] is turned on according to one of the corresponding signals to transmit the input signal VIN to one of the multiple nodes N0 to Nn. For example, auxiliary switch SW A0 The switch is turned on according to the control signal P[0] to transmit the input signal VIN to node N0. Similarly, the remaining auxiliary switches SW can be understood as... A1 ~SW An The correspondence between multiple control signals P[1]~P[n] and multiple nodes N1~Nn.

[0038] In different embodiments, multiple auxiliary switches SW A0 ~SW An The conduction time of each of them can be set to be earlier than, the same as or later than the global switch SW. G The conduction time, and multiple auxiliary switches SW A0 ~SW An The shutdown time of each device can be set to be earlier than or the same as the global switch SW. G The off time. Through the above configuration, multiple auxiliary switches SW... A0 ~SW An Each of these circuits can provide an additional signal path to transmit the input signal VIN to multiple storage circuits 110[0] to 110[n] during the sampling of the input signal VIN. In this way, the tracking speed of the storage circuits 110[0] to 110[n] for the input signal VIN can be improved to suit the sampling of input signals VIN with high frequencies.

[0039] In some embodiments, multiple auxiliary switches SW A0 ~SW An The specifications of each of them can be lower than those of the global switch SW. G or multiple local switches SW L0 ~SW Lnspecification requirements. In some embodiments, the specification requirements herein can include, but are not limited to, on-resistance, on-resistance at different voltages, clock feed through or charge injection at on or off transition, linearity, etc. For example, to improve the performance of the front-end sampling circuit 100, the global switch SW G or the plurality of local switches SW L0 ~SW Ln may be implemented by a switch circuit with higher performance, such as a bootstrapped switch circuit, so that the switches have higher linearity or provide more stable transfer values. For example, the global switch SW G and each of the plurality of local switches SW L0 ~SW Ln may be implemented by, but not limited to, a bootstrapped switch circuit. In contrast, the plurality of auxiliary switches SW A0 ~SW An are used to provide additional paths to speed up the tracking speed of the input signal VIN without affecting the sampling operation, and thus each of the plurality of auxiliary switches SW A0 ~SW An may be implemented by a simpler switch circuit, such as, but not limited to, a complementary pass-gate circuit. In this way, the circuit cost of the plurality of auxiliary switches SW A0 ~SW An may be reduced. In other words, in some embodiments, the circuit area of each of the plurality of auxiliary switches SW A0 ~SW An may be lower than the circuit area of each of the global switch SW G and the plurality of local switches SW L0 ~SW Ln .

[0040] Figure 2 is a schematic diagram of a front-end sampling circuit 200 according to some embodiments of the present disclosure. Compared to the front-end sampling circuit 100, Figure 1 in this embodiment, the front-end sampling circuit 200 further includes a capacitor C G and a buffer circuit 210.

[0041] The capacitor C G is coupled to the global switch SW G to receive the input signal VIN from the global switch SW G and store the input signal VIN as a sampling signal S1. The buffer circuit 210 is coupled to the capacitor C G and used to transmit the sampling signal S1 to the plurality of local switches SW L0 ~SW LnIn this embodiment, the plurality of local switches SW L0 ~SW Ln are used to transmit the sampling signal S1 to the plurality of nodes N0~Nn, and the plurality of storage circuits 110[0]~110[n] are also used to store the sampling signal S1. For example, when the global switch SW G is turned on, the capacitor C G can store the input signal VIN as the sampling signal S1. When the local switch SW L0 is turned on, the sampling signal S1 can be transmitted to the node N0 via the local switch SW L0 . In this way, the storage circuit 110[0] can store the sampling signal S1.

[0042] By providing the buffer circuit 210, the driving capability can be further improved to transmit the input signal VIN (equivalent to the sampling signal S1) to more storage circuits, and the number of time-interleaved channels can be further increased. Furthermore, compared with the embodiment shown in Figure 1 , in this embodiment, the turn-off time of each of the plurality of auxiliary switches SW A0 ~SW An can be set to be earlier than or the same as the turn-off time of the global switch SW G . In other words, by the driving capability of the buffer circuit 210, the signal value stored by the plurality of storage circuits 110[0]~110[n] can be quickly corrected.

[0043] Figure 1 The number of circuits shown in Figure 2 is used for example, and the present application is not limited thereto. For example, the front-end sampling circuit 100 (or the front-end sampling circuit 200) can include more global switches, and a plurality of groups of local switches and a plurality of groups of storage circuits corresponding to the global switches. The circuit arrangement shown in the front-end sampling circuit 100 (or the front-end sampling circuit 200) is used for example, and the present application is not limited thereto. For example, in other embodiments, each of the plurality of auxiliary switches SW A0 ~SW An may be connected between the second end of the global switch SW G and a corresponding one of the plurality of nodes N0~Nn. For example, the auxiliary switch SWA0 is coupled between the second end of the global switch SW G and the node N0. Various arrangements using the auxiliary switches SW A0 ~SW An to provide additional signal paths to speed up the tracking of the input signal VIN are all within the scope of the present application.

[0044] Figure 3A is drawn according to some embodiments of the present application Figure 1 or Figure 2Fig. 6 is a timing diagram of the plurality of control signals in Fig. 5. In this embodiment, the turn-off time point (e.g., time point t04) of the auxiliary switch SW A0 is set to be earlier than the turn-off time point (e.g., time point t05) of the global switch SW G , and the turn-on time point (e.g., time point t01 or t02) of the auxiliary switch SW A0 is set to be earlier than the turn-on time point (e.g., time point t03) of the global switch SW G .

[0045] For example, at time point t04, the control signal P[0] is switched to the disable level to turn off the auxiliary switch SW A0 . In other words, the auxiliary switch SW A0 begins to turn off at the turn-off time point t04. Similarly, at time point t05, the control signal S0 is switched to the disable level to turn off the global switch SW G . In other words, the global switch SW G begins to turn off (i.e., not to turn on) at the turn-off time point t05, where the time point t04 is earlier than the time point t05. Further, at time point t01 (see the control signal P[0] pattern of setting one) or time point t02 (see the control signal P[0] pattern of setting two), the control signal P[0] is switched to the enable level to turn on the auxiliary switch SW A0 . The auxiliary switch SW A0 begins to turn on at the turn-on time point t01 (setting one of the control signal P[0]) or time point t02 (setting two of the control signal P[0]). Similarly, at time point t03, the control signal S0 is switched to the enable level to turn on the global switch SW G . The global switch SW G begins to turn on at the turn-on time point t03, where the time point t01 and the time point t02 are both earlier than the time point t03.

[0046] When the turn-off time point (e.g., time point t04) of the auxiliary switch SW A0 is set to be earlier than the turn-off time point (e.g., time point t05) of the global switch SW G , the turn-on time point (e.g., time point t02) of the local switch SW L0 controlled by the control signal S[0] is earlier than the turn-on time point (e.g., time point t03) of the global switch SW G , and the turn-off time point (e.g., time point t06) of the local switch SW L0 is later than the turn-off time point (e.g., time point t05) of the global switch SW GThe shutdown time point (e.g., time point t05). Specifically, at time point t02, the control signal S[0] switches to the enable level to turn on the local switch SW. L0 In other words, the local switch SW L0 The start time of conduction is time point t02, where time point t02 is earlier than time point t03 (i.e., the global switch SW). G (The conduction time point). Similarly, at time point t06, the control signal S[0] switches to the disabled level to turn off the local switch SW. L0 In other words, the local switch SW L0 The shutdown begins at time point t06, which is later than time point t05 (i.e., the global switch SW). G (the shutdown time point).

[0047] Additionally, in this example, the auxiliary switch SW A0 The turn-on time can be set to be earlier than or the same as the local switch SW. L0 The conduction time point. For example, in setting one, the auxiliary switch SW A0 The conduction time point is time point t01, which is earlier than the local switch SW. L0 The conduction time point (e.g., time point t02). Alternatively, in setting two, the auxiliary switch SW... A0 The conduction time point is time point t02, which is the same as the local switch SW. L0 The conduction time (e.g., time t02). By means of the above configuration, during the sampling of the input signal VIN by the storage circuit 110[0], the auxiliary switch SW... A0 It can be turned on to provide an additional path to couple the input signal VIN to the storage circuit 110[0], thereby accelerating the tracking speed of the storage circuit 110[0] for the input signal VIN. Furthermore, due to the auxiliary switch SW... A0 The shutdown time is earlier than the global switch SW. G The shutdown time point is such that the aforementioned additional path will not affect the original sampling operation.

[0048] Figure 3B Drawings based on some embodiments of this application Figure 1 or Figure 2 A timing diagram of multiple control signals in the process. Compared to Figure 3A In this embodiment, the auxiliary switch SW A0 The on-time point (e.g., time point t03) controlled by the control signal P[0] is set to be the same as that of the global switch SW. GThe conduction time point (e.g., time point t03). For example, control signal P[0] and control signal S0 switch to the enable level at the same time point t03 to turn on the auxiliary switch SW respectively. A0 With global switch SW G Auxiliary switch SW A0 Shutdown time point, global switch SW G Shutdown time point, local switch SW L0 The conduction time point, local switch SW L0 The setting method between the shutdown time points is the same as Figure 3A Therefore, I will not elaborate further here.

[0049] Figure 4 Drawings based on some embodiments of this application Figure 1 or Figure 2 A timing diagram of multiple control signals is shown. In this embodiment, when the auxiliary switch SW... A0 The off time point (e.g., time point t14) controlled by the control signal P[0] of setting one or setting two is set to be earlier than the global switch SW. G At the turn-off time point (e.g., time point t15) controlled by control signal S0, the local switch SW L0 The turn-on time (e.g., time point t13) of the control signal S[0] is later than that of the global switch SW. G The conduction time point (e.g., time point t12), and the local switch SW L0 The shutdown time (e.g., time point t16) is later than the global switch SW. G The shutdown time point.

[0050] Specifically, at time t14, the control signal P[0] in setting one or setting two is switched to the disabled level to turn off the auxiliary switch SW. A0 In other words, the auxiliary switch SW A0 The shutdown begins at time t14. At time t15, control signal S0 switches to the disabled level to turn off the global switch SW. G In other words, the global switch SW G The shutdown begins at time t15, where time t14 is earlier than time t15. Furthermore, at time t13, the control signal S[0] switches to the enable level to turn on the local switch SW. L0 Local switch SW L0 The conduction begins at time point t13. At time point t12, the control signal S0 switches to the enable level to turn on the global switch SW. G Global switch SW GThe turn-on time point of the local switch SW L0 is time point t12, where time point t13 is later than time point t12. At time point t16, the control signal S[0] is switched to the disable level to turn off the local switch SW L0 . The turn-off time point of the local switch SW G is time point t16, where time point t16 is later than time point t15 (i.e. the turn-off time point of the global switch SW A0 ).

[0051] In addition, in this example, the turn-on time point of the auxiliary switch SW L0 may be set to be earlier than or the same as the turn-on time point of the local switch SW A0 . For example, in setting one, the control signal P[0] is switched to the enable level at time point t11 to turn on the auxiliary switch SW A0 . The turn-on time point of the auxiliary switch SW L0 is time point t11, which is earlier than the turn-on time point of the local switch SW A0 (e.g. time point t12). Alternatively, in setting two, the control signal P[0] is switched to the enable level at time point t12 to turn on the auxiliary switch SW A0 . The turn-on time point of the auxiliary switch SW L0 is time point t12, which is the same as the turn-on time point of the local switch SW A0 .

[0052] Figure 5 is a timing diagram of a plurality of control signals in Figure 2 according to some embodiments of the present application. In some embodiments, the timing configuration shown in Figure 5 is applicable to the front-end sampling circuit 200 of Figure 2 . Unlike the foregoing embodiments, in Figure 5 , the turn-on time point of the auxiliary switch SW G (controlled by the control signal P[0]) can be earlier (setting one), the same as (setting two) or later (setting three) than the turn-on time point of the global switch SW A0 (e.g. time point t22), and the turn-off time point of the auxiliary switch SW G (e.g. time point t24 or t25) can be earlier than or the same as the turn-off time point of the global switch SW G (e.g. time point t25).

[0053] In detail, at time point t22, the control signal S0 is switched to the enable level to turn on the global switch SW GThe conduction begins at time t22. At time t25, the control signal S0 switches to the disabled level to turn off the global switch SW. G In other words, the global switch SW G The shutdown time point is t25. In setting one, the control signal P[0] switches to the enable level at time point t21 to turn on the auxiliary switch SW. A0 Furthermore, the control signal P[0] switches to the disabled level at time t24 to turn off the auxiliary switch SW. A0 In setting one, the auxiliary switch SW A0 The conduction begins at time point t21, which is earlier than time point t22 (i.e., the global switch SW). G (the conduction time point), and auxiliary switch SW A0 The shutdown start time can be time point t24, which is earlier than time point t25 (i.e., global switch SW). G (the turn-off time point). Alternatively, in other examples, the control signal P[0] may be delayed until time point t25 (indicated by the dashed line) before switching to the disabled level (i.e., the falling edge E1) to turn off the auxiliary switch SW. A0 In other words, in setting one, the auxiliary switch SW A0 The shutdown start time can be extended to time point t25, which is the same as the global switch SW. G The shutdown time point.

[0054] Similarly, in setup two, the control signal P[0] switches to the enable level at time t22 to turn on the auxiliary switch SW. A0 Furthermore, the control signal P[0] switches to the disabled level at time t24 to turn off the auxiliary switch SW. A0 In setting two, the auxiliary switch SW A0 The start time for conduction is time point t22, which is the same as the global switch SW. G The conduction time point, and the auxiliary switch SW A0 The shutdown start time can be time point t24, which is earlier than the global switch SW. G The turn-off time point. Alternatively, in other examples, the control signal P[0] may be delayed until time point t25 (indicated by the dashed line) to switch to the disabled level (i.e., the falling edge E2) to turn off the auxiliary switch SW. A0 In other words, in setting two, the auxiliary switch SW A0 The shutdown start time can be extended to time point t25, which is the same as the global switch SW. G The shutdown time point.

[0055] In setting 3, the control signal P[0] switches to the enable level at time t23 to turn on the auxiliary switch SW.A0 Furthermore, the control signal P[0] switches to the disabled level at time t24 to turn off the auxiliary switch SW. A0 In setting three, the auxiliary switch SW A0 The conduction begins at time t23, which is later than the global switch SW. G The conduction time point, and the auxiliary switch SW A0 The shutdown start time can be time point t24, which is earlier than the global switch SW. G The turn-off time point. Alternatively, in other examples, the control signal P[0] may be delayed until time point t25 (indicated by the dashed line) to switch to the disabled level (i.e., the falling edge E3) to turn off the auxiliary switch SW. A0 In other words, in setting three, the auxiliary switch SW A0 The shutdown start time can be extended to time point t25, which is the same as the global switch SW. G The shutdown time point. As previously mentioned, at Figure 2 In this embodiment, by providing a buffer circuit 210, the signal values ​​stored in the multiple storage circuits 110[0] to 110[n] can be quickly corrected. Therefore, in Figure 5 In some of the examples shown, the auxiliary switch SW A0 With global switch SW G It can be turned off at the same time point without affecting the original sampling operation.

[0056] Furthermore, in this embodiment, the local switch SW L0 The turn-on time (e.g., time t26) of the control signal S[0] is later than that of the global switch SW. G The shutdown time point (e.g., time point t25). Specifically, the control signal S0 switches to the disabled level at time point t26 to turn off the local switch SW. L0 In other words, the local switch SW L0 The shutdown begins at time t26, which is later than the global switch SW. G The shutdown time point. By using the above configuration method, the local SW switch can be prevented. L0 Affecting capacitor C G The process of storing the input signal VIN.

[0057] Figure 3A , Figure 3B , Figure 4 as well as Figure 5 The timing sequence shown is based on the local switch (e.g., local switch SW) corresponding to one channel in the control time interleaving. L0 The control signal S[0] and the auxiliary switch (e.g., auxiliary switch SW) A0The timing of the control signal P[0] in one sampling is taken as an example. The corresponding relationship between the control signals S[1]-S[n] and P[1]-P[n] and the control signal S0 can be similarly deduced, and thus will not be repeated here.

[0058] Figure 6 A flowchart of a signal sampling method 600 is drawn according to some embodiments of the present application. In operation S610, a global switch (e.g., the global switch SW G ) is selectively turned on according to a first control signal (e.g., the control signal S0) to transmit an input signal (e.g., the input signal VIN). In operation S620, a local switch (e.g., the local switch SW L0 ) is selectively turned on according to a second control signal (e.g., the control signal S[0]) to transmit the input signal from the global switch to a node (e.g., the node N0), wherein a storage circuit (e.g., the storage circuit 110[0]) is coupled to the node to store the input signal. In operation S630, an auxiliary switch (e.g., the auxiliary switch SW A0 ) is selectively turned on according to a third control signal (e.g., the control signal P[0]) to transmit the input signal to the node, wherein the turn-off time point of the auxiliary switch is set to be earlier than or the same as the turn-off time point of the global switch.

[0059] The above operations can be understood with reference to the foregoing embodiments, and thus will not be repeated here. Figure 6 The operations and / or steps in the above embodiments are merely examples, and are not intended to limit the order of execution according to the examples. Without departing from the operation mode and scope of the embodiments of the present application, the operations in the signal sampling method 600 can be appropriately added, replaced, omitted, or executed in different order. Alternatively, the operations in the signal sampling method 600 can be simultaneously or partially simultaneously executed.

[0060] In summary, the front-end sampling circuit and the signal sampling method in some embodiments of the present application can use switches with lower specifications to provide additional paths for sampling. In this way, the speed of the storage circuit (e.g., the sample-and-hold circuit) in tracking the input signal can be improved, so as to improve the overall operation speed of the analog-to-digital converter.

[0061] Although the embodiments of the present application are described above, the embodiments are not intended to limit the present application. Those skilled in the art can make changes to the technical features of the present application according to the explicit or implicit content of the present application, and such changes can all fall within the scope of the patent protection sought by the present application. In other words, the scope of the patent protection of the present application shall be subject to the claims of the present specification.

Claims

1. A front-end sampling circuit, characterized in that, Include: A global switch is used to selectively turn on according to a first control signal to transmit an input signal; A local switch is selectively turned on according to a second control signal to transmit the input signal from the global switch to a node, wherein a storage circuit is coupled to the node to store the input signal; as well as An auxiliary switch is selectively turned on according to a third control signal to transmit the input signal to the node, wherein the off time of the auxiliary switch is set to be earlier than or the same as the off time of the global switch. The local switch turns off later than the global switch.

2. The front-end sampling circuit as described in claim 1, characterized in that, The input signal is received at a first terminal of the global switch and at a first terminal of the auxiliary switch, and a second terminal of the global switch is coupled to the node via the local switch.

3. The front-end sampling circuit as described in claim 1, characterized in that, The local switch is turned on earlier than the global switch.

4. The front-end sampling circuit as described in claim 3, characterized in that, The turn-on time of the auxiliary switch is earlier than or the same as the turn-on time of the local switch.

5. The front-end sampling circuit as described in claim 1, characterized in that, The local switch is activated later than the global switch.

6. The front-end sampling circuit as described in claim 5, characterized in that, The turn-on time of the auxiliary switch is earlier than or the same as the turn-on time of the global switch.

7. The front-end sampling circuit as claimed in claim 1, characterized in that, Also includes: A capacitor is coupled to the global switch to receive the input signal from the global switch and to store the input signal as a sample signal. as well as A buffer circuit, coupled to the capacitor, is used to transmit the sampling signal to the local switch. The local switch is used to transmit the sampling signal to the node, and the storage circuit is used to store the sampling signal.

8. The front-end sampling circuit as claimed in claim 7, characterized in that, The turn-on time of the auxiliary switch is earlier than, later than, or the same as the turn-on time of the global switch, and the turn-on time of the local switch is later than the turn-off time of the global switch.

9. The front-end sampling circuit as claimed in claim 1, characterized in that, The specifications of this auxiliary switch are lower than those of the global switch or the local switch.

10. A signal sampling method, characterized in that, Include: A global switch is selectively turned on according to a first control signal to transmit an input signal; A local switch is selectively turned on according to a second control signal to transmit the input signal from the global switch to a node, wherein a storage circuit is coupled to the node to store the input signal; as well as An auxiliary switch is selectively turned on according to a third control signal to transmit the input signal to the node, wherein the off time of the auxiliary switch is set to be earlier than or the same as the off time of the global switch. The local switch is set to turn off at a time later than the global switch.

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