System and method for controlling a low dropout regulator

Abstract

The present invention relates to systems and methods for controlling a low dropout regulator. A system and method for controlling a low dropout regulator (LDO) is disclosed. The system and method includes a charge pump that is controlled to provide a charge pump voltage to power the LDO. The charge pump voltage can be adjusted relative to an input voltage of the LDO to ensure effective operation of the LDO for a range of input voltages. The charge pump is also controlled to limit a maximum charge pump voltage provided to ensure safe operation of the LDO. The system and method also includes an under-voltage lockout circuit that enables the LDO when it is determined that the charge pump voltage is sufficient to meet a plurality of criteria. For example, the charge pump voltage can be analyzed to determine if it is above a minimum voltage and also sufficiently above an output voltage of the LDO.

Description

[0001] Divisional application information

[0002] This application is a divisional application of the application for patent with the application date of December 30, 2019, the application number of “201911398489.1”, and the invention name of “System and method for controlling low dropout regulator”. The application number of the divisional application is “202111339593.2”, and the invention name of “System and method for controlling low dropout regulator”.

[0003] CROSS-REFERENCE TO RELATED APPLICATIONS

[0004] This patent application claims priority to U.S. Patent Application No. 16 / 513,978, filed July 17, 2019, which in turn claims the benefit of U.S. Provisional Patent Application No. 62 / 815,114, filed March 7, 2019, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0005] The present disclosure relates to low dropout regulators (i.e., LDOs), and more specifically to systems, circuits, and methods for generating voltages to power LDOs and for enabling / disabling LDOs to ensure safe and efficient operation. BACKGROUND

[0006] A low dropout regulator (i.e., LDO) is a voltage regulator with a low dropout (i.e., V IN -V OUT ~100 millivolts) that receives an unregulated input voltage (i.e., V IN ) and provides a regulated output voltage (i.e., V OUT ). Typically, an LDO includes a transistor device (e.g., N-type transistor) connected in series between an input and an output of the LDO. The LDO also includes a driver (i.e., error amplifier, gate driver, etc.) that operates in a feedback loop between the output of the LDO and a control terminal (e.g., gate) of the transistor device. An output of the driver is coupled to the control terminal to adjust an operating point of the transistor device for regulation. The other two terminals (e.g., drain, source) of the transistor device are connected to the input and the output of the LDO, respectively. The driver controls the voltage drop across the transistor device based on feedback to regulate the output voltage of the LDO. SUMMARY

[0007] In one general aspect, the present disclosure describes a regulator system. The regulator system includes an LDO configured to receive an input voltage and provide a regulated output voltage. The system also includes a charge pump configured to power the LDO and a charge pump control circuit configured to control the charge pump. Specifically, the charge pump is controlled to output a charge pump voltage that (i) is higher than the input voltage and (ii) does not exceed a maximum voltage. The system also includes an under-voltage lockout (UVLO) circuit configured to enable the LDO when the charge pump voltage (i) is higher than a minimum voltage for operation of the LDO (i.e., a minimum voltage expected at the input plus a voltage to ensure operation of transistor devices in the LDO) and (ii) is sufficient to ensure operation of the transistor devices (i.e., is higher than the output voltage by a certain voltage).

[0008] In another general aspect, the present disclosure describes a circuit for controlling an LDO. The circuit includes a charge pump control circuit configured to receive an input voltage from an input terminal of the LDO and also receive a charge pump voltage from a charge pump (i.e., from an output terminal of the charge pump). The charge pump control circuit controls the charge pump as a function of the input voltage and the charge pump voltage. The charge pump voltage provides power to the LDO. The circuit also includes a UVLO circuit configured to receive the charge pump voltage and enable the LDO when the charge pump voltage satisfies a plurality of conditions (i.e., criteria).

[0009] In another general aspect, the present disclosure describes a method for controlling an LDO. The method includes receiving an input voltage from an input of the LDO and receiving a charge pump voltage from an output of a charge pump. The charge pump voltage is adjusted (e.g., changed) based on the received input voltage and the received charge pump voltage. The adjusted charge pump voltage is then provided to the LDO for powering (i.e., as a voltage rail for operation of the LDO). Additionally, the method includes determining that the adjusted charge pump voltage satisfies a plurality of conditions. Based on the determination, the LDO is enabled to operate.

[0010] The foregoing illustrative summary, together with other exemplary objectives and / or advantages of the present disclosure, and embodiments thereof, are further described in the following detailed description and appended claims. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 is a block diagram of a regulator system in accordance with embodiments of the present disclosure.

[0012] Figure 2 is a block diagram of a low dropout regulator that can be used with the system of Figure 1 .

[0013] Figure 3 is a block diagram of a low dropout regulator that can be used with the system of Figure 1schematic diagram of a charge pump usable with the system of

[0014] Figure 4 schematic diagram of a charge pump control circuit usable with the system of Figure 1

[0015] Figure 5 schematic diagram of an under-voltage lockout (UVLO) circuit usable with the system of Figure 1

[0016] Figure 6 schematic diagram of a possible circuit implementation of the regulator system of Figure 1

[0017] Figure 7 flowchart of a method for controlling a low-dropout regulator according to an embodiment of the present disclosure.

[0018] The components in the drawings are not necessarily drawn to scale relative to each other. Like reference numerals designate corresponding parts throughout the several views. DETAILED DESCRIPTION

[0019] Figure 1 A block diagram of a regulator system 100 according to an embodiment of the present disclosure is shown schematically. The system 100 can be configured to receive an input voltage (V IN ) and a ground voltage (GND) at respective input terminals. The system 100 can be configured to transmit (i.e., output) an output voltage (V OUT ) at an output terminal. The output voltage is regulated such that variations (e.g., fluctuations) in the input voltage are not reflected in the output voltage. The output voltage is lower (i.e., smaller) than the input voltage by a voltage drop (i.e., V DO = V IN -V OUT ).

[0020] The system 100 includes a low-dropout regulator (i.e., LDO) 110 configured to regulate the output voltage (V OUT ) to be less than the input voltage (V IN ) within a small voltage drop (e.g., V DO ≤ 100 millivolts (mV)). The LDO 110 dissipates power during the regulation. The dissipated power is proportional to the voltage drop (V DO ). Thus, reducing V DO can reduce the regulation loss and reduce the heat dissipation requirement.

[0021] Figure 2 ​​​A block diagram of a possible LDO 110 is shown. The LDO 110 includes a transistor device 111. The transistor device 111 can be implemented using various transistor types (e.g., BJT, MOSFET, JFET, etc.). For example, the transistor device 111 can be an N-channel MOSFET or a P-channel MOSFET. In fact, an N-channel MOSFET LDO offers advantages over other types of transistor devices. For example, an N-channel MOSFET LDO can provide a lower dropout voltage (i.e., V0) than a P-channel MOSFET LDO. DO Therefore, although the transistor device 111 disclosed herein is not limited to any particular transistor type or technology, an N-channel enhancement mode MOSFET will be described as transistor device 111.

[0022] The regulation can be achieved by controlling the voltage drop across transistor device 111. For example, the voltage drop between the drain terminal (D) 112 and the source terminal (S) 113 of the N-channel MOSFET can be controlled by the voltage applied to the gate terminal (G) 114 of the N-channel MOSFET.

[0023] The LDO 110 includes a drive circuit (i.e., a driver) 115 to provide a voltage at the gate terminal 114 of the transistor device 111. The driver 115 can be configured to receive an output voltage (V) via a feedback loop 116 formed between the driver 115 and the transistor device 111. OUT Driver 115 can also be configured to receive a reference voltage (V). REF When enabled, the driver can be used to measure the difference between the reference voltage and the output voltage (i.e., V). REF -V OUT ) output voltage (V G A differential amplifier. The driver's output voltage V G A gate 114 can be applied to the transistor device 111 to control the transistor's operating point (i.e., its on-state and its voltage drop (V)). DO )wait).

[0024] Driver 115 passes through high voltage (V CHP The driver is powered by both high rail (i.e., high rail) and low rail (GND) for operation. The low rail (GND) of the driver can also be V. IN The reference voltage. In other words, the LDO and the input voltage share the same voltage domain. To provide full control over transistor device 111, V CHP It can be higher than the input voltage V IN For example, if the input voltage V IN The voltage is 1 volt (V) (i.e., at the drain terminal 112) and the voltage difference is 0.1V (i.e., V).IN = 1 V, V DO = 0.1 V), the voltage at the output of the transistor device (i.e., at the source terminal 113) can be 0.9 V (i.e., V OUT = 0.9 V). To turn on (i.e., operate in the on state) the transistor device 111, the voltage at the output of the driver 115 can be at least 0.9 V plus the threshold voltage (V T ) of the transistor device 111. For a threshold voltage (i.e., V T = 0.7), the driver outputs a voltage of at least 1.6 V (i.e., V G > 1.6 V). Thus, the driver can be powered by a high voltage that enables the driver to output at least 1.6 V. Thus, in embodiments of the LDO 110, the high voltage provided to the driver 115 is configured to be higher than the input voltage (i.e., V CHP > V IN ). A high voltage (V IN ) configured as a single value higher than all expected input voltages (V CHP ) can be inefficient (e.g., when V IN is low) and can result in increased cost and / or size. The circuits and methods of the present disclosure advantageously provide for efficient operation based on an upper limit value (V IN ) of the input voltage (V CHP ).

[0025] The driver 115 can be enabled for operation by an enable signal EN. The enable signal EN can be a digital signal whose low voltage (i.e., logic zero) disables operation of the driver 115 and whose high voltage (i.e., logic one) enables operation of the driver 115 (or vice versa). The enable signal can be used to shut down the LDO 110 in the event that the voltage drops below a desired (e.g., target, threshold) value. This control can be used to protect (e.g., devices coupled to the system 100). The circuits and methods of the present disclosure advantageously utilize multiple criteria to determine the state of the enable signal EN.

[0026] Returning to Figure 1 , the system 100 also includes a charge pump 130 and charge pump control circuit 140 to generate the high voltage V CHP , and an under voltage lockout circuit 120 to generate the enable signal EN.

[0027] Figure 3Examples of charge pump circuits are shown. The example charge pump circuits shown are provided to aid in understanding and are not limiting examples of the present disclosure. The systems, circuits, and methods disclosed herein can be used with other charge pump types and architectures. For example, one possible implementation of a charge pump suitable for use in system 100 is disclosed in U.S. Patent Application 16 / 183,844, which is incorporated by reference herein in its entirety. In the present disclosure, a charge pump circuit similar to that shown in Figure 3 is described. However, the charge pump circuit includes input switches and output switches that are individually controlled by different clock signals to alternatively couple the tank capacitors to the input and output. The individual switching control allows the use of clock signals that do not have overlapping transitions to improve conversion efficiency. In addition, the input switches are controlled by clock signals that are level shifted with respect to the input voltage. The level shifted switching control also improves efficiency and allows the range of input voltages to be accommodated for DC voltage conversion.

[0028] Charge pump 130 is a cross-coupled symmetric charge pump that receives an input voltage V IN and generates a high voltage V CHP for powering system 100, e.g., driver 115. The voltage increase is achieved by charging and discharging a pair of capacitors C1, C2 using a network of transistors that operate as switches controlled by a clock signal (CLK) and its inverse (CLK-i). For example, when CLK is a high signal and CLK-i is a low signal, then transistors M1 and M3 are ON (i.e., conductive) and transistors M4 and M2 are OFF (i.e., non-conductive). In this state, capacitor C1 is coupled to the input and charged by V IN . When CLK is a low signal (e.g., GND) and CLK-i is a high signal, then transistors M1 and M3 are OFF and transistors M4 and M2 are ON. In this state, capacitor C1 is coupled to the output. By alternatively charging and discharging the respective capacitors (C1, C2), V IN is generated at a value higher than V CHP . The exact upper value depends on the clock signals (CLK, CLK-i). For example, the frequency of the clock signals can correspond to the voltage (V CHP ) at the output of the charge pump.

[0029] To control the charge pump voltage V CHP , as shown in Figure 1 , system 100 can include a charge pump control circuit 140. The charge pump control circuit controls the charge pump 130 to generate the charge pump voltage (V IN ) based on the input voltage (V CHPThe generated charge pump voltage (V) CHP The amplitude is adjusted to exceed the input voltage (V). IN V CHP The exact value and / or V CHP The relationship with VIN can be based on V IN (e.g., 1.1V to 3.6V) range of operation (e.g., stability, efficiency). In some embodiments, the charge pump control circuit 140 may also be configured to control the charge pump voltage (V) within a range of 1.1V to 3.6V. CHP The voltage is limited to the maximum voltage (V). CHPMAX To prevent damage (e.g., as determined by the process safe operating area (SOA)).

[0030] Figure 4 A block diagram of a possible charge pump control circuit 140 is shown. The charge pump control circuit 140 can be configured to control the charge pump based on the received voltage (V). IN V CHP This generates / controls the clock signal (CLK, CLK-i) of the charge pump. For example, the amplitude of the clock signal (CLK, CLK-i) can be equal to the received input voltage (V). IN The amplitude of the clock signal (CLK, CLK-i). Alternatively, or as another option, the frequency of the clock signal (CLK, CLK-i) can be determined based on the received input voltage (V). IN The frequency of the clock signal is adjusted proportionally to the amplitude of the charge pump. The charge pump control circuit 140 can also be configured to limit the frequency of the clock signal to a maximum value to prevent damage to the charge pump and / or to prevent the charge pump's output (V) from being interrupted. CHP Damage to other circuits.

[0031] like Figure 4 As shown, the charge pump control circuit may include a voltage sensing stage 141. The voltage sensing stage (i.e., the circuit) is configured to generate a voltage relative to V. CHP The floating voltage level. Therefore, the voltage sensing stage may include a voltage divider or voltage regulation device (i.e., a voltage reference source) to provide a voltage level relative to V. IN and / or V CHP Set one or more voltages. This may help to make V IN and V CHP The voltage level is adapted to other voltage domains.

[0032] The charge pump control circuit 140 also includes a differential amplifier 142 configured to perform one or more (e.g., two) comparisons. A first comparison 146 will be compared with V... CHP and V IN The relevant relative amplitudes are compared. The second comparison 147 compares V... CHPthe relative magnitude of V CHP to the maximum voltage for safe and / or normal functioning of the charge pump. Differential amplifier 142 can respond to the comparison in different ways. For example, determining that V CHP is equal to or above the maximum voltage can cause the amplifier to ignore (i.e., suppress) the first comparison. Whereas when the second comparison determines that V CHP is below the maximum voltage, then the output of the amplifier can be determined by the relationship between V IN and V IN (i.e., by the first comparison).

[0033] Differential amplifier 142 drives a voltage controlled oscillator (VCO) 143. The VCO is configured to receive an input voltage and generate an oscillating signal having a frequency that is proportional to the voltage at the input of the VCO (e.g., V CHP -V CHP ). The charge pump control circuit also includes clock logic 145 that receives the oscillating signal from the VCO and generates a corresponding digital clock signal (CLK) and a complementary (i.e., inverted) clock signal (CLK-i). The clock signals control the charge pump 130, as previously described.

[0034] Charge pump 130 and charge pump control circuit 140 can operate together to produce a voltage (V IN ) that is relatively high (i.e., regardless of how V IN varies) compared to the input voltage (V CHPMAX ) but less than (or equal to) a maximum voltage (V CHP ). The maximum voltage can be selected to correspond to the maximum voltage rating of the device technology of the LDO.

[0035] As shown in FIG. 1, system 100 can include an under-voltage lockout (UVLO) circuit 120. Generally, UVLO circuit 120 (via an enable signal EN) disables operation when the charge pump voltage (V CHPMIN ) is at or below a minimum voltage (V CHP ). In other words, a single criterion is used to determine whether to enable or disable driver 115. One advantageous aspect of the disclosed UVLO circuit is that it can use multiple criteria and logic to determine whether to enable or disable driver 115. For example, the UVLO circuit can additionally determine that the charge pump voltage (V CHP ) is above the output voltage of LDO 110 by a certain amount, then enable operation of the driver to ensure that transistor device 111 can be controlled.

[0036] Figure 5 A block diagram of a possible implementation of UVLO circuit 120 is shown in FIG. 2. The UVLO circuit receives the charge pump voltage (V CHP) and outputs an enable signal (EN). The enable signal can be a digital signal EN that, based on its state (e.g., high / low, 1 / 0, etc.), can enable / disable operation of the driver 115 of the LDO 110. The UVLO circuit 120 includes a voltage sensing stage (i.e., voltage sensing circuit, voltage sense) that receives, creates, and / or manipulates voltages for comparison. Thus, the voltage sense 121 can include circuitry (e.g., voltage source, regulator, voltage reference source, etc.) to output a voltage level relative to (floating) another voltage level (e.g., V CHP ) and / or output a voltage relative to a ground voltage. The UVLO circuit can provide one or more output voltages to a comparison stage (i.e., comparison circuit, compare) for comparison. Thus, the compare 123 can include circuitry for determining a relative voltage state. For example, a comparator can be used to indicate that a first voltage is higher than a second voltage. The compare 123 outputs one or more signals (e.g., digital signals) indicating the results of the voltage level comparison. The UVLO circuit also includes a logic stage (e.g., logic circuit, logic). The logic 125 can include one or more logic gates (e.g., inverter, AND, OR, XOR, etc.) that generate an enable signal (EN) based on a logical analysis of one or more results applied to the compare 123. Thus, the state (high / low, 1 / 0, ON / OFF) of the enable signal can be based on the (one or) more criteria. To avoid confusion, it can be noted that other enable signals are possible for a regulator system. For example, an enable signal (e.g., externally applied) can be used to control the overall operation of the regulator system. The enable signal (EN) described herein is a signal generated within the regulator system and applied to control the driver. Naming this signal as “enable” (i.e., EN) should not be understood as a replacement or exclusion of other possible enable signals for other (e.g., different) purposes.

[0037] Figure 6 For Figure 1 a schematic diagram of a possible implementation of a regulator system. The system includes a regulator having a NMOS switching device with a drain terminal (D), a source terminal (S), and a gate terminal (G). The gate terminal is coupled to and receives a voltage from a driver circuit 115. The voltage at the gate terminal (G) controls the conduction between the drain terminal (D) and the source terminal (S) such that the voltage at the source terminal (i.e., V OUT ) is lower than the voltage applied to the input terminal (i.e., V IN ) by a voltage difference. The voltage at the source terminal (i.e., V OUT ) is fed back to the input of the driver where an amplifier (i.e., differential amplifier, error amplifier) compares this voltage to a reference voltage generated by an internal voltage reference source.

[0038] The driver 115 is provided with a voltage (i.e., VCHP ) to power the LDO. The magnitude of the charge pump voltage is controlled by a (complementary) clock signal coupled from clock logic 145 to the charge pump. Specifically, VCO 143 can control the clock signal to adjust the charge pump voltage (V IN ) based on the input voltage (V CHP ), as long as V CHP does not exceed a maximum voltage. The control of the VCO is performed by differential amplifier 142, which is configured to receive four input signals (i.e., two input pairs) for comparison. One of the input sections of differential amplifier 142 is coupled to a voltage divider comprising first resistor R1 and second resistor R2. Another of the input sections of differential amplifier is coupled to first voltage reference source VI, second voltage reference source V2, and current source 608. In one possible implementation, the first voltage reference source VI, the second voltage reference source V2, and the current source can be implemented as resistors coupled in series with a transistor device.

[0039] Differential amplifier 142 receives four input signals: V IN , (V CHP -V1-V2), V4, and V CHP *R2 / (R1+R2). The amplifier can be implemented as a four-input operational amplifier (i.e., opamp) comprising two differential stages. The first differential stage is used for the maximum allowed charge pump voltage V4*(1+R1 / R2). V4 is the voltage generated by the voltage divider when the charge pump voltage is maximum. Since it is not possible to directly compare the charge pump voltage, a voltage divider is used.

[0040] The second differential stage is used to compare V IN to Vchp-V1-V2. VI is a floating voltage referred to as V CHP , and represents the minimum voltage difference (e.g., 1V) between the gate terminal (G) and the source terminal (S) of a transistor device (e.g., power NMOS) to provide sufficient output current. V2 is a voltage reference source (e.g., 0.3V) floating between the V CHP voltage and VI.

[0041] Driver 115 is enabled by a digital signal (EN) determined by UVLO circuit 120. The UVLO circuit receives the charge pump voltage (V CHP ). The UVLO circuit 120 comprises a voltage reference source (VI) (e.g., a Zener diode) that is the minimum voltage difference (e.g., ~1V) between the gate terminal (G) and the source terminal (S) of a transistor device (e.g., power NMOS) to provide sufficient current at the LDO output. The UVLO circuit 120 comprises a voltage reference source (V CH) greater than the minimum charge pump voltage, V3. In other words, V3 is the minimum charge pump voltage for the minimum input voltage (V IN ) of 1.1V. CHP_MIN ) of 2.2V. The UVLO circuit 120 also includes a second comparator 604 that outputs a logic high signal when the charge pump voltage (V CHP ) is greater than the input voltage (i.e., the voltage at the source (S) terminal) by an amount sufficient to turn on (i.e., turn on) the power NMOS transistor 111. The UVLO circuit includes an AND gate 601 that outputs a logic high when both conditions determined by the comparators 604, 605 are true. Thus, if the charge pump voltages are both greater than the minimum voltage and sufficient to control the NMOS transistor 111, then the driver is enabled. In some embodiments, the UVLO circuit can include delay circuits 602, 603 at the inputs of the AND gate to prevent instability.

[0042] Figure 6 Some conditions of the system shown in FIG. 6 are summarized in Table 1 below.

[0043] Table 1: Conditions for controlling the regulator system of FIG. 6 Figure 6

[0044]

[0045] In the following, a particular operating scenario is described as an example to help understanding. In this scenario, the transistor device 111 is an N-channel MOSFET with a safe operating area (SOA) of 3.6V, a threshold voltage of 0.7V, and an ON voltage of 1.3V at 4 amperes. In the operating scenario, 1.1V < V IN < 3.6V. In the operating scenario, V1 = 1V, V2 = 0.3V, V3 = 2.2V, and V4 = 0.8V.

[0046] In the operating scenario, V OUT is initially zero. When the input voltage V IN is applied to the LDO, the charge pump is activated and increases the V CHP voltage to a level determined by the charge pump control circuit 140 (i.e., the differential amplifier 142). The charge pump voltage is monitored by the UVLO circuit. When V CHP is greater than V OUT by V1 (i.e., V CHP - V OUT > 1V) and when V CHP is higher than the minimum voltage level V3 (i.e., V CHP > 2.2V), then the UVLO circuit enables the LDO driver (i.e., EN = logic high).

[0047] ​In an operating scenario, the differential amplifier 142 controls the VCO such that V CHP is higher than V IN (i.e., V CHP = V IN + 0.3 + 1.0). The charge pump can be controlled to output even higher voltages for operation, but this would be inefficient because power consumption increases with oscillator frequency. Thus, an advantage of the disclosed system and method is to control V IN to achieve efficient operation based on V CHP . In other words, V CHP tracks V IN at a voltage that is suitable for LDO regulation but not so high as to result in inefficiency because the tracking results in no need to select a V IN that is higher than one of all possible V CHP .

[0048] In an operating scenario, as V IN increases, V IN + 1.3V can be greater than the safe operating area (SOA) voltage of 3.6V for transistor technology. In this case, the voltage across resistor R2 exceeds V4. The second differential stage of the differential amplifier 142 is turned off and the frequency is reduced such that the charge pump voltage is clamped at the steady voltage maximum of 3.6V. The voltage across resistor R2 can be used to regulate the input voltage of the differential amplifier 142 to be within the operating voltage range of the amplifier.

[0049] In an operating scenario, the first comparator 605 determines whether the charge pump voltage exceeds 2.2V (i.e., the minimum charge pump voltage). The system can receive an input voltage in the range of 1.1V to 3.6V. The minimum input voltage is 1.1 volts, which means that to achieve efficient operation, the minimum charge pump voltage is 1.1V + 1.3V = 2.4V (i.e., V IN + V1+ V2). To protect against the effects of voltage spikes, this voltage can be slightly decreased (e.g., 0.2V), resulting in a minimum charge pump voltage (i.e., V3) of 2.2V for all conditions.

[0050] In an operating scenario, the second comparator ensures that the charge pump voltage V CHP exceeds V OUT by at least 1V (i.e., V1). This condition ensures that the minimum voltage difference between the gate (G) and source (S) of the power NMOS provides sufficient output current.

[0051] The system combines the ground condition and the floating condition of the under-voltage lockout to ensure efficient charge pump operation in the best mode of the LDO regulator. The applied conditions drive the charge pump output relative to V INthe LDO's input (i.e., V IN ) by at least a minimum voltage. The imposed conditions also ensure that the charge pump voltage is at a certain voltage level above the LDO's output (i.e., V OUT ). The imposed conditions use floating voltages (i.e., V1, V2) that are referenced to the charge pump voltage.

[0052] Figure 7 A flowchart showing one possible implementation of a method for controlling a low dropout regulator (LDO) is shown in FIG. 7. In the method 700, an input voltage V IN and a charge pump voltage (V CHP ) are received 710 (e.g., by the charge pump control circuit 140). Based on V IN and V CHP , the charge pump is controlled to adjust (e.g., raise, lower, hold) the charge pump voltage (V CHP ) and provide 730 (i.e., couple, transfer) the adjusted charge pump voltage to the LDO for powering (to energize and operate the circuit). In addition, it is determined (e.g., by the UVLO circuit 120) whether the adjusted V CHP satisfies a plurality of conditions, and if so, the LDO is enabled 750, otherwise it is disabled 750.

[0053] In the description and / or drawings, typical embodiments have been disclosed. The disclosure is not limited to such exemplary embodiments. The use of the term "and / or" includes any and all combinations of one or more of the associated listed items. The drawings are schematic representations and, as such, are not necessarily drawn to scale. Unless otherwise stated, specific terms have been used in a generic and descriptive sense, and not for purposes of limitation.

[0054] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. Methods and materials similar or equivalent to those described herein can be used in the practice or testing of the present disclosure. As used in this specification and the appended claims, the singular forms "a," "an" and "the" include plural referents unless the content clearly dictates otherwise. It should also be understood that the endpoints of each of the ranges are significant, and that the endpoints are independent of one another.

[0055] It will be understood that, in the foregoing description, when an element such as a layer, region, substrate or component is referred to as being on another element, connected to another element, electrically connected to another element, coupled to another element, or electrically coupled to another element, it can be directly on, connected to, electrically connected to, or coupled to the other element, or one or more intervening elements can also be present. In contrast, when an element is referred to as being directly on, directly connected to, or directly coupled to another element, there are no intervening elements or layers present. While the terms directly on, directly connected to, or directly coupled to may not be used in the detailed description throughout the specification, elements described as directly on, directly connected to, or directly coupled to an element can be referred to in this manner. The claims of the present application, if any, can be amended to recite example relationships described in the specification or shown in the drawings.

[0056] As used in this specification, unless expressly stated otherwise, the singular form "a," "an," and "the" include plural referents. Spatially relative terms, such as "above," "on," "over," "under," "beneath," "below," "lower," "upward," "downward," "vertical," "horizontal," and the like, merely indicate the presence of a device in a direction relative to another device as illustrated in the orientation of the figures, unless specifically stated otherwise. In some embodiments, relative terms "above" and "below" can include vertically above and vertically below, respectively. In some embodiments, the term adjacent can include laterally adjacent or horizontally adjacent.

[0057] Some embodiments can be implemented using various semiconductor processing and / or packaging techniques. Some embodiments can be implemented using various types of semiconductor processing techniques associated with semiconductor substrates including, but not limited to, for example, silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), etc.

[0058] While certain features of described implementations have been illustrated as described herein, many modifications, substitutions, changes, and equivalents will now occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the scope of the implementations. It should be understood that they have been presented by way of example only, not limitation, and various changes in form and details can be made. Any portion of the apparatus and / or methods described herein can be combined in any combination, except for combinations that are mutually exclusive. The implementations described herein can include various combinations and / or sub-combinations of the functions, components and / or features of the different implementations described.

Claims

1. A voltage regulator system, comprising: A low-dropout regulator (LDO) configured to receive an input voltage at the input terminal of a transistor device and, when enabled, provide an output voltage at the output terminal of the transistor device, the LDO including a driver configured to compare the output voltage with a reference voltage, the driver being powered by a charge pump voltage that serves as the high rail voltage of the driver; and An undervoltage lockout circuit is configured to enable the driver when multiple voltage conditions are met, including the charge pump voltage being at least one voltage difference higher than the output voltage of the LDO, and the charge pump voltage being higher than a first threshold voltage. The voltage difference is the minimum voltage difference between the gate and source of the transistor device required to drive the transistor device to provide output current.

2. The voltage regulator system of claim 1, wherein the input voltage varies within a voltage range from the minimum input voltage to the maximum input voltage.

3. The voltage regulator system according to claim 2, further comprising: A charge pump, which is controlled by a charge pump control circuit configured to receive the input voltage and control the charge pump to output a charge pump voltage that is a fixed amount above the input voltage.

4. The voltage regulator system of claim 2, wherein the first threshold voltage is the minimum value of the charge pump voltage required to ensure the operation of the LDO when the input voltage is the minimum input voltage.

5. The voltage regulator system of claim 1, wherein the plurality of voltage conditions ensure that (i) the driver can turn on the transistor device; and (ii) the driver can control the transistor device to provide a predetermined current to the output terminal of the transistor device.

6. A method for voltage regulation, the method comprising: The input voltage is received at the input terminal of a low dropout regulator (LDO), the LDO including a driver powered by a charge pump voltage as a high rail voltage, the driver being configured to compare an output voltage at the output terminal of the LDO with a reference voltage, wherein the input voltage is variable within a voltage range from a minimum input voltage to a maximum input voltage; The LDO is powered by a charge pump voltage that floats above the input voltage; The driver is enabled when multiple voltage conditions are met, including a charge pump voltage that is at least one voltage difference higher than the output voltage and the charge pump voltage being higher than a first threshold voltage, wherein the voltage difference is the minimum voltage difference between the gate and source of the transistor device required to drive the transistor device to provide output current; and The output voltage is generated at the output terminal of the LDO.

7. The method for voltage regulation according to claim 6, wherein as the input voltage varies within the voltage range from the minimum input voltage to the maximum input voltage, the charge pump voltage floats above the input voltage by a fixed amount.

8. The method for voltage regulation according to claim 6, wherein: The first threshold voltage is the minimum value of the charge pump voltage required to ensure the operation of the LDO when the input voltage is the minimum input voltage.

9. A voltage regulator system, comprising: A low dropout regulator (LDO) configured to receive an input voltage at the input terminal of a transistor device and, when enabled, to provide an output voltage at the output terminal of the transistor device, the LDO including a driver configured to compare the output voltage with a reference voltage; A charge pump, controlled by a charge pump control circuit configured to receive the input voltage and control the charge pump to output a charge pump voltage as a high rail voltage to power the driver, wherein the charge pump voltage is a fixed amount above the input voltage as the input voltage varies within a voltage range from a minimum input voltage to a maximum input voltage; and An undervoltage lockout circuit is configured to enable the driver when multiple voltage conditions are met.

10. The voltage regulator system of claim 9, wherein the plurality of voltage conditions includes: The charge pump voltage is higher than a first threshold voltage, which is the minimum value of the charge pump voltage required to ensure the LDO operation when the input voltage is the minimum input voltage; and The charge pump voltage is at least one voltage difference higher than the output voltage of the LDO, the voltage difference being the minimum voltage difference between the gate and source of the transistor device required to drive the transistor device to provide output current.

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