Method for DDR debugging by using DDR parameter modeling

Abstract

The present invention discloses a method for DDR debugging by using DDR parameter modeling, which includes the following steps: S1, parameter search and input; S2, generate all timing parameters; S3, import the Python debugging tool; S4, power on the chip, run the Python debugging tool and view the configuration result; S5, start DDR training; S6, if the DDR training fails, repeat step S5; if the training passes, enter S7; S7, start DDR self-check; S8, if the DDR self-check is normal, the DDR debugging is completed; if the DDR self-check fails, return to S4 and start repeating S4-S7. Advantages: In the present invention, the parameter modeling tool is more general and convenient, does not require the installation of any software, and is not restricted by imported or domestic particles; the operation is simple; the Python debugging tool can intuitively display the configuration status of the parameters, modify and debug the DDR parameters step by step in an online manner, complete various DDR physical layer PHY trainings and perform read-write tests for self-checking.

Description

Technical Field

[0001] The present invention relates to a method for DDR debugging by using DDR parameter modeling. Background Art Technical Background

[0003] In an embedded system, the performance of DDR directly affects the performance of the product. Therefore, in system design, the signal integrity design of DDR and the timing parameter configuration during system debugging are particularly important. Understanding the working principle of DDR and correctly understanding the meaning of each parameter enable DDR to achieve the best configuration, providing a strong guarantee for the efficient and stable operation of the system.

[0004] Currently, DDR parameters are generated in a simulation verification environment. According to the DDR operating frequency and die model information, the SOMA file of the parameter configuration is first obtained. After decompressing the SOMA file, it is then converted into an XML format file. Finally, the verification tool uses a script to generate the configuration parameters in C or Verilog language under the simulation platform based on the XML format file. The chip bootloader sets the configuration parameters into the memory controller and debugs and runs.

[0005] Disadvantages of the traditional technology:

[0006] Memory parameters are limited by the simulation verification tool. Configuration parameters can only be generated for memory die models that can be recognized in the simulation verification tool library; domestic memory dies are not supported; the timing parameters under the simulation system need to be corrected and debugged according to the actual situation. Debugging of memory timing parameters requires the assistance of the bootloader, and the debugging efficiency is not high.

[0007] The DDR configuration parameters in the simulation verification environment cannot be directly used in the chip back-end test, and the delayed timing parameters need to be adjusted. For each debugging, the modified memory configuration parameters need to be synthesized into the startup code for running and debugging, and the DDR debugging process is time-consuming and difficult. Summary of the Invention

[0008] The present invention proposes a method for DDR debugging by using DDR parameter modeling, including the following steps:

[0009] S1. Parameter search and input;

[0010] S2. The parameter modeling tool generates all timing parameters;

[0011] S3. All the timing parameters generated in S2 are imported into the Python debugging tool;

[0012] S4. Power on the chip and run the Python debugging tool; all the timing parameters generated in S2 are used to automatically configure the chip's DDR timing parameters with the help of the Python debugging tool; when the DDR physical layer PHY initialization is completed and the external memory chip DRAM initialization is completed, it indicates the end of the configuration; and view the configuration result.

[0013] S5. When the DDR physical layer link status register shows correctly, it indicates the end of the configuration, and the Python debugging tool starts DDR training; when the write equalization WL, data strobe signal DQS, write equalization adjustment WLA, data read training RD, data write training WD, write eye diagram RE, write eye diagram WE, and static read data SDD in the DDR all show that the training is completed, it indicates that the training passes; otherwise, the training fails.

[0014] S6. If the DDR training fails, repeat step S5; if the training passes, enter S7.

[0015] S7. The Python debugging tool starts DDR self-check; when the physical layer data self-check PHY Data BIST, controller layer data self-check CTRL Data BIST, physical layer address self-check PHY Address BIST, and controller layer address self-check CTRL Address BIST in the DDR all show that they pass, it indicates that the DDR self-check is normal; otherwise, it indicates that the DDR self-check has an error.

[0016] S8. When the DDR self-check is normal, the DDR debugging is completed; when the DDR self-check has an error, return to step S4 and start repeating steps S4 - S7.

[0017] For further optimization of the technical solution of the present invention, when performing DDR training in S5, single-step debugging is also set. When the training fails, it is necessary to determine which training has a problem through single-step debugging, and modify the timing parameters again through the online interaction module in the Python debugging tool for debugging. After locating the problem, directly solve the problem through online modification.

[0018] For further optimization of the technical solution of the present invention, 9 parameters are input when looking up the chip manual in S1, which are: read latency CL, clock frequency tCK, latency from activation to read / write tRCD, precharge command period tRP, row address, column address, bank address, activation command interval tRRD, and 4 activation window intervals tFAW.

[0019] For further optimization of the technical solution of the present invention, the parameter modeling tool is completed by an Excel table. The input instructions of 9 key parameters are marked in the table header of the table. After the input is completed, the Excel table automatically generates the timing parameters of all DDR memory controllers and PHYs. The Excel table is more general and convenient as a parameter modeling tool. It does not require the installation of any software and is not restricted by imported or domestic particles; the operation is simple.

[0020] For further optimization of the technical solution of the present invention, the specific steps for generating timing parameters in S2 are as follows:

[0021] S2.1. Input the 9 parameters into columns A1-I1 of the Excel table;

[0022] S2.2. Import the timing formula required according to the DDR physical layer PHY manual into the Excel table;

[0023] S2.3. Import the timing formula required according to the DDR memory controller CTRL manual into the Excel table;

[0024] S2.4. The Excel table automatically generates the timing parameter values from columns A257 to I257;

[0025] S2.5. Export two columns of timing parameter values, one column is the DDR memory controller CTRL timing parameter, and the other column is the DDR physical layer PHY timing parameter.

[0026] The advantage of the specific steps for generating timing parameters in S2 is that the controller timing parameters and the physical layer timing parameters are automatically separated, which is convenient for timing problem positioning and subsequent code upgrade.

[0027] For further optimization of the technical solution of the present invention, the Python debugging tool includes a parameter configuration module, an online interaction module, a single-step debugging module, a training debugging module, and a self-check module. The parameter configuration module is responsible for configuring all the timing parameters generated by the parameter modeling tool according to the requirements of the parameter process. The online interaction module includes read and write interfaces, which directly read the status of the controller and the DDR physical layer through the read and write interfaces, and can modify the configuration parameters online. The training debugging module performs training and debugging on the write equalization WL, data strobe signal DQS, write equalization adjustment WLA, data read training RD, data write training WD, write eye diagram RE, write eye diagram WE, and static read data SDD of the DDR physical layer PHY and the controller to ensure the accuracy of data sampling during reading and writing. The single-step debugging module is an interface that cooperates with the DDR training debugging module. When the training fails, it determines which training has problems through single-step debugging, and modifies the parameters through the online interaction module to perform debugging again. The self-check module includes an address line test and a data line test. After the training passes, an internal read and write test is performed. It can intuitively and clearly know whether the currently configured timing parameters are accurate and available, and prepare for subsequent performance optimization.

[0028] For further optimization of the technical solution of the present invention, the parameter configuration process of the parameter configuration module is as follows:

[0029] 1) Configure the controller register,

[0030] 2) Release the controller core reset signal,

[0031] 3) Configure the PUB register,

[0032] 4) Wait for the DDR physical layer PHY to complete initialization,

[0033] 5) Wait for the external memory chip DRAM to complete initialization.

[0034] The advantage of the parameter configuration of the parameter configuration module is that it strictly follows the configuration process of the controller and physical layer timing parameters, removes unstable factors, and ensures reliability under known timing parameters.

[0035] Compared with the prior art, the present invention has the following beneficial effects:

[0036] 1. The method of the present invention uses an Excel table in combination with the DDR physical layer PHY manual and the DDR memory controller CTRL manual to automatically generate timing parameters suitable for the DDR physical layer PHY and the DDR memory controller CTRL.

[0037] 2. The method of the present invention uses the script interaction function of the python debugging tool, in combination with the online interaction module and the training module, to solve the single-step debugging function.

[0038] 3. After the training is completed, the method of the present invention uses the online interaction module to perform write and read operations on the memory address, and then judges the data to solve the online read-write test problem.

[0039] 4. The method of the present invention, the parameter modeling tool (Excel table) is more general and more convenient. It does not require the installation of any software and is not restricted by imported or domestic particles; the operation is simple.

[0040] 5. The method of the present invention, the python debugging tool adds a self-check module, increases the self-check function of the DDR physical layer PHY, and improves the reliability of system parameters.

[0041] 6. The method of the present invention, the python debugging tool can intuitively display the configuration status of the parameters, modify and debug the DDR parameters step by step in an online manner, complete various DDR physical layer PHY trainings, and perform self-check read-write tests. Description of the Drawings

[0042] Figure 1 is the debugging flowchart of the method of this embodiment.

[0043] Figure 2 is the module schematic diagram of the Python debugging tool in the method of this embodiment. Detailed Embodiments

[0044] The technical solution of the present invention will be described in detail below, but the protection scope of the present invention is not limited to the described embodiments.

[0045] To make the content of the present invention more obvious and understandable, the following is combined with the attached Figure 1 - attached Figure 2 and specific implementation manners for further description.

[0046] In order to make the purpose, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0047] As Figure 1 shown, this embodiment is a method for DDR debugging using DDR parameter modeling, including the following steps:

[0048] S1. Parameter search and input;

[0049] S2. The parameter modeling tool generates all timing parameters;

[0050] S3. All the timing parameters generated in S2 are imported into the Python debugging tool;

[0051] S4. Power on the chip and run the Python debugging tool; all the timing parameters generated in S2 are used to automatically configure the chip's DDR timing parameters with the help of the Python debugging tool; when the DDR physical layer PHY initialization is completed and the external memory chip DRAM initialization is completed, it indicates the end of the configuration; and view the configuration result;

[0052] S5. When the DDR physical layer link status register shows correctly, it indicates the end of the configuration, and the Python debugging tool starts DDR training; when the write equalization WL, data strobe signal DQS, write equalization adjustment WLA, data read training RD, data write training WD, write eye diagram RE, write eye diagram WE, and static read data SDD in the DDR all show that the training is completed, it indicates that the training has passed; otherwise, the training has not passed;

[0053] S6. If the DDR training fails, repeat step S5; if the training passes, proceed to S7;

[0054] S7. The Python debugging tool starts DDR self-check; when the physical layer data self-check PHY Data BIST, controller layer data self-check CTRL Data BIST, physical layer address self-check PHY Address BIST, and controller layer address self-check CTRL Address BIST in the DDR all show that they have passed, it indicates that the DDR self-check is normal; otherwise, it indicates that the DDR self-check has an error;

[0055] S8. When the DDR self-check is normal, the DDR debugging is completed; when the DDR self-check has an error, return to step S4 and start repeating steps S4 - S7.

[0056] In step S1, 9 parameters are found in the chip manual, namely: read latency CL, clock frequency tCK, latency from activation to read / write tRCD, precharge command cycle tRP, row address Row Address, column address Column Address, bank address BankAddress, activation command interval tRRD, and 4 activation window intervals tFAW.

[0057] The parameter modeling tool is completed by an Excel spreadsheet. The input instructions for the 9 key parameters are marked in the table header of the spreadsheet. After the input is completed, the Excel spreadsheet automatically generates all the timing parameters of the DDR memory controller and the DDR physical layer PHY.

[0058] The specific steps for the parameter modeling tool to generate timing parameters are as follows:

[0059] S2.1. Input the 9 parameters into columns A1 - I1 of the Excel spreadsheet;

[0060] S2.2. Import the timing formula according to the requirements of the DDR physical layer PHY manual into the Excel spreadsheet;

[0061] S2.3. Import the timing formula according to the requirements of the DDR memory controller CTRL manual into the Excel spreadsheet;

[0062] S2.4. Automatically generate the timing parameter values from column A257 to column I257 in the Excel spreadsheet, including the power-down exit time tXP, the minimum interval period tRRD between activation commands, the interval period tCCD between column commands, etc., a total of 451 timing parameters;

[0063] S2.5. Export two columns of timing parameter values, one column is the timing parameters of the DDR memory controller CTRL, and the other column is the timing parameters of the DDR physical layer PHY.

[0064] As Figure 2 shown, in this embodiment, the communication decoding function is integrated in the Python debugging tool, and the read / write memory register function is completed by using the communication protocol of the chip serial port. The normalization configuration function streamlines the DDR parameter configuration of the chip according to the standard logical process to ensure the effectiveness of the timing parameter configuration.

[0065] As Figure 2 shown, the Python debugging tool includes a parameter configuration module, an online interaction module, a single-step debugging module, a training debugging module, and a self-checking module. The parameter configuration module is responsible for configuring all the timing parameters generated by the parameter modeling tool according to the parameter process requirements; the online interaction module includes read / write interfaces, directly reads the status of the controller and the DDR physical layer through the read / write interfaces, and can modify the configuration parameters online; the training debugging module performs training and debugging on the write equalization WL, data strobe signal DQS, write equalization adjustment WLA, data read training RD, data write training WD, write eye diagram RE, write eye diagram WE, and static read data SDD of the DDR physical layer PHY and the controller to ensure the accuracy of data sampling during reading and writing; the single-step debugging module is an interface that cooperates with the DDR training debugging module. When the training fails, it determines which training has problems through single-step debugging and modifies the parameters through the online interaction module to perform debugging again; the self-checking module includes address line testing and data line testing, and performs internal read / write testing after the training passes.

[0066] The specific implementation method is as follows:

[0067] DDR parameters are specific to a particular frequency. The commonly used frequencies for DDR3 include the following: 800MHz, 1066MHz, 1333MHz, 1600MHz, 1866MHz. From the die manual, for the corresponding frequency information, the above 9 key timing parameter values can be obtained. Input these parameter values into the DDR parameter modeling tool, and the parameter modeling tool will automatically generate all the timing parameters required for the DDR memory controller and the DDR physical layer PHY. After the timing parameters are generated, they are imported into the Python debugging tool in a file manner. The Python debugging tool has implemented the decoding function of the chip serial port communication protocol, the normalization function of the chip DDR memory controller parameter configuration, and the running result display and single-step debugging functions. After the chip is powered on, set the dip switches to the programming and debugging mode, run the Python debugging tool, and it will download and configure the parameters generated by the parameter modeling tool into the chip DDR memory controller and the DDR physical layer PHY registers; check the configuration result, and after it is displayed correctly, start the DDR training. The DDR physical layer PHY training generally includes the write equalization WL, data strobe signal DQS, write equalization adjustment WLA, data read training RD, data write training WD, write eye diagram RE, write eye diagram WE, and static read data SDD training inside the DDR. For each training, there will be a status value indicating whether it is correct or incorrect. Adjust the parameter configuration of the training until all trainings are completed. Finally, start the DDR self-test. If the self-test passes, all DDR parameter debugging is completed. Example 1

[0068] The method of using DDR parameter modeling for DDR debugging has been completed and verified on the KWDSP chip. For DDR3, it has been successfully adapted to data rates of 1066MHz and 1333MHz. Taking the data rate of 1333MHz as an example: First, input the corresponding 9 parameter values at 1333MHz in an Excel spreadsheet, CL = 10, tCK = 1.5, tRCD = 13.5, tRP = 10, Row Address = 15, ColAddress = 10, Bank Address = 3, tRRD = 7, tFAW = 30; the following timing parameter table will be automatically generated, as shown in Table 1:

[0069] Table 1

[0070]

[0071] Import the timing parameters in Table 1 into the Python debugging tool for automatic configuration. After the DDR physical layer initialization is completed and the external memory die initialization is completed, check the configuration result. Then perform DDR training. After all trainings are correct, perform the self-test. The running results are shown in Table 2:

[0072] Table 2

[0073]

[0074] The parts not involved in the present invention are the same as or can be implemented by the prior art.

[0075] As described above, although the present invention has been shown and described with reference to specific preferred embodiments, it should not be construed as a limitation on the present invention itself. Various changes in form and detail may be made without departing from the spirit and scope of the present invention as defined by the appended claims.

Claims

1. A method for DDR debugging using DDR parameter modeling, characterized in that, It includes the following steps: S1. Parameter search and input; S2. The parameter modeling tool generates all timing parameters; S3. All the timing parameters generated in S2 are imported into the Python debugging tool; S4. Power on the chip and run the Python debugging tool; all the timing parameters generated in S2 are used to automatically configure the chip's DDR timing parameters with the help of the Python debugging tool; when the initialization of the DDR physical layer PHY is completed and the initialization of the external memory chip DRAM is completed, it means the configuration is finished; and view the configuration result; S5. When the DDR physical layer link status register shows correctly, it means the configuration is finished, and the Python debugging tool starts DDR training; when the write equalization WL, data strobe DQS, write equalization adjustment WLA, data read training RD, data write training WD, write eye diagram RE, write eye diagram WE, and static read data SDD in the DDR all show that the training is completed, it means the training passes; otherwise, the training fails; S6. If the DDR training fails, repeat step S5; if the training passes, proceed to S7; S7. The Python debugging tool starts DDR self - test; when the physical layer data self - test PHY Data BIST, controller layer data self - test CTRL Data BIST, physical layer address self - test PHY Address BIST, and controller layer address self - test CTRL Address BIST in the DDR all show passing, it means the DDR self - test is normal; otherwise, it means the DDR self - test has an error; S8. When the DDR self - test is normal, the DDR debugging is completed; when the DDR self - test has an error, return to step S4 and start repeating steps S4 - S7; Among them, 9 parameters are searched and input from the chip manual in S1, which are: read latency CL, clock frequency tCK, latency from activation to read / write tRCD, pre - charge command period tRP, row address, column address, bank address, activation command interval tRRD, and 4 activation window intervals tFAW; In S2, the parameter modeling tool is completed by an Excel spreadsheet. The input instructions for 9 key parameters are marked in the spreadsheet header. After the input is completed, the Excel spreadsheet automatically generates all the timing parameters of the DDR memory controller and the DDR physical layer PHY; The specific steps for generating the timing parameters in S2 are as follows: S2.

1. Input the 9 parameters into columns A1 - I1 of the Excel spreadsheet; S2.

2. Import the timing formula required according to the DDR physical layer PHY manual into the Excel spreadsheet; S2.

3. Import the timing formula required according to the DDR memory controller CTRL manual into the Excel spreadsheet; S2.

4. The Excel spreadsheet automatically generates the timing parameter values from columns A257 to I257; S2.

5. Export two columns of timing parameter values, one column is the DDR memory controller CTRL timing parameters, and the other column is the DDR physical layer PHY timing parameters.

2. The method for DDR debugging using DDR parameter modeling according to claim 1, wherein When performing DDR training in S5, single-step debugging is also set. When the training fails, it is necessary to determine which training has problems through single-step debugging and modify the timing parameters through the online interaction module in the Python debugging tool to perform debugging again.

3. The method for DDR debugging by using DDR parameter modeling according to claim 1, wherein The Python debugging tool includes a parameter configuration module, an online interaction module, a single-step debugging module, a training debugging module, and a self-check module. The parameter configuration module is responsible for configuring all the timing parameters generated by the parameter modeling tool according to the requirements of the parameter process. The online interaction module includes read and write interfaces, which directly read the status of the controller and the DDR physical layer through the read and write interfaces and can modify the configuration parameters online. The training debugging module performs training debugging on the write equalization WL, data strobe signal DQS, write equalization adjustment WLA, data read training RD, data write training WD, write eye diagram RE, write eye diagram WE, and static read data SDD of the DDR physical layer PHY and the controller to ensure the accuracy of data sampling during reading and writing. The single-step debugging module is an interface that cooperates with the DDR training debugging module. When the training fails, it determines which training has problems through single-step debugging and modifies the parameters through the online interaction module to perform debugging again. The self-check module includes address line testing and data line testing. After the training passes, internal read and write tests are performed.

4. The method for DDR debugging by using DDR parameter modeling according to claim 3, characterized in that The parameter configuration process of the parameter configuration module is as follows: 1) Configure the controller register. 2) Release the controller core reset signal. 3) Configure the PUB register. 4) Wait for the DDR physical layer PHY to complete initialization. 5) Wait for the external memory chip DRAM to complete initialization.

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