Gate driving circuit, driving method thereof and display panel

Abstract

The application provides a gate driving circuit and a driving method thereof and a display panel, and relates to the technical field of display, which can improve the refresh rate and response speed of a display product while reducing power consumption. The gate driving circuit comprises m shift register units and m selectors; the nth selector is coupled with the input end of the nth shift register unit, the output end of the (n-1)th shift register unit, the controllable signal input end, the reset signal input end and the address signal input end; the nth selector is used for controlling the nth selector to input the (n-1)th output signal provided by the output end of the (n-1)th shift register unit under the joint control of the reset signal provided by the reset signal input end and the address signal provided by the address signal input end, and outputting the (n-1)th output signal to the input end of the nth shift register unit, or controlling the nth selector to input the controllable signal provided by the controllable signal input end and output the controllable signal to the input end of the nth shift register unit.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a gate driving circuit and its driving method, and a display panel. Background Technology

[0002] To meet the narrow bezel requirements of display products, these products typically employ Gate On Array (GOA) technology. GOA-based displays drive signals by shifting them down through each stage. However, as display demands for refresh rates and response times increase, GOA-based products, while achieving these high refresh rates and response times, experience significant power consumption. Summary of the Invention

[0003] The purpose of this invention is to provide a gate driving circuit and its driving method, as well as a display panel, for improving the refresh rate and response speed of display products while reducing the power consumption of display products.

[0004] To achieve the above objectives, the present invention provides the following technical solution:

[0005] A first aspect of the present invention provides a gate driving circuit, comprising: m shift register units and m selectors, where m is an integer greater than 1;

[0006] The nth selector is coupled to the input terminal of the nth shift register unit, the output terminal of the (n-1)th shift register unit, the controllable signal input terminal, the reset signal input terminal, and the address signal input terminal, respectively, where 1 < n ≤ m; the nth selector is used to: under the joint control of the reset signal provided by the reset signal input terminal and the address signal provided by the address signal input terminal, control the nth selector to input the (n-1)th output signal provided by the output terminal of the (n-1)th shift register unit, and output the (n-1)th output signal to the input terminal of the nth shift register unit; or, control the nth selector to input the controllable signal provided by the controllable signal input terminal, and output the controllable signal to the input terminal of the nth shift register unit.

[0007] Optionally, the nth selector includes a selection control circuit and an input selection circuit;

[0008] The selection control circuit is coupled to the reset signal input terminal and the address signal input terminal respectively, and is used to output an enable signal from the output terminal of the selection control circuit according to the reset signal and the address signal;

[0009] The input selection circuit is coupled to the output terminal of the (n-1)th shift register unit, the controllable signal input terminal, and the output terminal of the selection control circuit, respectively. Under the control of the enable signal, it controls the nth selector to input the (n-1)th output signal provided by the output terminal of the (n-1)th shift register unit and outputs the (n-1)th output signal to the input terminal of the nth shift register unit; or, it controls the nth selector to input the controllable signal provided by the controllable signal input terminal and outputs the controllable signal to the input terminal of the nth shift register unit.

[0010] Optionally, the selection control circuit includes:

[0011] The address selection sub-circuit is coupled to the address signal input terminal and is used to control the output terminal of the address selection sub-circuit to output a first selection signal according to the address signal.

[0012] A first OR gate logic sub-circuit, wherein the first input terminal of the first OR gate logic sub-circuit is coupled to the reset signal input terminal, and the second input terminal of the first OR gate logic sub-circuit is coupled to the output terminal of the address selection sub-circuit, is used to output a second selection signal from the output terminal of the first OR gate logic sub-circuit according to the reset signal and the first selection signal.

[0013] Optionally, the input selection circuit includes:

[0014] The first NOT gate logic sub-circuit, wherein the input terminal of the first NOT gate logic sub-circuit is coupled to the output terminal of the first OR gate logic sub-circuit;

[0015] The first AND gate logic sub-circuit has a first input terminal coupled to the controllable signal input terminal, and a second input terminal coupled to the output terminal of the first OR gate logic sub-circuit.

[0016] The second AND gate logic sub-circuit has its first input terminal coupled to the output terminal of the NOT gate logic sub-circuit, and its second input terminal coupled to the output terminal of the (n-1)th shift register unit.

[0017] The second OR gate logic sub-circuit has its first input terminal coupled to the output terminal of the first AND gate logic sub-circuit, its second input terminal coupled to the output terminal of the second AND gate logic sub-circuit, and its output terminal coupled to the input terminal of the nth shift register unit.

[0018] Optionally, the address signal input terminal includes multiple address signal ports;

[0019] The address selection sub-circuits included in each selector are different, and the address selection sub-circuit includes:

[0020] The third AND gate logic sub-circuit, the output of which serves as the output of the address selection sub-circuit, includes multiple input terminals. Each input terminal of the third AND gate logic sub-circuit is coupled to the corresponding address signal port through the second NOT gate logic sub-circuit, or directly coupled to the corresponding address signal port.

[0021] Based on the technical solution of the above-described gate driving circuit driving method, a second aspect of the present invention provides a driving method for a gate driving circuit, used to drive the gate driving circuit, the driving method comprising:

[0022] In normal operating mode, the reset signal input to the reset signal input terminal is at an inactive level, the address signal input to the address signal input terminal is 0, and the nth selector outputs the (n-1)th output signal to the input terminal of the nth shift register unit.

[0023] A partial refresh mode includes a refresh phase in which the reset signal input to the reset signal input terminal is at an inactive level, the target address signal is input to the address signal input terminal coupled to the target selector among the m selectors, and the target selector inputs a controllable signal according to the reset signal and the target address signal, and outputs the controllable signal to the input terminal of the target shift register unit coupled to the target selector.

[0024] Optionally, the partial refresh mode further includes:

[0025] During the reset phase, the reset signal input at the reset signal input terminal is at an active level, the controllable signal input at the controllable signal input terminal is at a reset level, and the nth selector outputs the controllable signal to the nth shift register unit.

[0026] Optionally, the driving method further includes:

[0027] The m shift register units are encoded, and the address signal input terminal inputs the target address signal according to the encoding of the target shift register unit.

[0028] Based on the above-described gate driving circuit technical solution, a third aspect of the present invention provides a display panel including the gate driving circuit provided in the above embodiments. The display panel includes a display area and a peripheral area surrounding the display area, the gate driving circuit being located in the peripheral area. The display panel further includes:

[0029] Multiple scan lines, at least a portion of which are located in the display area, and a shift register unit in the gate drive circuit is coupled to the corresponding scan line;

[0030] The driver chip includes: a controllable signal input terminal, a reset signal input terminal, and an address signal input terminal.

[0031] Optionally, the display panel further includes controllable signal lines, reset signal lines, and address signal lines. The controllable signal lines, reset signal lines, and address signal lines are all located in the peripheral area. The controllable signal lines are coupled to m selectors and the controllable signal input terminal, respectively. The reset signal lines are coupled to m selectors and the reset signal input terminal, respectively. The address signal lines are coupled to m selectors and the address signal input terminal, respectively.

[0032] In the technical solution provided by this invention, m shift register units are coupled one-to-one with m selectors. The nth selector can, under the joint control of the reset signal provided at the reset signal input terminal and the address signal provided at the address signal input terminal, control the nth selector to input the (n-1)th output signal provided at the output terminal of the (n-1)th shift register unit and output the (n-1)th output signal to the input terminal of the nth shift register unit. Alternatively, it can control the nth selector to input the controllable signal provided at the controllable signal input terminal and output the controllable signal to the input terminal of the nth shift register unit.

[0033] When the controllable signal is input to the nth selector and output to the input of the nth shift register unit, high-frequency refresh can be started from the nth row of sub-pixels at any time. When it is necessary to stop the high-frequency refresh, the gate driving circuit can be controlled to work in normal operation at any time through the reset signal and the address signal. Therefore, the gate driving circuit provided by the embodiments of the present invention can control a part of the shift register units to achieve multiple outputs according to actual needs, thereby controlling the multi-row sub-pixels coupled to a part of the shift register units to achieve high-frequency scanning. Therefore, the display product using the gate driving circuit provided by the embodiments of the present invention can realize the function of terminating transmission and re-specifying the refresh start position at any time, thereby realizing local ultra-high frequency refresh, partitioned refresh and ultra-fast image input response, and can meet the requirements of high refresh rate and high response speed without generating large power consumption. Attached Figure Description

[0034] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0035] Figure 1 A schematic diagram of the connection between the selector and the shift register unit provided in an embodiment of the present invention;

[0036] Figure 2 A schematic diagram of the selector provided in an embodiment of the present invention;

[0037] Figure 3 This is a schematic diagram of the input selection circuit provided in an embodiment of the present invention;

[0038] Figure 4 This is a schematic diagram of the first structure of the address selection sub-circuit provided in an embodiment of the present invention;

[0039] Figure 5 This is a schematic diagram of the second structure of the address selection sub-circuit provided in an embodiment of the present invention;

[0040] Figure 6 A schematic diagram of the third structure of the address selection sub-circuit provided in an embodiment of the present invention;

[0041] Figure 7 The timing diagram of the signals received by the selector provided in this embodiment of the invention. Detailed Implementation

[0042] To further illustrate the gate driving circuit and its driving method, as well as the display panel provided in the embodiments of the present invention, a detailed description is provided below with reference to the accompanying drawings.

[0043] Please see Figure 1 and Figure 2 This invention provides a gate driving circuit, comprising: m shift register units and m selectors, where m is an integer greater than 1;

[0044] The nth selector 1 is coupled to the input terminal GOAn-in of the nth shift register unit, the output terminal Vout-n-1 of the (n-1)th shift register unit, the controllable signal input terminal Vk, the reset signal input terminal Rst, and the address signal input terminal Vd, where 1 < n ≤ m. The nth selector 1 is used to: under the joint control of the reset signal provided by the reset signal provided by the reset signal input terminal Rst and the address signal provided by the address signal input terminal Vd, control the nth selector 1 to input the (n-1)th output signal provided by the output terminal Vout-n-1 of the (n-1)th shift register unit, and output the (n-1)th output signal to the input terminal GOAn-in of the nth shift register unit; or, control the nth selector 1 to input the controllable signal provided by the controllable signal input terminal Vk, and output the controllable signal to the input terminal GOAn-in of the nth shift register unit.

[0045] For example, the gate driving circuit is applied to a display panel and disposed in the peripheral area of ​​the display panel. The display area of ​​the display panel includes a plurality of sub-pixels distributed in an array. The plurality of sub-pixels are divided into multiple rows of sub-pixels. Each row of sub-pixels is provided with a corresponding gate driving signal by a corresponding scan line, thereby driving the sub-pixels in that row. The scan line is coupled to a corresponding shift register unit, receives the gate driving signal provided by the shift register unit, and transmits it to the corresponding sub-pixel.

[0046] It should be noted that the scan lines include, but are not limited to, gate lines, light emission control signal lines, reset lines, etc.

[0047] For example, the m selectors are coupled one-to-one with the m shift register units. The m selectors are connected to the same controllable signal input terminal Vk, the m selectors are connected to the same reset signal input terminal Rst, and the m selectors are connected to the same address signal input terminal Vd.

[0048] For example, the controllable signal input at the controllable signal input terminal Vk can be set according to actual needs. For example, the controllable signal can be set to a DC signal with a reset level, or it can be set to a single-phase pulse signal, but it is not limited to these.

[0049] In normal operating mode, the reset signal input at the reset signal input terminal Rst is at an inactive level, the address signal input at the address signal input terminal Vd is 0, and the nth selector outputs the (n-1)th output signal to the input terminal GOAn-in of the nth shift register unit, so that the m shift register units realize step-by-step shifting, that is, starting from the first shift register unit, the gate drive signal is output step by step until the mth shift register unit outputs the gate drive signal.

[0050] In partial refresh mode, during the refresh phase, the reset signal input at the reset signal input terminal Rst is at an inactive level, and the target address signal is input at the address signal input terminal Vd of the target selector among the m selectors. Based on the reset signal and the target address signal, the target selector inputs a controllable signal and outputs the controllable signal to the input terminal of the target shift register unit coupled to the target selector.

[0051] Taking the high-frequency refresh of sub-pixels from row n-4 to row n as an example, the specific refresh process is explained below:

[0052] During the refresh phase, the reset signal input at the reset signal input terminal Rst is at an inactive level. The (n-4)th selector acts as the target selector, and the target address signal is input at the address signal input terminal Vd coupled to the (n-4)th selector. Based on the inactive reset signal and the target address signal, the (n-4)th selector controls the input of a controllable signal and outputs the controllable signal to the input terminal of the (n-4)th shift register unit coupled to the (n-4)th selector, thereby controlling the (n-4)th row of sub-pixels coupled to the (n-4)th shift register unit to start scanning. After the (n-4)th row of sub-pixels begins scanning, the (n-3)th selector receives the (n-4)th output signal (i.e., the gate drive signal corresponding to the (n-4)th row of sub-pixels) from the (n-4)th shift register unit, and outputs the (n-4)th output signal to the (n-3)th shift register unit, causing the (n-3)th shift register unit to output the (n-3)th output signal (i.e., the gate drive signal corresponding to the (n-3)th row of sub-pixels) to the (n-3)th row of sub-pixels. In the above manner, the (n-2)th shift register unit, the (n-1)th shift register unit, and the nth shift register unit sequentially implement the output of the gate drive signal, and then return to the normal working mode.

[0053] As can be seen, shift register units n-4 to n can be individually controlled by outputting the target address signal to the n-4 selector, thereby achieving step-by-step output from the n-4 shift register unit to the nth shift register unit, and realizing independent refresh of sub-pixels from the n-4th row to the nth row.

[0054] It is worth noting that when controlling the high-frequency refresh of sub-pixels from row (n-4) to row (n), the target address signal is only valid for the (n-4)th selector and invalid for other selectors. Therefore, after receiving the target address signal, the (n-4)th selector can receive the controllable signal and output the controllable signal to the (n-4)th shift register unit, controlling the (n-4)th shift register unit to output the corresponding gate drive signal, thereby realizing the scanning of the (n-4)th row of sub-pixels. Although other selectors also receive the target address signal, this target address signal is invalid for them. Therefore, other selectors will receive the output signal of the shift register unit coupled to their adjacent upper-level selector and output it to the input of the corresponding shift register unit.

[0055] It should be noted that in the technical solution provided by the present invention, the local high-frequency refresh does not shorten the refresh time of each row of sub-pixels, but increases the number of refreshes of the sub-pixels in the area that needs high-frequency refresh. For example, the sub-pixels from the first row to the n-5th row are refreshed once, and the sub-pixels from the n-4th row to the nth row are refreshed three times.

[0056] According to the specific structure and operation of the gate driving circuit described above, in the gate driving circuit provided in this embodiment of the invention, m shift register units are coupled one-to-one with m selectors. The nth selector can, under the joint control of the reset signal provided at the reset signal input terminal Rst and the address signal provided at the address signal input terminal Vd, control the nth selector to input the (n-1)th output signal provided at the output terminal Vout-n-1 of the (n-1)th shift register unit and output the (n-1)th output signal to the input terminal GOAn-in of the nth shift register unit. Alternatively, it can control the nth selector to input the controllable signal provided at the controllable signal input terminal Vk and output the controllable signal to the input terminal GOAn-in of the nth shift register unit.

[0057] When the controllable signal is input to the nth selector and output to the input terminal GOAn-in of the nth shift register unit, high-frequency refresh can be started from the nth row of sub-pixels at any time. When it is necessary to stop the high-frequency refresh, the gate driving circuit can be controlled to work in normal operating state at any time through the reset signal and the address signal. Therefore, the gate driving circuit provided by the embodiments of the present invention can control a part of the shift register units to achieve multiple outputs according to actual needs, thereby controlling the multi-row sub-pixels coupled to a part of the shift register units to achieve high-frequency scanning. Therefore, the display product using the gate driving circuit provided by the embodiments of the present invention can realize the function of terminating transmission and re-specifying the refresh start position at any time, thereby realizing local ultra-high frequency refresh, partition refresh and ultra-fast image input response, and can meet the requirements of high refresh rate and high response speed without generating large power consumption.

[0058] like Figure 2 As shown, in some embodiments, the nth selector 1 includes a selection control circuit 10 and an input selection circuit 11;

[0059] The selection control circuit 10 is coupled to the reset signal input terminal Rst and the address signal input terminal Vd respectively, and is used to output an enable signal from the output terminal EN of the selection control circuit 10 according to the reset signal and the address signal;

[0060] The input selection circuit 11 is coupled to the output terminal Vout-n-1 of the (n-1)th shift register unit, the controllable signal input terminal Vk, and the output terminal EN of the selection control circuit 10, respectively. Under the control of the enable signal, it controls the nth selector to input the (n-1)th output signal provided by the output terminal Vout-n-1 of the (n-1)th shift register unit and outputs the (n-1)th output signal to the input terminal GOAn-in of the nth shift register unit; or, it controls the nth selector to input the controllable signal provided by the controllable signal input terminal Vk and outputs the controllable signal to the input terminal GOAn-in of the nth shift register unit.

[0061] In normal operating mode, the reset signal input at the reset signal input terminal Rst is at an inactive level, and the address signal input at the address signal input terminal Vd is 0. The selection control circuit 10 outputs an enable signal from its output terminal EN according to the reset signal and the address signal. Under the control of the enable signal, the input selection circuit 11 controls the nth selector to input the (n-1)th output signal provided by the output terminal Vout-n-1 of the (n-1)th shift register unit, and outputs the (n-1)th output signal to the input terminal GOAn-in of the nth shift register unit, so that the m shift register units achieve step-by-step shifting, that is, starting from the first shift register unit, the gate drive signal is output step-by-step until the mth shift register unit outputs the gate drive signal.

[0062] In partial refresh mode, during the refresh phase, the reset signal input at the reset signal input terminal Rst is at an inactive level. The target address signal is input at the address signal input terminal Vd of the target selector among the m selectors. The selection control circuit 10 in the target selector outputs an enable signal from its output terminal EN according to the reset signal and the address signal. Under the control of the enable signal, the input selection circuit 11 in the target selector inputs the controllable signal provided by the controllable signal input terminal Vk and outputs the controllable signal to the input terminal of the target shift register unit coupled to the target selector.

[0063] like Figure 2 As shown, in some embodiments, the selection control circuit 10 includes:

[0064] Address selection sub-circuit 101, which is coupled to the address signal input terminal Vd, is used to control the output terminal of the address selection sub-circuit 101 to output a first selection signal according to the address signal;

[0065] A first OR gate logic sub-circuit 102 has its first input terminal coupled to the reset signal input terminal Rst, and its second input terminal coupled to the output terminal of the address selection sub-circuit 101. It is used to output a second selection signal from the output terminal of the first OR gate logic sub-circuit 102 according to the reset signal and the first selection signal.

[0066] For example, the address signal input terminal Vd includes multiple address signal ports; the address selection sub-circuits 101 included in each selector are different, and the address selection sub-circuit 101 includes: a third AND gate logic sub-circuit, the output terminal of the third AND gate logic sub-circuit is used as the output terminal of the address selection sub-circuit 101, the third AND gate logic sub-circuit includes multiple input terminals, and each input terminal of the third AND gate logic sub-circuit is coupled to the corresponding address signal port through a second NOT gate logic sub-circuit, or directly coupled to the corresponding address signal port.

[0067] Taking the address signal input terminal Vd as an example, which includes three address signal ports, the three address signal ports can output a total of 8 address signals: 000, 001, 010, 011, 100, 101, 110, and 111.

[0068] like Figures 4 to 6 The diagram illustrates the structure of the three address selection sub-circuits 101 included in the three selectors. The address selection sub-circuits 101 in the remaining selectors are described in the same manner.

[0069] like Figure 4 As shown, the three input terminals of the third AND gate logic sub-circuit are all coupled to the corresponding address signal ports through the second NOT gate logic sub-circuit. When the address signal is 000, the address selection sub-circuit 101 outputs 1.

[0070] like Figure 5 As shown, each of the two input terminals of the third AND gate logic sub-circuit is coupled to the corresponding address signal port through the second NOT gate logic sub-circuit, and the other input terminal of the third AND gate logic sub-circuit is directly coupled to the corresponding address signal port. When the address signal is 001, the address selection sub-circuit 101 outputs 1.

[0071] like Figure 6 As shown, the three input terminals of the third AND gate logic sub-circuit are directly coupled to the corresponding address signal ports. When the address signal is 111, the address selection sub-circuit 101 outputs 1.

[0072] The address selection sub-circuit 101 is used to specify whether the shift register unit coupled to its selector is selected as the starting shift register unit for high-frequency scanning. For example, when selected, the output of the address selection sub-circuit 101 is 1, and when not selected, the output of the address selection sub-circuit 101 is 0.

[0073] The second selection signal is generated by logically ORing the reset signal and the first selection signal. For example, when the reset signal is 1, the second selection signal is 1 and the selector inputs the control signal. When the reset signal is 0, the second selection signal is determined by the first selection signal.

[0074] like Figure 2 and Figure 3 As shown, in some embodiments, the input selection circuit 11 includes:

[0075] The first NOT gate logic sub-circuit 110, the input terminal of the first NOT gate logic sub-circuit is coupled to the output terminal of the first OR gate logic sub-circuit 102;

[0076] The first AND gate logic sub-circuit 111 has its first input terminal coupled to the controllable signal input terminal Vk, and its second input terminal coupled to the output terminal of the first OR gate logic sub-circuit 102.

[0077] The second AND gate logic sub-circuit 112 has its first input terminal coupled to the output terminal of the NOT gate logic sub-circuit, and its second input terminal coupled to the output terminal Vout-n-1 of the (n-1)th shift register unit.

[0078] The second OR gate logic sub-circuit 113 has its first input terminal coupled to the output terminal of the first AND gate logic sub-circuit 111, its second input terminal coupled to the output terminal of the second AND gate logic sub-circuit 112, and its output terminal coupled to the input terminal GOAn-in of the nth shift register unit.

[0079] It is worth noting that among the multiple selectors, only the address selection sub-circuit 101 is different; the other structures are completely identical.

[0080] For example, when the second selection signal output by the output terminal of the first OR gate logic sub-circuit 102 is 0, the input selection circuit 11 inputs the (n-1)th output signal, and the output terminal of the second OR gate logic sub-circuit 113 outputs the (n-1)th output signal.

[0081] For example, when the second selection signal output by the output terminal of the first OR gate logic sub-circuit 102 is 1, the input selection circuit 11 inputs the control signal, and the output terminal of the second OR gate logic sub-circuit 113 outputs the control signal.

[0082] like Figure 7 As shown, this invention also provides a driving method for a gate driving circuit, used to drive the gate driving circuit provided in the above embodiments. The driving method includes:

[0083] In normal operating mode, the reset signal input at the reset signal input terminal Rst is at an inactive level, the address signal input at the address signal input terminal Vd is 0, and the nth selector outputs the (n-1)th output signal to the input terminal GOAn-in of the nth shift register unit; thus enabling the m shift register units to perform step-by-step shifting, that is, starting from the first shift register unit, the gate drive signal is output step by step until the mth shift register unit outputs the gate drive signal.

[0084] The partial refresh mode includes a refresh phase in which the reset signal input at the reset signal input terminal Rst is at an inactive level, the target address signal is input at the address signal input terminal Vd of the target selector among the m selectors, and the target selector inputs a controllable signal according to the reset signal and the target address signal, and outputs the controllable signal to the input terminal of the target shift register unit coupled to the target selector.

[0085] Taking the target selector including the 100th selector as an example. During the refresh phase, the target address signal corresponds to the encoding of the selected position. Based on the reset signal and the target address signal, the second selection signal in the 100th selector is 1. The 100th selector inputs a controllable signal and outputs the controllable signal to the input of the 100th shift register unit, thus realizing refresh starting from the 100th row sub-pixel. It is worth noting that during the refresh phase, the waveform of the controllable signal can be set according to actual needs.

[0086] During the refresh phase, the target selector can be selected according to actual needs, or the refresh phase time can be extended or shortened by controlling the waveform of the control signal.

[0087] In the driving method of the gate driving circuit provided in the embodiments of the present invention, the nth selector can, under the joint control of the reset signal provided by the reset signal input terminal Rst and the address signal provided by the address signal input terminal Vd, control the nth selector to input the (n-1)th output signal provided by the output terminal Vout-n-1 of the (n-1)th shift register unit and output the (n-1)th output signal to the input terminal GOAn-in of the nth shift register unit; or, control the nth selector to input the controllable signal provided by the controllable signal input terminal Vk and output the controllable signal to the input terminal GOAn-in of the nth shift register unit.

[0088] When the controllable signal is input to the nth selector and output to the input terminal GOAn-in of the nth shift register unit, high-frequency refresh can be started from the nth row of sub-pixels at any time. When it is necessary to stop the high-frequency refresh, the gate driving circuit can be controlled to work in normal operation at any time through the reset signal and the address signal. Therefore, the driving method of the gate driving circuit provided in this embodiment of the invention can control a part of the shift register units to achieve multiple outputs according to actual needs, thereby controlling the multi-row sub-pixels coupled to a part of the shift register units to achieve high-frequency scanning. Therefore, the display product driven by the gate driving circuit driving method provided in this embodiment of the invention can realize the function of terminating transmission and re-specifying the refresh start position at any time, thereby realizing local ultra-high frequency refresh, partitioned refresh and ultra-fast image input response, and can meet the requirements of high refresh rate and high response speed without generating large power consumption.

[0089] In some embodiments, the partial refresh mode further includes:

[0090] During the reset phase, the reset signal input at the reset signal input terminal Rst is at an active level, the controllable signal input at the controllable signal input terminal Vk is at a reset level, and the nth selector outputs the controllable signal to the nth shift register unit.

[0091] For example, the reset phase is located before the refresh phase. In the reset phase, the input terminals of all m shift register units are input with controllable signals having a reset level, all m shift register units are reset, and the step-by-step signal shift transmission of the m shift register units is interrupted.

[0092] For example, the level of the reset of the controllable signal depends on the type of the first transistor coupled to the input of the shift register unit.

[0093] For example, when you want to end the partial refresh mode, you can set the reset signal input at the reset signal input terminal Rst to an inactive level and the address signal input at the address signal input terminal Vd to 0, thereby restoring the normal working mode.

[0094] In some embodiments, the driving method further includes:

[0095] The m shift register units are encoded, and the address signal input terminal Vd inputs the target address signal according to the encoding of the target shift register unit.

[0096] More specifically, the shift register unit corresponding to each row of sub-pixels is first encoded. For example, the first shift register unit corresponding to the first row of sub-pixels is encoded as 1, the second shift register unit corresponding to the second row of sub-pixels is encoded as 2, and so on; 0 is reserved as a disabled option.

[0097] The address selection sub-circuit 101 is designed based on the encoding of m shift register units. Taking four address lines A / B / C / D as an example, the encoding of the first shift register unit is 1, the encoding of the second shift register unit is 2, and so on. Then the output of the address selection sub-circuit 101 in the first selector is —A—&—B—&—C—&D. That is, when ABCD = 0001, the first selection signal is 1, and in other cases, the first selection signal is 0.

[0098] The address selection sub-circuit 101 in the second selector outputs —A—&—B—&C&—D—, that is, when ABCD=0010, the first selection signal is 1, and in other cases the first selection signal is 0.

[0099] The address selection sub-circuit 101 in the third selector outputs —A—&—B—&C&D, that is, when ABCD=0011, the first selection signal is 1, and in other cases the first selection signal is 0, and so on.

[0100] Because 0 is reserved, when ABCD = 0000, all address selection sub-circuits 101 output 0.

[0101] This invention also provides a display panel, including the gate driving circuit provided in the above embodiments. The display panel includes a display area and a peripheral area surrounding the display area, the gate driving circuit is located in the peripheral area, and the display panel further includes:

[0102] Multiple scan lines, at least a portion of which are located in the display area, and a shift register unit in the gate drive circuit is coupled to the corresponding scan line;

[0103] The driver chip includes: a controllable signal input terminal Vk, a reset signal input terminal Rst, and an address signal input terminal Vd.

[0104] For example, the display panel further includes multiple rows of sub-pixels located in the display area, the multiple scan lines correspond one-to-one with the multiple rows of sub-pixels, and the scan lines are respectively coupled to each sub-pixel in the corresponding row of sub-pixels.

[0105] When the display panel provided in the embodiments of the present invention includes the gate driving circuit provided in the above embodiments, it can realize the function of terminating the transmission and re-specifying the refresh start position at any time. This enables local ultra-high frequency refresh, partitioned refresh, and ultra-fast image input response, and can meet the requirements of high refresh rate and high response speed without generating large power consumption.

[0106] When the display panel provided in the embodiments of the present invention includes the gate driving circuit provided in the above embodiments, the following beneficial effects can be achieved:

[0107] Partitioned frequency conversion allows for flexible partitioned refreshing by selecting the refresh start position and stopping the refresh at any time. This enables refreshing only the areas that have changed, thereby reducing unnecessary power consumption.

[0108] Local ultra-high frequency refresh allows for the termination of the refresh process and the reselection of the starting position at any time. It does not require waiting for a full frame to be refreshed before starting the refresh. If only a local change occurs in the displayed image, only that local area can be updated, thus shortening the time required to refresh a frame and achieving a higher refresh rate than a full refresh.

[0109] Because it can achieve high-frequency local refresh, it can respond to changes in the displayed screen more quickly, reduce input and output latency, and improve the user experience of display products.

[0110] In some embodiments, the display panel further includes controllable signal lines, reset signal lines, and address signal lines. The controllable signal lines, reset signal lines, and address signal lines are all located in the peripheral area. The controllable signal lines are coupled to m selectors and the controllable signal input terminal Vk, respectively. The reset signal lines are coupled to m selectors and the reset signal input terminal Rst, respectively. The address signal lines are coupled to m selectors and the address signal input terminal Vd, respectively.

[0111] The m selectors share the same reset signal line and the same controllable signal line. The display panel includes multiple address signal lines, and the m selectors share multiple address signal lines.

[0112] When the display panel is applied to a display device, the display device can be any product or component with display function, such as a television, monitor, digital photo frame, mobile phone, or tablet computer. The display device also includes flexible circuit boards, printed circuit boards, and back panels.

[0113] In the various method embodiments of the present invention, the sequence numbers of each step are not intended to limit the order of the steps. For those skilled in the art, any changes in the order of the steps without creative effort are also within the scope of protection of the present invention.

[0114] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the method embodiments are basically similar to the product embodiments, so the description is relatively simple, and the relevant parts can be referred to the description of the product embodiments.

[0115] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connection,” “coupled,” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships; these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0116] It is understandable that when a component such as a layer, film, region, or substrate is referred to as being "above" or "below" another component, the component may be "directly" located "above" or "below" the other component, or there may be intermediate components present.

[0117] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0118] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A gate driving circuit, characterized in that, include: m shift register units and m selectors, where m is an integer greater than 1; The nth selector is coupled to the input terminal of the nth shift register unit, the output terminal of the (n-1)th shift register unit, the controllable signal input terminal, the reset signal input terminal, and the address signal input terminal, respectively, where 1 < n ≤ m. The nth selector is used to: determine whether the address signal provided by the address signal input terminal is the target address signal; and under the joint control of the reset signal provided by the reset signal input terminal and the address signal, if the address signal is not the target address signal, control the nth selector to input the (n-1)th output signal provided by the output terminal of the (n-1)th shift register unit and output the (n-1)th output signal to the input terminal of the nth shift register unit; if the address signal is the target address signal, control the nth selector to input the controllable signal provided by the controllable signal input terminal and output the controllable signal to the input terminal of the nth shift register unit.

2. The gate driving circuit according to claim 1, characterized in that, The nth selector includes a selection control circuit and an input selection circuit; The selection control circuit is coupled to the reset signal input terminal and the address signal input terminal respectively, and is used to output an enable signal from the output terminal of the selection control circuit according to the reset signal and the address signal; The input selection circuit is coupled to the output terminal of the (n-1)th shift register unit, the controllable signal input terminal, and the output terminal of the selection control circuit, respectively. Under the control of the enable signal, it controls the nth selector to input the (n-1)th output signal provided by the output terminal of the (n-1)th shift register unit and outputs the (n-1)th output signal to the input terminal of the nth shift register unit; or, it controls the nth selector to input the controllable signal provided by the controllable signal input terminal and outputs the controllable signal to the input terminal of the nth shift register unit.

3. The gate driving circuit according to claim 2, characterized in that, The selection control circuit includes: The address selection sub-circuit is coupled to the address signal input terminal and is used to control the output terminal of the address selection sub-circuit to output a first selection signal according to the address signal. A first OR gate logic sub-circuit, wherein the first input terminal of the first OR gate logic sub-circuit is coupled to the reset signal input terminal, and the second input terminal of the first OR gate logic sub-circuit is coupled to the output terminal of the address selection sub-circuit, is used to output a second selection signal from the output terminal of the first OR gate logic sub-circuit according to the reset signal and the first selection signal.

4. The gate driving circuit according to claim 3, characterized in that, The input selection circuit includes: The first NOT gate logic sub-circuit, wherein the input terminal of the first NOT gate logic sub-circuit is coupled to the output terminal of the first OR gate logic sub-circuit; The first AND gate logic sub-circuit has a first input terminal coupled to the controllable signal input terminal, and a second input terminal coupled to the output terminal of the first OR gate logic sub-circuit. The second AND gate logic sub-circuit has its first input terminal coupled to the output terminal of the NOT gate logic sub-circuit, and its second input terminal coupled to the output terminal of the (n-1)th shift register unit. The second OR gate logic sub-circuit has its first input terminal coupled to the output terminal of the first AND gate logic sub-circuit, its second input terminal coupled to the output terminal of the second AND gate logic sub-circuit, and its output terminal coupled to the input terminal of the nth shift register unit.

5. The gate driving circuit according to claim 3, characterized in that, The address signal input terminal includes multiple address signal ports; The address selection sub-circuits included in each selector are different, and the address selection sub-circuit includes: The third AND gate logic sub-circuit, the output of which serves as the output of the address selection sub-circuit, includes multiple input terminals. Each input terminal of the third AND gate logic sub-circuit is coupled to the corresponding address signal port through the second NOT gate logic sub-circuit, or directly coupled to the corresponding address signal port.

6. A driving method for a gate driving circuit, characterized in that, The driving method is used to drive the gate driving circuit as described in any one of claims 1 to 5, and the driving method includes: In normal operating mode, the reset signal input to the reset signal input terminal is at an inactive level, the address signal input to the address signal input terminal is 0, and the nth selector outputs the (n-1)th output signal to the input terminal of the nth shift register unit. A partial refresh mode includes a refresh phase in which the reset signal input to the reset signal input terminal is at an inactive level, the target address signal is input to the address signal input terminal coupled to the target selector among the m selectors, and the target selector inputs a controllable signal according to the reset signal and the target address signal, and outputs the controllable signal to the input terminal of the target shift register unit coupled to the target selector.

7. The driving method for the gate driving circuit according to claim 6, characterized in that, The partial refresh mode also includes: During the reset phase, the reset signal input at the reset signal input terminal is at an active level, the controllable signal input at the controllable signal input terminal is at a reset level, and the nth selector outputs the controllable signal to the nth shift register unit.

8. The driving method for the gate driving circuit according to claim 6, characterized in that, The driving method further includes: The m shift register units are encoded, and the address signal input terminal inputs the target address signal according to the encoding of the target shift register unit.

9. A display panel, characterized in that, The display panel includes the gate driving circuit as described in any one of claims 1 to 5, the display panel includes a display area and a peripheral area surrounding the display area, the gate driving circuit is located in the peripheral area, and the display panel further includes: Multiple scan lines, at least a portion of which are located in the display area, and a shift register unit in the gate drive circuit is coupled to the corresponding scan line; The driver chip includes: a controllable signal input terminal, a reset signal input terminal, and an address signal input terminal.

10. The display panel according to claim 9, characterized in that, The display panel also includes controllable signal lines, reset signal lines, and address signal lines. The controllable signal lines, reset signal lines, and address signal lines are all located in the peripheral area. The controllable signal lines are coupled to m selectors and the controllable signal input terminal, respectively. The reset signal lines are coupled to m selectors and the reset signal input terminal, respectively. The address signal lines are coupled to m selectors and the address signal input terminal, respectively.

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