Test structure and test method

Abstract

The present invention provides a test structure and a test method, the test structure comprising: a substrate; a device structure formed on the substrate; a first protection diode and a second protection diode formed in the substrate, the first protection diode and the second protection diode being connected in parallel with the device structure, the first protection diode and the second protection diode having opposite polarities; a first metal interconnection structure and a second metal interconnection structure, the first metal interconnection structure being electrically connected to the device structure, the second metal interconnection structure being electrically connected to the first protection diode and the second protection diode, a fuse structure being connected between the first metal interconnection structure and the second metal interconnection structure. The technical solution of the present invention can improve the protection effect on the device structure while avoiding the influence on the test of the device structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a test structure and a test method. Background Art

[0002] During processes such as deposition and etching, plasma bombardment is performed on the wafer surface, resulting in free positive and negative charges on the wafer surface. These free charges are conducted through conductors on the wafer surface to the device structure in the test structure used for reliability and WAT testing. For example, when the device structure is a MOS transistor, the free charges are conducted to the gate layer and gate oxide layer in the MOS transistor, causing damage to the gate oxide layer, thereby affecting the performance of the semiconductor device.

[0003] Among them, in order to avoid damage to the device structure, a protection diode connected in parallel with the device structure is currently added to the test structure to conduct away the free charge. However, when a protection diode connected in parallel with the device structure is added to the test structure, in order to be able to test the semiconductor device normally later, the polarity of the protection diode needs to be specially selected (for example, when the device structure is a MOS transistor, in order to perform a normal inversion test, NMOS must select an N / P diode instead of a P / N diode, and PMOS must select a P / N diode instead of an N / P diode), but this will cause the protection diode to be unable to conduct away the free positive and negative charges at the same time, which in turn leads to a poor protection effect on the device structure.

[0004] Therefore, the test structure needs to be improved to solve the above problems. Summary of the invention

[0005] The object of the present invention is to provide a test structure and a test method, which can improve the protection effect on the device structure while avoiding the influence on the test of the device structure.

[0006] To achieve the above object, the present invention provides a test structure, comprising:

[0007] substrate;

[0008] a device structure formed on the substrate;

[0009] A first protection diode and a second protection diode are formed in the substrate, the first protection diode and the second protection diode are connected in parallel with the device structure, and the first protection diode and the second protection diode have opposite polarities;

[0010] A first metal interconnection structure and a second metal interconnection structure, wherein the first metal interconnection structure is electrically connected to the device structure, the second metal interconnection structure is electrically connected to the first protection diode and the second protection diode, and a fuse structure is connected between the first metal interconnection structure and the second metal interconnection structure.

[0011] Optionally, the test structure further includes:

[0012] a first pad electrically connected to the device structure through the first metal interconnect structure;

[0013] The second pad is electrically connected to the first protection diode and the second protection tube through the second metal interconnection structure. The first metal interconnection structure and the second metal interconnection structure both include metal interconnection lines and conductive plugs electrically connected to the metal interconnection lines.

[0014] Optionally, the fuse structure is a metal line, which is easier to disconnect and form an open circuit than the metal interconnection line.

[0015] Optionally, the fuse structure comprises an insulating dielectric layer, a polysilicon layer and a metal silicide layer sequentially formed on the substrate, and a longitudinal cross-sectional area of ​​the metal silicide layer is smaller than a longitudinal cross-sectional area of ​​the metal interconnection line.

[0016] Optionally, the device structure is a MOS transistor, the MOS transistor includes a gate oxide layer and a gate layer formed in sequence on the substrate, and the MOS transistor is an NMOS transistor or a PMOS transistor; the device structure is a capacitor structure, the capacitor structure includes an oxide layer, a floating gate layer, an inter-gate dielectric layer and a control gate layer formed in sequence on the substrate, or the capacitor structure includes the substrate and a gate oxide layer and a control gate layer formed in sequence on the substrate.

[0017] The present invention also provides a testing method, comprising:

[0018] Providing a wafer comprising the test structure as claimed in claim 1;

[0019] A production process is performed, wherein the free positive charges and negative charges generated on the surface of the wafer by the production process are respectively conducted away through the first protection diode and the second protection diode.

[0020] Optionally, the testing method further comprises:

[0021] forming a first pad, wherein the first pad is electrically connected to the device structure through the first metal interconnect structure;

[0022] A second pad is formed, and the second pad is electrically connected to the first protection diode and the second protection tube through the second metal interconnection structure. The first metal interconnection structure and the second metal interconnection structure both include metal interconnection lines and conductive plugs electrically connected to the metal interconnection lines.

[0023] Optionally, the testing method further comprises:

[0024] The first pad is grounded and a positive voltage is applied to the second pad to open the fuse structure.

[0025] Optionally, the fuse structure is a metal line, which is easier to disconnect and form an open circuit than the metal interconnection line; after the first pad is grounded and a positive voltage is applied to the second pad, the metal line is disconnected.

[0026] Optionally, the fuse structure includes an insulating dielectric layer, a polysilicon layer and a metal silicide layer formed in sequence on the substrate, and the longitudinal cross-sectional area of ​​the metal silicide layer is smaller than the longitudinal cross-sectional area of ​​the metal interconnection line; after the first pad is grounded and a positive voltage is applied to the second pad, the metal silicide layer is disconnected.

[0027] Optionally, after the fuse structure is disconnected, the testing method further includes:

[0028] Testing is performed on the device structure.

[0029] Optionally, the production process includes a deposition process or an etching process.

[0030] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0031] 1. The test structure of the present invention comprises: a substrate; a device structure formed on the substrate; a first protection diode and a second protection diode formed in the substrate, the first protection diode and the second protection diode being connected in parallel with the device structure, and the first protection diode and the second protection diode having opposite polarities; a first metal interconnection structure and a second metal interconnection structure, the first metal interconnection structure being electrically connected to the device structure, the second metal interconnection structure being electrically connected to the first protection diode and the second protection diode, and a fuse being connected between the first metal interconnection structure and the second metal interconnection structure, so that the protection effect on the device structure can be improved while avoiding affecting the test of the device structure.

[0032] 2. The testing method of the present invention provides a wafer including the test structure; and executes a production process, wherein the free positive charges and negative charges generated on the surface of the wafer by the production process are respectively conducted away through the first protection diode and the second protection diode, thereby improving the protection effect on the device structure while avoiding affecting the test of the device structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1a is a schematic diagram of a test structure according to an embodiment of the present invention;

[0034] Figure 1b yes Figure 1a A schematic top view of metal lines and metal interconnects in the test structure shown;

[0035] Figure 2 is a schematic diagram of a test structure according to another embodiment of the present invention;

[0036] Figure 3 yes Figure 1a A schematic diagram of the fuse structure in the test structure shown after disconnection;

[0037] Figure 4 yes Figure 2 A schematic diagram of the fuse structure in the test structure shown after disconnection;

[0038] Figure 5 is a flow chart of a testing method according to an embodiment of the present invention.

[0039] Among them, Figure 1a to Figure 5 The reference numerals are described as follows:

[0040] 11-substrate; 121-gate oxide layer; 122-gate layer; 123-source region; 124-drain region; 131-first ion doping region; 132-second ion doping region; 141-third ion doping region; 142-fourth ion doping region; 15-first pad; 16-second pad; 17-metal interconnection line; 18-conductive plug; 19-metal line; 211-insulating dielectric layer; 212-polysilicon layer; 213-metal silicide layer. DETAILED DESCRIPTION

[0041] In order to make the purpose, advantages and features of the present invention clearer, the test structure and test method proposed in the present invention are further described in detail below. It should be noted that the drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0042] An embodiment of the present invention provides a test structure, including: a substrate; a device structure formed on the substrate; a first protection diode and a second protection diode formed in the substrate, the first protection diode and the second protection diode being connected in parallel with the device structure, the first protection diode and the second protection diode having opposite polarities; a first metal interconnection structure and a second metal interconnection structure, the first metal interconnection structure being electrically connected to the device structure, the second metal interconnection structure being electrically connected to the first protection diode and the second protection diode, and a fuse structure being connected between the first metal interconnection structure and the second metal interconnection structure.

[0043] See below Figure 1a to Figure 1b and Figure 2 The test structure provided by this embodiment is described in detail.

[0044] The device structure is formed on the substrate 11. The device structure is a MOS transistor or a capacitor structure.

[0045] like Figure 1a and Figure 2 As shown, the MOS transistor includes a gate oxide layer 121 and a gate layer 122 sequentially formed on the substrate 11 , and the MOS transistor also includes a source region 123 and a drain region 124 formed in the substrate 11 on both sides of the gate layer 122 .

[0046] The MOS transistor may be an NMOS transistor or a PMOS transistor, and the test structure may include only an NMOS transistor or a PMOS transistor, or include both an NMOS transistor and a PMOS transistor.

[0047] The capacitor structure (not shown) may be a PIP (Poly-insulator-poly) capacitor, which includes an oxide layer, a floating gate layer, an inter-gate dielectric layer, and a control gate layer sequentially formed on the substrate 11; or, the capacitor structure may include the substrate 11 and a gate oxide layer and a control gate layer sequentially formed on the substrate 11. It should be noted that the capacitor structure is not limited to the above two types.

[0048] The first protection diode and the second protection diode are formed in the substrate 11 , the first protection diode and the second protection diode are connected in parallel with the device structure, and the first protection diode and the second protection diode have opposite polarities.

[0049] The first protection diode may include a first ion doping region 131 and a second ion doping region 132, wherein the ion doping types of the first ion doping region 131 and the second ion doping region 132 are opposite, and the second ion doping region 132 surrounds the first ion doping region 131. When the ion doping type of the first ion doping region 131 is N-type, the ion doping type of the second ion doping region 132 is P-type, and the first protection diode is an N / P diode; when the ion doping type of the first ion doping region 131 is P-type, the ion doping type of the second ion doping region 132 is N-type, and the second protection diode is a P / N diode.

[0050] The second protection diode may include a third ion doping region 141 and a fourth ion doping region 142, wherein the ion doping types of the third ion doping region 141 and the fourth ion doping region 142 are opposite, and the fourth ion doping region 142 surrounds the third ion doping region 141. Since the polarity of the first protection diode is opposite to that of the second protection diode, when the ion doping type of the first ion doping region 131 is N-type and the ion doping type of the second ion doping region 132 is P-type, the ion doping type of the third ion doping region 141 is P-type, the ion doping type of the fourth ion doping region 142 is N-type, and the second protection diode is a P / N diode; when the ion doping type of the first ion doping region 131 is P-type and the ion doping type of the second ion doping region 132 is N-type, the ion doping type of the third ion doping region 141 is N-type, the ion doping type of the fourth ion doping region 142 is P-type, and the second protection diode is an N / P diode.

[0051] The first metal interconnect structure is electrically connected to the device structure, and the second metal interconnect structure is electrically connected to the first protection diode and the second protection diode.

[0052] The test structure also includes:

[0053] A first pad 15, electrically connected to the device structure through the first metal interconnect structure;

[0054] The second pad 16 is electrically connected to the first protection diode and the second protection transistor through the second metal interconnection structure.

[0055] The first metal interconnection structure and the second metal interconnection structure both include a metal interconnection line 17 and a conductive plug 18 electrically connected to the metal interconnection line 17; the first pad 15 is electrically connected to the gate layer 122 in the MOS transistor through at least one layer of the conductive plug 18 and at least one layer of the metal interconnection line 17; or the first pad 15 is electrically connected to the control gate layer in the capacitor structure through at least one layer of the conductive plug 18 and at least one layer of the metal interconnection line 17; the second pad 16 is electrically connected to the first ion doping region 131 in the first protection diode and the third ion doping region 141 in the second protection diode through at least one layer of the conductive plug 18 and at least one layer of the metal interconnection line 17. The conductive plugs 18 of each layer are alternately connected to the metal interconnection lines 17 of each layer.

[0056] Furthermore, a fuse structure is connected between the first metal interconnection structure and the second metal interconnection structure, and the fuse structure can cut off the current by fusing itself when the current rises to a certain level, thereby disconnecting the circuit and forming an open circuit.

[0057] In some embodiments, Figure 1a As shown, the fuse structure may be a metal line 19 , and the metal interconnection line 17 in the first metal interconnection structure and the metal interconnection line 17 in the second metal interconnection structure are electrically connected via the metal line 19 .

[0058] Moreover, the amount of current allowed to pass through the metal wire 19 is smaller than that of the metal interconnection line 17, that is, when the load of the on-current is too large, the metal wire 19 is more likely to be burned than the metal interconnection line 17, so that the metal wire 19 can be disconnected to form an open circuit by applying a specific voltage to the first pad 15 and the second pad 16. The longitudinal cross-sectional area of ​​the metal wire 19 is smaller than that of the metal interconnection line 17, so that the current density in the metal wire 19 is higher than that in the metal interconnection line 17, so that the metal wire 19 is more likely to be burned than the metal interconnection line 17; or the anti-migration ability of the material of the metal wire 19 is smaller than that of the material of the metal interconnection line 17, so that under the action of a large current, the metal atoms in the metal wire 19 are more likely to be pushed away and disconnected than the metal atoms in the metal interconnection line 17, so that the metal wire 19 is more likely to be disconnected than the metal interconnection line 17.

[0059] When the longitudinal cross-sectional area of ​​the metal line 19 is smaller than the longitudinal cross-sectional area of ​​the metal interconnection line 17, the width of the metal line 19 in a direction parallel to the surface of the substrate 11 is smaller than the width of the metal interconnection line 17 in a direction parallel to the surface of the substrate 11. Figure 1a and Figure 1b As shown, the metal interconnection line 17 in the first metal interconnection structure and the metal interconnection line 17 in the second metal interconnection structure extend along the X-axis direction, the X-axis direction is the length direction of the metal interconnection line 17 and the metal line 19, and the Y-axis direction is the width direction of the metal interconnection line 17 and the metal line 19, and the width of the metal line 19 is smaller than the width of the metal interconnection line 17; or, the thickness of the metal line 19 in a direction perpendicular to the surface of the substrate 11 may be smaller than the thickness of the metal interconnection line 17 in a direction perpendicular to the surface of the substrate 11; or, the width of the metal line 19 in a direction parallel to the surface of the substrate 11 is smaller than the width of the metal interconnection line 17 in a direction parallel to the surface of the substrate 11 and the thickness of the metal line 19 in a direction perpendicular to the surface of the substrate 11 is smaller than the thickness of the metal interconnection line 17 in a direction perpendicular to the surface of the substrate 11.

[0060] When the anti-migration capability of the material of the metal line 19 is less than that of the material of the metal interconnection line 17, the material of the metal line 19 may be aluminum or copper, and the material of the metal interconnection line 17 may be copper or tungsten, and the anti-migration capabilities of aluminum, copper and tungsten increase in turn.

[0061] In some embodiments, Figure 2 As shown, the fuse structure may include an insulating dielectric layer 211, a polysilicon layer 212 and a metal silicide layer 213 formed in sequence on the substrate 11, and the metal interconnection line 17 and the conductive plug 18 in the first metal interconnection structure are electrically connected to the metal interconnection line 17 and the conductive plug 18 in the second metal interconnection structure through the metal silicide layer 213.

[0062] Furthermore, it is preferred that the longitudinal cross-sectional area of ​​the metal silicide layer 213 is smaller than the longitudinal cross-sectional area of ​​the metal interconnection line 17, so that the metal silicide layer 213 can be disconnected when a voltage is applied to the first pad 15 and the second pad 16. Wherein, the width of the metal silicide layer 213 in the direction parallel to the surface of the substrate 11 (i.e., the width in the Y-axis direction) is smaller than the width of the metal interconnection line 17 in the direction parallel to the surface of the substrate 11; or, the thickness of the metal silicide layer 213 in the direction perpendicular to the surface of the substrate 11 may be smaller than the thickness of the metal interconnection line 17 in the direction perpendicular to the surface of the substrate 11; or, the width of the metal silicide layer 213 in the direction parallel to the surface of the substrate 11 is smaller than the width of the metal interconnection line 17 in the direction parallel to the surface of the substrate 11 and the thickness of the metal silicide layer 213 in the direction perpendicular to the surface of the substrate 11 is smaller than the thickness of the metal interconnection line 17 in the direction perpendicular to the surface of the substrate 11.

[0063] Furthermore, since the metal silicide layer 213 is formed by depositing metal on top of the polysilicon layer 212 and then performing thermal annealing to allow the metal to react with the polysilicon layer 212, the length and width of the insulating dielectric layer 211 and the polysilicon layer 212 in a direction parallel to the surface of the substrate 11 are the same as the length and width of the metal silicide layer 213 in a direction parallel to the surface of the substrate 11.

[0064] Since plasma bombardment is performed on the wafer surface during the production process, free positive and negative charges are generated on the wafer surface. In order to prevent the free positive and negative charges from being conducted into the device structure through the first metal interconnect structure electrically connected to the device structure, thereby damaging the device structure, the present invention adds the first protection diode and the second protection diode in parallel with the device structure to the test structure, so that the free positive and negative charges can flow into the first protection diode and the second protection diode with lower resistance, and since the first protection diode and the second protection diode have opposite polarities, the free positive and negative charges can be conducted away through the first protection diode and the second protection diode with opposite polarities, respectively, thereby improving the protection effect of the device structure and further improving the performance of the semiconductor device. Among them, the free positive charges can be conducted away through the P / N diode, and the free negative charges can be conducted away through the N / P diode.

[0065] Among them, when the device structure is a MOS transistor, if the free positive and negative charges are introduced into the device structure, the gate oxide layer 121 will be damaged, which will lead to problems such as increased gate oxide leakage and increased turn-on voltage; when the device structure is a capacitor structure, if the free positive and negative charges are introduced into the device structure, the inter-gate dielectric layer and the gate oxide layer will be damaged, which will lead to problems such as increased leakage, weakened anti-breakdown capability and reduced life. Therefore, the free positive and negative charges are respectively conducted away through the first protection diode and the second protection diode with opposite polarities, which can avoid the above problems.

[0066] However, when the test structure includes a protection diode, it will affect the subsequent test of the semiconductor device.

[0067] For example, when the device structure is a MOS transistor, the semiconductor device needs to be subsequently subjected to an inversion test and a cumulative test, etc. When the MOS transistor is an NMOS transistor, the inversion test is to apply a positive voltage to the gate layer 122. If the protection diode contains a P / N diode, the P / N diode will be turned on, and the voltage cannot be applied to the NMOS transistor, so that the inversion test cannot be performed (and if the protection diode is an N / P diode, the N / P diode will be in a reverse cutoff state, that is, it will not be turned on, so that the voltage can be normally applied to the NMOS transistor, and the inversion test can be performed normally); the cumulative test is to apply a negative voltage to the gate layer 122. If the protection diode contains an N / P diode, the N / P diode will be turned on, and the voltage cannot be added to the NMOS transistor, so that the cumulative test cannot be performed. When the MOS transistor is a PMOS transistor, the inversion test is to apply a negative voltage to the gate layer 122. If the protection diode contains an N / P diode, the N / P diode will be turned on, and the voltage cannot be added to the NMOS transistor, so that the inversion test cannot be performed; the accumulation test is to apply a positive voltage to the gate layer 122. If the protection diode contains a P / N diode, the P / N diode will be turned on, and the voltage cannot be added to the NMOS transistor, so that the accumulation test cannot be performed. Therefore, if the test structure only contains a protection diode of one polarity (P / N diode or N / P diode), it will result in the inability to test the NMOS transistor and the PMOS transistor at the same time, and it will also result in the inability to use the same test structure to perform an inversion test and an accumulation test on the NMOS transistor or the PMOS transistor; if the test structure contains two types of the first protection diode and the second protection diode (P / N diode and N / P diode) with opposite polarities, it will result in the inability to perform an inversion test and an accumulation test on the NMOS transistor and the PMOS transistor.

[0068] For example, when the device structure is a capacitor structure, it is necessary to subsequently evaluate the quality of the inter-gate dielectric layer and the gate oxide layer to obtain the reliability performance of the semiconductor device, such as the breakdown time. When a positive voltage is applied to the control gate layer, if the protection diode contains a P / N diode, the P / N diode will be turned on, and the voltage cannot be added to the capacitor structure, so that the test cannot be performed; when a negative voltage is applied to the control gate layer, if the protection diode contains an N / P diode, the N / P diode will be turned on, and the voltage cannot be added to the capacitor structure, so that the test cannot be performed. Therefore, if the test structure only contains a protection diode of one polarity, the capacitor structure cannot be tested using the same test structure; if the test structure contains the first protection diode and the second protection diode of two opposite polarities, the above two tests on the capacitor structure cannot be performed.

[0069] Therefore, in the present invention, by forming the fuse structure between the first metal interconnection structure and the second metal interconnection structure, the fuse structure can be disconnected after executing the production process and before executing the test, thereby disconnecting the device structure and the protection diode (i.e., the first protection diode and the second protection diode), thereby avoiding the protection diode from affecting the test.

[0070] In summary, the present invention provides a test structure, including: a substrate; a device structure formed on the substrate; a first protection diode and a second protection diode formed in the substrate, the first protection diode and the second protection diode are connected in parallel with the device structure, and the polarity of the first protection diode is opposite to that of the second protection diode; a first metal interconnection structure and a second metal interconnection structure, the first metal interconnection structure is electrically connected to the device structure, the second metal interconnection structure is electrically connected to the first protection diode and the second protection diode, and a fuse structure is connected between the first metal interconnection structure and the second metal interconnection structure. The test structure provided by the present invention can improve the protection effect on the device structure while avoiding the influence on the test of the device structure.

[0071] Based on the same inventive concept, an embodiment of the present invention provides a testing method, referring to Figure 5 ,from Figure 5 As can be seen from the figure, the test method includes:

[0072] Step S1, providing a wafer including the test structure;

[0073] Step S2, executing a production process, wherein the free positive charges and negative charges generated on the surface of the wafer by the production process are respectively conducted away through the first protection diode and the second protection diode.

[0074] See below Figure 3 and Figure 4 The testing method provided in this embodiment is described in detail.

[0075] According to step S1, a wafer including the test structure of the present invention is provided.

[0076] The test structure can be found in the above-mentioned detailed description of the test structure of the present invention, which will not be described in detail here.

[0077] The test structure can be located in the cutting path of the wafer, and the cutting path is located at the periphery of the chip area. After cutting along the cutting path, the chip can be obtained. The test structure does not occupy the area of ​​the chip area to avoid affecting the wiring design of the chip area, thereby avoiding affecting the performance of the chip and increasing the production cost.

[0078] The wafer includes the substrate 11 and a dielectric layer (not shown) formed on the substrate 11, the gate oxide layer 121 and the gate layer 122 in the MOS transistor, the capacitor structure, the fuse structure, the first metal interconnection structure and the second metal interconnection structure are all formed in the dielectric layer, and the dielectric layer can expose the metal interconnection lines 17 in the first metal interconnection structure and the second metal interconnection structure.

[0079] According to step S2, a production process is performed, and the free positive charges and negative charges generated on the surface of the wafer by the production process are respectively conducted away through the first protection diode and the second protection diode.

[0080] Among them, the production process may include a deposition process or an etching process. Further, the deposition process may be a high-density plasma enhanced chemical vapor deposition process, and the etching process may be a plasma etching process, so that plasma bombardment is performed on the surface of the wafer during the production process, resulting in free positive and negative charges on the surface of the wafer.

[0081] The free positive charges and negative charges are directed to the first protection diode and the second protection diode with lower resistance through the metal interconnection lines 17 in the first metal interconnection structure and the second metal interconnection structure exposed by the dielectric layer. Moreover, since the first protection diode and the second protection diode have opposite polarities, the free positive charges and negative charges can be respectively conducted away through the first protection diode and the second protection diode with opposite polarities, thereby preventing the free positive charges or negative charges from being directed to the device structure and causing damage to the device structure, thereby improving the protection effect of the device structure and further improving the performance of the semiconductor device.

[0082] Among them, when the device structure is a MOS transistor, if the free positive and negative charges are introduced into the device structure, the gate oxide layer 121 will be damaged, which will lead to problems such as increased gate oxide leakage and increased turn-on voltage; when the device structure is a capacitor structure, if the free positive and negative charges are introduced into the device structure, the inter-gate dielectric layer and the gate oxide layer will be damaged, which will lead to problems such as increased leakage, weakened anti-breakdown capability and reduced life. Therefore, the free positive and negative charges are respectively conducted away through the first protection diode and the second protection diode with opposite polarities, which can avoid the above problems.

[0083] In addition, after performing the production process and before performing a test on the device structure, the testing method further includes:

[0084] forming a first pad 15, wherein the first pad 15 is electrically connected to the device structure through the first metal interconnect structure;

[0085] A second pad 16 is formed, and the second pad 16 is electrically connected to the first protection diode and the second protection tube through the second metal interconnection structure. The first metal interconnection structure and the second metal interconnection structure both include a metal interconnection line 17 and a conductive plug 18 electrically connected to the metal interconnection line 17.

[0086] In addition, since when the test structure includes a protection diode, it will affect the subsequent testing of the semiconductor device, after forming the first pad 15 and the second pad 16, the testing method also includes: grounding the first pad 15 and applying a positive voltage to the second pad 16, so as to disconnect the fuse structure while avoiding damage to the device structure.

[0087] Preferably, the positive voltage applied to the second pad 16 is in the range of 2V to 5V.

[0088] Furthermore, when the fuse structure is a metal wire 19, Figure 3As shown, since the metal wire 19 is easier to be disconnected and form an open circuit than the metal interconnection line 17, the metal wire 19 is disconnected after the first pad 15 is grounded and a positive voltage is applied to the second pad 16. If the longitudinal cross-sectional area of ​​the metal wire 19 is smaller than the longitudinal cross-sectional area of ​​the metal interconnection line 17, when the first pad 15 is grounded and a positive voltage is applied to the second pad 16, the current density in the metal wire 19 is higher than the current density in the metal interconnection line 17, so that the metal wire 19 is burned out; if the anti-migration ability of the material of the metal wire 19 is lower than the anti-migration ability of the material of the metal interconnection line 17, when the first pad 15 is grounded and a positive voltage is applied to the second pad 16, under the action of a large current, the metal atoms in the metal wire 19 are easier to be pushed away than the metal atoms in the metal interconnection line 17, and the metal in the metal wire 19 migrates in the direction opposite to the current direction and disconnects, so that the metal wire 19 is disconnected.

[0089] When the fuse structure includes an insulating dielectric layer 211, a polysilicon layer 212 and a metal silicide layer 213 sequentially formed on the substrate 11, as shown in FIG. Figure 4 As shown, since the longitudinal cross-sectional area of ​​the metal silicide layer 213 is smaller than the longitudinal cross-sectional area of ​​the metal interconnection line 17, after the first pad 15 is grounded and a positive voltage is applied to the second pad 16, under the action of a large current, the metal in the metal silicide layer 213 migrates in a direction opposite to the current direction, thereby disconnecting the metal silicide layer 213.

[0090] In addition, after the fuse structure is disconnected, the testing method further includes: performing a test on the device structure.

[0091] Wherein, since the fuse structure is disconnected, the device structure is disconnected from the first protection diode and the second protection diode to form an open circuit, thereby preventing the protection diodes from affecting the test.

[0092] Furthermore, when the device structure is a MOS transistor, the test items may include an inversion test and an accumulation test, etc., to evaluate the quality of the gate oxide layer 121; when the device structure is a capacitor structure, it is necessary to perform an evaluation test on the quality of the inter-gate dielectric layer and the gate oxide layer to obtain reliability performance such as the breakdown time of the semiconductor device.

[0093] Among them, when the MOS transistor is an NMOS transistor, the inversion test is to apply a positive voltage to the gate layer 122 and the source region 123 and the substrate 11 are grounded to form an N channel, and then the electrical parameters such as saturation current, hot electron current carrying effect and turn-on resistance are obtained by testing; the accumulation test is to apply a negative voltage to the gate layer 122 and the source region 123 and the substrate 11 are grounded to make holes gather at the junction of the substrate 11 and the gate oxide layer 121, and then the parameters such as breakdown voltage are obtained. When the MOS transistor is a PMOS transistor, the inversion test is to apply a negative voltage to the gate layer 122 and the source region 123 and the substrate 11 are grounded, and the accumulation test is to apply a positive voltage to the gate layer 122 and the source region 123 and the substrate 11 are grounded, and the parameters obtained by the test are the same as above.

[0094] When the device structure is a capacitor structure, taking the capacitor structure as a PIP capacitor as an example, by applying a positive voltage to the control gate layer and a negative voltage to the floating gate layer, and by applying a negative voltage to the control gate layer and a positive voltage to the floating gate layer, the quality of the inter-gate dielectric layer is evaluated when voltages in different directions are applied, and reliability performance parameters such as breakdown time are obtained.

[0095] From the above content, it can be seen that since the fuse structure is disconnected before the device structure is tested, the device structure and the protection diode are disconnected, thereby avoiding the protection diode from affecting the test (the principle is described in the above test structure and will not be repeated here).

[0096] In summary, the present invention provides a shift test method, comprising: providing a wafer including the test structure; executing a production process, wherein the free positive charges and negative charges generated on the surface of the wafer by the production process are respectively conducted away through the first protection diode and the second protection diode. The test method provided by the present invention can improve the protection effect on the device structure while avoiding affecting the test of the device structure.

[0097] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A test structure, characterized in that: include: substrate; a device structure formed on the substrate; A first protection diode and a second protection diode are formed in the substrate, the first protection diode and the second protection diode are connected in parallel with the device structure, and the first protection diode and the second protection diode have opposite polarities; A first metal interconnect structure and a second metal interconnect structure, wherein the first metal interconnect structure is electrically connected to the device structure, and the second metal interconnect structure is electrically connected to the first protection diode and the second protection diode, and a fuse structure is connected between the first metal interconnect structure and the second metal interconnect structure, and the fuse structure is used to be disconnected after executing the production process and before executing the test.

2. The test structure according to claim 1, characterized in that The test structure also includes: a first pad electrically connected to the device structure through the first metal interconnect structure; The second pad is electrically connected to the first protection diode and the second protection diode through the second metal interconnection structure. The first metal interconnection structure and the second metal interconnection structure both include metal interconnection lines and conductive plugs electrically connected to the metal interconnection lines.

3. The test structure according to claim 2, characterized in that: The fuse structure is a metal line, which is easier to disconnect and form an open circuit than the metal interconnection line.

4. The test structure according to claim 2, characterized in that: The fuse structure comprises an insulating dielectric layer, a polysilicon layer and a metal silicide layer which are sequentially formed on the substrate, and a longitudinal cross-sectional area of ​​the metal silicide layer is smaller than a longitudinal cross-sectional area of ​​the metal interconnection line.

5. The test structure according to any one of claims 1 to 4, characterized in that: The device structure is a MOS transistor, which includes a gate oxide layer and a gate layer formed in sequence on the substrate, and the MOS transistor is an NMOS transistor or a PMOS transistor; the device structure is a capacitor structure, which includes an oxide layer, a floating gate layer, an inter-gate dielectric layer and a control gate layer formed in sequence on the substrate, or the capacitor structure includes the substrate and a gate oxide layer and a control gate layer formed in sequence on the substrate.

6. A testing method, characterized in that: include: Providing a wafer comprising the test structure as claimed in claim 1; A production process is performed, wherein the free positive charges and negative charges generated on the surface of the wafer by the production process are respectively conducted away through the first protection diode and the second protection diode.

7. The testing method according to claim 6, characterized in that: The test method also includes: forming a first pad, wherein the first pad is electrically connected to the device structure through the first metal interconnect structure; A second pad is formed, and the second pad is electrically connected to the first protection diode and the second protection diode through the second metal interconnection structure, and the first metal interconnection structure and the second metal interconnection structure each include a metal interconnection line and a conductive plug electrically connected to the metal interconnection line.

8. The testing method according to claim 7, characterized in that: The test method also includes: The first pad is grounded and a positive voltage is applied to the second pad to open the fuse structure.

9. The testing method according to claim 8, characterized in that: The fuse structure is a metal line, which is easier to disconnect and form an open circuit than the metal interconnection line; after the first pad is grounded and a positive voltage is applied to the second pad, the metal line is disconnected.

10. The testing method according to claim 8, characterized in that: The fuse structure includes an insulating dielectric layer, a polysilicon layer and a metal silicide layer formed in sequence on the substrate, wherein the longitudinal cross-sectional area of ​​the metal silicide layer is smaller than the longitudinal cross-sectional area of ​​the metal interconnection line; after the first pad is grounded and a positive voltage is applied to the second pad, the metal silicide layer is disconnected.

11. The testing method according to claim 8, characterized in that: After the fuse structure is disconnected, the testing method further comprises: Testing is performed on the device structure.

12. The testing method according to claim 6, characterized in that: The production process includes a deposition process or an etching process.

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