Circuit board structure

Abstract

This invention provides a circuit board structure including a substrate, a third dielectric layer, a fourth dielectric layer, a first external circuit layer, a second external circuit layer, a conductive via, a first annular barrier, and a second annular barrier. The conductive via penetrates the third, second, and fourth dielectric layers and electrically connects the first and second external circuit layers. The first annular barrier is disposed within the third dielectric layer, surrounds the conductive via, and electrically connects the first external circuit layer and the first internal circuit layer. The second annular barrier is disposed within the fourth dielectric layer, surrounds the conductive via, and electrically connects the second external circuit layer and the second internal circuit layer. The circuit board structure of this invention effectively prevents energy loss and reduces noise interference, resulting in better signal integrity.

Description

Technical Field

[0001] This invention relates to a substrate structure, and more particularly to a circuit board structure. Background Technology

[0002] In existing circuit boards, the design of coaxial vias requires one or more insulating layers between the inner and outer conductor layers for insulation. These insulating layers are formed through lamination. Therefore, impedance mismatch and electromagnetic interference (EMI) shielding gaps appear at the two ends of the coaxial via, thus affecting the integrity of high-frequency signals. Summary of the Invention

[0003] This invention relates to a circuit board structure that can effectively prevent energy loss and reduce noise interference, and can provide better signal integrity.

[0004] According to an embodiment of the present invention, a circuit board structure includes a substrate, a third dielectric layer, a fourth dielectric layer, a first external circuit layer, a second external circuit layer, a conductive via, a first annular barrier, and a second annular barrier. The substrate has an opening and includes a first dielectric layer, a second dielectric layer, a first internal circuit layer, a second internal circuit layer, and a conductive connection layer. The opening penetrates the first dielectric layer. The first dielectric layer has a first surface and a second surface opposite to each other. A first internal circuit layer is disposed on the first surface, and a second internal circuit layer is disposed on the second surface. The conductive connection layer covers the inner wall of the opening and connects the first internal circuit layer and the second internal circuit layer. The second dielectric layer fills the opening and has a third surface and a fourth surface opposite to each other. The third dielectric layer covers the first internal circuit layer and the third surface. The fourth dielectric layer covers the second internal circuit layer and the fourth surface. A first external circuit layer is disposed on the third dielectric layer. A second external circuit layer is disposed on the fourth dielectric layer. The conductive via penetrates the third dielectric layer, the second dielectric layer, and the fourth dielectric layer and electrically connects the first external circuit layer and the second external circuit layer. A first annular barrier is disposed within the third dielectric layer, surrounding the conductive via and electrically connecting the first external circuit layer and the first internal circuit layer. A second annular barrier is disposed within the fourth dielectric layer, surrounding the conductive via and electrically connecting the second external circuit layer and the second internal circuit layer.

[0005] According to an embodiment of the present invention, a circuit board structure includes a first substrate, a second substrate, a third dielectric layer, a fourth dielectric layer, a first annular barrier, and a second annular barrier. The first substrate includes a first dielectric layer, a first external circuit layer, a first conductive via, and a first internal circuit layer. The first external circuit layer and the first internal circuit layer are located on opposite sides of the first dielectric layer. The first conductive via penetrates the first dielectric layer and electrically connects the first external circuit layer and the first internal circuit layer. The second substrate includes a second dielectric layer, a second external circuit layer, a second conductive via, and a second internal circuit layer. The second external circuit layer and the second internal circuit layer are located on opposite sides of the second dielectric layer. The second conductive via penetrates the second dielectric layer and electrically connects the second external circuit layer and the second internal circuit layer. The third dielectric layer covers the first internal circuit layer. The fourth dielectric layer covers the second internal circuit layer. The first annular barrier is disposed within the third dielectric layer and electrically connected to the first internal circuit layer. The orthographic projection of the first annular barrier on the first substrate surrounds the first conductive via. The second annular barrier is disposed within the fourth dielectric layer and electrically connected to the second internal circuit layer. The orthographic projection of the second annular barrier on the second substrate surrounds the second conductive via. The third dielectric layer connects to the fourth dielectric layer, and a portion of the first annular barrier connects to a portion of the second annular barrier, thereby abutting the first substrate onto the second substrate.

[0006] Based on the above, in the circuit board structure design of the present invention, an annular barrier surrounds the conductive via, wherein the annular barrier is a closed boundary structure, which can reduce electromagnetic interference (EMI) and completely cover the signal of the conductive via. Compared with the prior art of setting a single row of blind vias with gaps around the conductive via, the circuit board structure of the present invention can effectively prevent energy loss and reduce noise interference, and can have better signal integrity. Attached Figure Description

[0007] Figure 1A This is a top view schematic diagram of a circuit board structure according to an embodiment of the present invention;

[0008] Figure 1B It is along Figure 1A A schematic cross-sectional view of line II;

[0009] Figure 1C It is along Figure 1A A schematic cross-sectional view of line II-II;

[0010] Figure 1D It is along Figure 1A A schematic cross-sectional view of line III-III;

[0011] Figure 2A This is a cross-sectional schematic diagram of a circuit board structure according to another embodiment of the present invention;

[0012] Figure 2B yes Figure 2A Another partial cross-sectional view of the circuit board structure;

[0013] Figure 2C yes Figure 2A A partial three-dimensional schematic diagram of the circuit board structure;

[0014] Figure 2D It includes Figure 2A A partial cross-sectional schematic diagram of an electronic device with a circuit board structure;

[0015] Figure 3A yes Figure 2A A top view of the first substrate, the third dielectric layer, and the first annular retaining wall of the circuit board structure;

[0016] Figure 3B It is along Figure 3A A schematic diagram of the cross section of line AA;

[0017] Figure 3C It is along Figure 3A A schematic cross-sectional view of line BB;

[0018] Figure 3D It is along Figure 3A A schematic cross-sectional view of line CC;

[0019] Figure 4A It is shown Figure 2A A top view of the second substrate, fourth dielectric layer, and second annular retaining wall of the circuit board structure;

[0020] Figure 4B It is along Figure 4A A schematic diagram of the cross section of line AA;

[0021] Figure 4C It is along Figure 4A A schematic cross-sectional view of line BB;

[0022] Figure 4D It is along Figure 4A A schematic cross-sectional view of line CC;

[0023] Figure 5A This is a cross-sectional schematic diagram of a circuit board structure according to another embodiment of the present invention;

[0024] Figure 5B yes Figure 5A Another partial cross-sectional view of the circuit board structure;

[0025] Figure 6A This is a cross-sectional schematic diagram of a circuit board structure according to another embodiment of the present invention;

[0026] Figure 6B yes Figure 6AAnother partial cross-sectional view of the circuit board structure;

[0027] Figure 7A This is a cross-sectional schematic diagram of a circuit board structure according to another embodiment of the present invention;

[0028] Figure 7B yes Figure 7A Another partial cross-sectional view of the circuit board structure.

[0029] Explanation of reference numerals in the attached figures

[0030] 10: Electronic devices;

[0031] 20: Electronic components;

[0032] 22: Pad;

[0033] 30: Connector;

[0034] 100, 200a, 200b, 200c, 200d: Circuit board structure;

[0035] 110: Base;

[0036] 111, 212: First dielectric layer;

[0037] 113, 222: Second dielectric layer;

[0038] 115, 218: First internal circuit layer;

[0039] 117, 228: Second internal circuit layer;

[0040] 119: Conductive connection layer;

[0041] 120, 230: Third dielectric layer;

[0042] 130, 240: Fourth dielectric layer;

[0043] 140, 214: First external circuit layer;

[0044] 142, 218a: First signal line;

[0045] 144, 218b: First grounding line;

[0046] 150, 224: Second external circuit layer;

[0047] 152, 228a: Second signal lines;

[0048] 154, 228b: Second grounding line;

[0049] 160: Conductive via;

[0050] 162: Through hole;

[0051] 164: Conductive material layer;

[0052] 166: Hole-filling material;

[0053] 167: Upper surface;

[0054] 169: Lower surface;

[0055] 170, 250: First ring retaining wall;

[0056] 180, 260: Second ring retaining wall;

[0057] 210: First basement;

[0058] 220: Second basement;

[0059] 216: First conductive via;

[0060] 226: Second conductive via;

[0061] 270: First joint;

[0062] 275: Second joint;

[0063] 280: Third joint;

[0064] 285: Fourth joint;

[0065] C1: Copper foil layer;

[0066] C2: Copper plating layer;

[0067] C3: Cover layer;

[0068] F1: First filler material;

[0069] F11: First upper surface;

[0070] F12: First lower surface;

[0071] F2: Second filler material;

[0072] F21: Second upper surface;

[0073] F22: Second lower surface;

[0074] H: Opening;

[0075] L1: Signal path;

[0076] L2, L3, L4, L5: Grounding paths;

[0077] M1: First conductive material layer;

[0078] M2: Second conductive material layer;

[0079] P1, P2, P3: Location;

[0080] S1: First surface;

[0081] S2: Second surface;

[0082] S3: Third surface;

[0083] S4: Fourth surface;

[0084] T1: First through hole;

[0085] T2: Second through hole. Detailed Implementation

[0086] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0087] Figure 1A This is a top view schematic diagram of a circuit board structure according to an embodiment of the present invention. Figure 1B It is along Figure 1A A schematic cross-sectional view of line II. Figure 1C It is along Figure 1A A schematic cross-sectional view of line II-II. Figure 1D It is along Figure 1A A schematic cross-sectional view of line III-III. Please also refer to... Figure 1A , Figure 1B , Figure 1C as well as Figure 1D In this embodiment, the circuit board structure 100 includes a substrate 110, a third dielectric layer 120, a fourth dielectric layer 130, a first external circuit layer 140, a second external circuit layer 150, a conductive via 160, a first annular barrier 170, and a second annular barrier 180.

[0088] In detail, in this embodiment, the substrate 110 has an opening H and includes a first dielectric layer 111, a second dielectric layer 113, a first internal circuit layer 115, a second internal circuit layer 117, and a conductive connection layer 119. The opening H penetrates the first dielectric layer 111, and the first dielectric layer 111 has a first surface S1 and a second surface S2 opposite to each other. The first internal circuit layer 115 is disposed on the first surface S1 of the first dielectric layer 111, while the second internal circuit layer 117 is disposed on the second surface S2 of the first dielectric layer 111. The conductive connection layer 119 covers the inner wall of the opening H and connects the first internal circuit layer 115 and the second internal circuit layer 117. The second dielectric layer 113 fills the opening H, and the second dielectric layer 113 has a third surface S3 and a fourth surface S4 opposite to each other, wherein the third surface S3 and the fourth surface S4 are respectively flush with the first internal circuit layer 115 and the second internal circuit layer 117. Here, the first dielectric layer 111 can use a general dielectric material, wherein the dielectric constant of the first dielectric layer 111 can be less than 4.0, and the dielectric loss (Df) of the first dielectric layer 111 can be less than 0.01, thereby providing appropriate impedance matching. The dielectric constant of the second dielectric layer 113 can be less than 5.0, and the dielectric loss (Df) of the second dielectric layer 113 is greater than 0 and less than 0.025, in order to provide appropriate insulation and impedance matching, and also to reduce dielectric loss.

[0089] Furthermore, in this embodiment, the third dielectric layer 120 covers the third surface S3 of the first internal circuit layer 115 and the second dielectric layer 113. The fourth dielectric layer 130 covers the fourth surface S4 of the second internal circuit layer 117 and the second dielectric layer 113. The first external circuit layer 140 is disposed on the third dielectric layer 120, and the second external circuit layer 150 is disposed on the fourth dielectric layer 130. The conductive via 160 penetrates the third dielectric layer 120, the second dielectric layer 113, and the fourth dielectric layer 130, and electrically connects the first external circuit layer 140 and the second external circuit layer 150. The conductive via 160 includes a through-hole 162, a conductive material layer 164, and a via-filling material 166. The through-hole 162 penetrates the third dielectric layer 120, the second dielectric layer 113, and the fourth dielectric layer 130. A conductive material layer 164 covers the inner wall of the through-hole 162 and electrically connects the first external circuit layer 140 and the second external circuit layer 150. A via-filling material 166 fills the through-hole 162, and the first external circuit layer 140 and the second external circuit layer 150 respectively cover the upper surface 167 and lower surface 169 of the via-filling material 166. Here, the first external circuit layer 140 and the second external circuit layer 150 are multilayer structures, each composed of a copper foil layer C1, a copper plating layer C2, and a capping layer C3. The copper plating layer C2 is located between the copper foil layer C1 and the capping layer C3, and the copper plating layer C2 and the conductive material layer 164 belong to the same film layer. The capping layer C3 is, for example, a copper layer, but is not limited to this, and covers the upper surface 167 and lower surface 169 of the via-filling material 166.

[0090] Specifically, in this embodiment, the first annular barrier 170 is embedded within the third dielectric layer 120, surrounds the conductive via 160, and is electrically connected to the first external circuit layer 140 and the first internal circuit layer 115. The second annular barrier 180 is embedded within the fourth dielectric layer 130, surrounds the conductive via 160, and is electrically connected to the second external circuit layer 150 and the second internal circuit layer 117. The first external circuit layer 140, the conductive via 160, and the second external circuit layer 150 define a signal path L1. The first external circuit layer 150, the first annular barrier 170, the first internal circuit layer 115, the connecting circuit layer 119, the second internal circuit layer 117, the second annular barrier 180, and the second external circuit layer 150 define a ground path L2, and the ground path L2 surrounds the signal path L1.

[0091] To go further, please refer to Figure 1BThe first external circuit layer 140 includes a first signal line 142 and a first ground line 144. The second external circuit layer 150 includes a second signal line 152 and a second ground line 154. The first signal line 142, the conductive via 160, and the second signal line 152 define a signal path L1. The first ground line 144, the first annular barrier 170, the first internal circuit layer 115, the conductive connection layer 119, the second internal circuit layer 117, the second annular barrier 180, and the second ground line 154 define a ground path L2. Because the signal path L1 is surrounded by the ground path L2 and is enclosed, a good high-frequency, high-speed loop can be formed.

[0092] In addition, please refer to Figure 1C as well as Figure 1D The first signal line 142 is surrounded and enclosed by the grounding path L3 defined by the first annular barrier 170 and the first internal line layer 115, while the second signal line 152 is surrounded and enclosed by the grounding path L4 defined by the second annular barrier 180 and the second internal line layer 117, thus forming a good high-frequency and high-speed loop.

[0093] In terms of manufacturing process, if the third dielectric layer 120 and the fourth dielectric layer 130 are, for example, photoimageable dielectric (PID) materials, they can be first dry-film laminated onto opposite sides of the substrate 110, and then closed trenches with a width of, for example, 100 micrometers and a diameter of, for example, 600 micrometers can be formed on the third dielectric layer 120 and the fourth dielectric layer 130 respectively through a photolithography process. Alternatively, if the third dielectric layer 120 and the fourth dielectric layer 130 are, for example, prepreg or Ajinomoto build-up film (ABF), closed trenches with a width of, for example, 100 micrometers and a diameter of, for example, 600 micrometers can be formed on the third dielectric layer 120 and the fourth dielectric layer 130 respectively through laser ablation. Next, conductive metal paste (such as conductive copper paste) is applied to the trench using Transient Liquid Phase Sintering (TLPS) and then air-dried. This process provides both electrical and thermal conductivity, and the paste is suitable for bonding with any metal material. Furthermore, it will not revert to a liquid state when heated, thus completing the fabrication of the first annular barrier 170 and the second annular barrier 180.

[0094] It should be noted that, in this embodiment, the first annular barrier 170 and the second annular barrier 180 are formed by filling the third dielectric layer 120 and the fourth dielectric layer 130 with conductive paste. Therefore, the first annular barrier 170 and the second annular barrier 180 are solid barrier structures, but this is not a limitation. The conductive material of the annular barrier can also be a metal electroplated layer or a chemically plated metal layer. In another embodiment not shown, the first annular barrier and the second annular barrier can also be formed by forming a metal electroplated layer, a chemically plated metal layer, or a metal conductive paste in the third dielectric layer and the fourth dielectric layer. Therefore, the first annular barrier and the second annular barrier can be grooved barrier structures, which are still within the scope of protection of this invention.

[0095] In short, in this embodiment, the signal path L1 defined by the first signal line 142, the conductive via 160, and the second signal line 152 is surrounded by a grounding path L2 defined by the first grounding line 144, the first annular barrier 170, the first internal circuit layer 115, the conductive connection layer 119, the second internal circuit layer 117, the second annular barrier 180, and the second grounding line 154. That is, a well-sealed grounding path L2 is provided around the signal path L1, which can transmit high-frequency and high-speed signals such as 5G, thereby forming a good high-frequency and high-speed loop, resulting in better signal integrity for the circuit board structure 100 of this embodiment. Here, high frequency refers to a frequency greater than 1 GHz; and high speed refers to a data transmission speed greater than 100 Mbps. Furthermore, since the first annular barrier 170 and the second annular barrier 180 are closed boundary structures, they can completely cover the signal of the conductive via 160. Compared to the prior art where a single row of blind vias with gaps is arranged around conductive vias, the circuit board structure 100 of this embodiment can effectively prevent energy loss and reduce noise interference, thus providing better signal integrity. Furthermore, the conductive via 160, the conductive connection layer 119, and the second dielectric layer 113 define a coaxial via, wherein the second dielectric layer 113 is located between the conductive via 160 and the conductive connection layer 119. Compared to the prior art method of using a lamination insulating layer to block the inner and outer conductor layers of the coaxial via, the fabrication method of the circuit board structure 100 of this embodiment avoids the problem of impedance mismatch affecting the integrity of high-frequency signals.

[0096] Figure 2A This is a cross-sectional schematic diagram of a circuit board structure according to another embodiment of the present invention. Figure 2B yes Figure 2A Another partial cross-sectional view of the circuit board structure. Figure 2C yes Figure 2A A partial three-dimensional schematic diagram of the circuit board structure. Figure 2DIt includes Figure 2A A partial cross-sectional schematic diagram of an electronic device with a circuit board structure. Figure 3A yes Figure 2A A top view of the first substrate, third dielectric layer, and first annular retaining wall of the circuit board structure. Figure 3B It is along Figure 3A The cross-sectional diagram of line AA, i.e., the cross-sectional diagram located at position P1. Figure 3C It is along Figure 3A The cross-sectional view of line BB is shown, that is, the cross-sectional view at position P2. Figure 3D It is along Figure 3A The cross-sectional view of line CC, i.e., the cross-sectional view at position P3. Figure 4A It is shown Figure 2A A top view of the second substrate, fourth dielectric layer, and second annular retaining wall of the circuit board structure. Figure 4B It is along Figure 4A The schematic diagram of the cross section of line AA, that is, the schematic diagram of the cross section located at position P1. Figure 4C It is along Figure 4A The cross-sectional view of line BB is shown, that is, the cross-sectional view at position P2. Figure 4D It is along Figure 4A The diagram shows a cross-sectional view of line CC, specifically the cross-sectional view at position P3. It should be noted that... Figure 2A It is along Figure 3A and Figure 4A A cross-sectional schematic diagram of line EE in the diagram, and Figure 2B This is a schematic cross-sectional view showing the first base 210 at position P1 and the second base 220 at position P1 after docking.

[0097] First, please refer to Figure 2A , Figure 2C , Figure 3A as well as Figure 4A In this embodiment, the circuit board structure 200 includes a first substrate 210, a second substrate 220, a third dielectric layer 230, a fourth dielectric layer 240, a first annular barrier 250, and a second annular barrier 260.

[0098] For details, please refer to [the relevant documentation / reference]. Figure 2A , Figure 3A , Figure 3B , Figure 3C as well as Figure 3DIn this embodiment, the first substrate 210 includes a first dielectric layer 212, a first external circuit layer 214, a first conductive via 216, and a first internal circuit layer 218. The first external circuit layer 214 and the first internal circuit layer 218 are located on opposite sides of the first dielectric layer 212. The first conductive via 216 penetrates the first dielectric layer 212 and electrically connects the first external circuit layer 214 and the first internal circuit layer 218. Here, as... Figure 3B As shown, the first conductive via 216 in this embodiment includes a first through-hole T1, a first conductive material layer M1, and a first via-filling material F1. The first through-hole T1 penetrates the first dielectric layer 212, and the first conductive material layer M1 covers the inner wall of the first through-hole T1 and is electrically connected to the first external circuit layer 214 and the first internal circuit layer 218. The first via-filling material F1 fills the first through-hole T1, and the first internal circuit layer 218 and the first external circuit layer 214 respectively cover the first upper surface F11 and the first lower surface F12 of the first via-filling material F1 that are opposite to each other. The third dielectric layer 230 covers the first internal circuit layer 218 of the first substrate 210. The first annular barrier 250 is embedded in the third dielectric layer 230 and is electrically connected to the first internal circuit layer 218, wherein the orthographic projection of the first annular barrier 250 on the first substrate 210 surrounds the first conductive via 216.

[0099] Furthermore, please also refer to Figure 3A , Figure 3B as well as Figure 3D The circuit board structure 200a of this embodiment further includes a first bonding portion 270 and a second bonding portion 275. The first bonding portion 270 and the second bonding portion 275 are disposed on the first internal circuit layer 218, and a first annular barrier 250 surrounds the first bonding portion 270 and the second bonding portion 275, wherein the first bonding portion 270 is provided corresponding to the first conductive via 216. Furthermore, the first internal circuit layer 218 of this embodiment includes a first signal line 218a and a first ground line 218b. The first annular barrier 250 is disposed on the first ground line 218b, while the first bonding portion 270 and the second bonding portion 275 are disposed on the first signal line 218a.

[0100] In terms of manufacturing process, the first bonding portion 270 and the second bonding portion 275 are formed simultaneously with the first annular barrier 250. Specifically, if the third dielectric layer 230 is, for example, a photoimageable dielectric (PID) material, it can be first dry-film laminated to opposite sides of the first substrate 210, and closed trenches and openings can be formed on the third dielectric layer 230 using a photolithography process. Alternatively, if the third dielectric layer 230 is, for example, a prepreg or Ajinomoto build-up film (ABF), closed trenches and openings can be formed on the third dielectric layer 230 by laser ablation. Next, conductive metal paste (such as conductive copper paste) is applied to the closed trench and opening using transient liquid phase sintering (TLPS) and then air-dried. This process provides both electrical and thermal conductivity, is suitable for bonding with any metal material, and will not revert to a liquid state upon heating. This completes the fabrication of the first annular barrier 250 in the closed trench and the first and second joints 270 and 275 in the opening. Here, the width of the first joint 270 and the width of the second joint 275 are both greater than the width of the first annular barrier 250.

[0101] Next, please refer to Figure 2A , Figure 4A , Figure 4B , Figure 4C as well as Figure 4D In this embodiment, the second substrate 220 includes a second dielectric layer 222, a second external circuit layer 224, a second conductive via 226, and a second internal circuit layer 228. The second external circuit layer 224 and the second internal circuit layer 228 are located on opposite sides of the second dielectric layer 222. The second conductive via 226 penetrates the second dielectric layer 222 and electrically connects the second external circuit layer 224 and the second internal circuit layer 228. Figure 4BAs shown, the second conductive via 226 in this embodiment includes a second through-hole T2, a second conductive material layer M2, and a second via-filling material F2. The second through-hole T2 penetrates the second dielectric layer 222, while the second conductive material layer M2 covers the inner wall of the second through-hole T2 and is electrically connected to the second external circuit layer 224 and the second internal circuit layer 228. The second via-filling material F2 fills the second through-hole T2, and the second internal circuit layer 228 and the second external circuit layer 224 respectively cover the second upper surface F21 and the second lower surface F22 of the second via-filling material F2 that are opposite to each other. The fourth dielectric layer 240 covers the second internal circuit layer 228 of the second substrate 220. The second annular barrier 260 is embedded in the fourth dielectric layer 240 and is electrically connected to the second internal circuit layer 228, wherein the orthographic projection of the second annular barrier 260 on the second substrate 220 surrounds the second conductive via 226.

[0102] Furthermore, please also refer to Figure 4A , Figure 4B as well as Figure 4D The circuit board structure 200a of this embodiment further includes a third joint 280 and a fourth joint 285. The third joint 280 and the fourth joint 285 are disposed on the second internal circuit layer 228, and a second annular barrier 260 surrounds the third joint 280 and the fourth joint 285, wherein the third joint 280 is provided corresponding to the second conductive via 226. Furthermore, the second internal circuit layer 228 of this embodiment includes a second signal line 228a and a second ground line 228b. The second annular barrier 260 is disposed on the second ground line 228b, while the third joint 280 and the fourth joint 285 are disposed on the second signal line 228a.

[0103] In terms of manufacturing process, the third bonding portion 280 and the fourth bonding portion 285 are formed simultaneously with the second annular barrier 260. Specifically, if the fourth dielectric layer 240 is, for example, a photoimageable dielectric (PID) material, it can be first dry-film laminated to opposite sides of the second substrate 220, and closed trenches and openings can be formed on the fourth dielectric layer 240 using a photolithography process. Alternatively, if the fourth dielectric layer 240 is, for example, a prepreg or Ajinomoto build-up film (ABF), closed trenches and openings can be formed on the fourth dielectric layer 240 by laser ablation. Next, conductive metal paste (such as conductive copper paste) is applied to the closed trench and opening using transient liquid phase sintering (TLPS) and then air-dried. This provides both electrical and thermal conductivity, is suitable for bonding with any metal material, and will not revert to a liquid state upon heating. This completes the fabrication of the second annular barrier 260 formed in the closed trench and the third and fourth joints 280 and 285 formed in the opening. Here, the width of the third joint 280 and the width of the fourth joint 285 are both greater than the width of the second annular barrier 260.

[0104] Next, please refer to the following: Figure 2A , Figure 2B as well as Figure 2C The third dielectric layer 230 connects to the fourth dielectric layer 240, and a portion of the first annular barrier 250 connects to a portion of the second annular barrier 260, thereby connecting the first substrate 210 to the second substrate 220. At this time, the first junction 270 joins to the third junction 280, and the first conductive via 216 overlaps the second conductive via 226, the first junction 270, and the third junction 280. The second ground line 228b, the second annular barrier 260, the first annular barrier 250, and the first ground line 218b define a ground path L5, which surrounds the first junction 270 and the third junction 280. In other words, in this embodiment, high-frequency, high-speed signals are placed in the inner layers (i.e., the first signal line 218a and the second signal line 228a), and a well-sealed ground path L5 is provided around them, thereby forming a good high-frequency, high-speed loop, resulting in better signal integrity for the circuit board structure 200a of this embodiment.

[0105] In addition, please refer to Figure 2D In this embodiment, the electronic device 10 includes, for example, the above-mentioned... Figure 2BThe circuit board structure 200a and electronic component 20 are included, wherein the electronic component 20 is electrically connected to the circuit board structure 200a and includes a plurality of pads 22. Furthermore, the electronic device 10 of this embodiment also includes a plurality of connectors 30 disposed between the first external circuit layer 214 of the first substrate 210 of the circuit board structure 200a and the pads 22 of the electronic component 20, wherein the electronic component 20 is electrically connected to the circuit board structure 200a via the connectors 30. Here, the connectors 30 are, for example, solder balls, but are not limited thereto. In application, an antenna structure can be provided on the other side of the circuit board structure 200a opposite to the electronic component 20, and the antenna structure is electrically connected to the first external circuit layer 224 of the second substrate 220 of the circuit board structure 200a. In the application of integrated circuits and antennas, the circuit board structure 200a of this embodiment can solve the problem of signal interference in the same plane, reduce signal energy loss and noise interference, thereby improving signal transmission reliability.

[0106] Figure 5A This is a cross-sectional schematic diagram of a circuit board structure according to another embodiment of the present invention. Figure 5B yes Figure 5A Another partial cross-sectional view of the circuit board structure. Please also refer to... Figure 2A , Figure 2B , Figure 5A as well as Figure 5B The circuit board structure 200b of this embodiment is similar to the circuit board structure 200a described above, except that in this embodiment, the first substrate 210 at position P1 is mated to the second substrate 220 at position P3. When the first substrate 210 is mated to the second substrate 220, the first joint 270 is mated to the fourth joint 285, and a portion of the first annular barrier 250 is mated to a portion of the second annular barrier 260. At this time, the first conductive via 216 does not overlap the second conductive via 226, and the first conductive via 216 overlaps the first joint 270 and the fourth joint 285, thereby forming a fan-out circuit board structure 200b to facilitate diverse subsequent applications.

[0107] Figure 6A This is a cross-sectional schematic diagram of a circuit board structure according to another embodiment of the present invention. Figure 6B yes Figure 6A Another partial cross-sectional view of the circuit board structure. Please also refer to... Figure 2A , Figure 2B , Figure 6A as well as Figure 6BThe circuit board structure 200c of this embodiment is similar to the circuit board structure 200a described above, except that in this embodiment, the first substrate 210 at position P3 is mated to the second substrate 220 at position P1. When the first substrate 210 is mated to the second substrate 220, the second joint 275 is mated to the third joint 280, and a portion of the first annular barrier 250 is mated to a portion of the second annular barrier 260. At this time, the first conductive via 216 does not overlap the second conductive via 226, and the second conductive via 226 overlaps the third joint 280 and the second joint 275, thereby forming a fan-out circuit board structure 200c to facilitate diverse subsequent applications.

[0108] Figure 7A This is a cross-sectional schematic diagram of a circuit board structure according to another embodiment of the present invention. Figure 7B yes Figure 7A Another partial cross-sectional view of the circuit board structure. Please also refer to... Figure 2A , Figure 2B , Figure 7A as well as Figure 7B The circuit board structure 200d in this embodiment is similar to the circuit board structure 200a described above, except that in this embodiment, the first substrate 210 at position P3 is mated to the second substrate 220 at position P3. When the first substrate 210 is mated to the second substrate 220, the second joint 275 is mated to the fourth joint 285, and a portion of the first annular barrier 250 is mated to a portion of the second annular barrier 260. At this time, the first conductive via 216 does not overlap the second conductive via 226, the second joint 275, and the fourth joint 285, thereby forming a fan-out circuit board structure 200d to facilitate diverse subsequent applications.

[0109] In summary, in the circuit board structure design of this invention, an annular barrier surrounds the conductive vias. This annular barrier is a closed boundary structure, which reduces electromagnetic interference (EMI) and completely covers the signals from the conductive vias. Compared to the prior art where a single row of blind vias with gaps is arranged around the conductive vias, the circuit board structure of this invention effectively prevents energy loss and reduces noise interference, resulting in better signal integrity.

[0110] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A circuit board structure, characterized by, Comprising: a substrate having an opening and comprising a first dielectric layer, a second dielectric layer, a first inner circuit layer, a second inner circuit layer, and a conductive connection layer, wherein the opening penetrates through the first dielectric layer, the first dielectric layer has a first surface and a second surface opposite to each other, the first inner circuit layer is disposed on the first surface, the second inner circuit layer is disposed on the second surface, the conductive connection layer covers inner walls of the opening and connects the first inner circuit layer and the second inner circuit layer, the second dielectric layer fills the opening, and the second dielectric layer has a third surface and a fourth surface opposite to each other; a third dielectric layer covering the first inner circuit layer and the third surface; a fourth dielectric layer covering the second inner circuit layer and the fourth surface; a first outer circuit layer disposed on the third dielectric layer; a second outer circuit layer disposed on the fourth dielectric layer; a conductive via penetrating through the third dielectric layer, the second dielectric layer, and the fourth dielectric layer and electrically connecting the first outer circuit layer and the second outer circuit layer; a first ring-shaped barrier disposed in the third dielectric layer, surrounding the conductive via, and electrically connecting the first outer circuit layer and the first inner circuit layer; and a second ring-shaped barrier disposed in the fourth dielectric layer, surrounding the conductive via, and electrically connecting the second outer circuit layer and the second inner circuit layer. The first outer circuit layer, the conductive via, and the second outer circuit layer define a signal path, and the first outer circuit layer, the first ring-shaped barrier, the first inner circuit layer, the conductive connection layer, the second inner circuit layer, the second ring-shaped barrier, and the second outer circuit layer define a ground path, and the ground path surrounds the signal path.

2. The circuit board structure according to claim 1, characterized by The first outer circuit layer comprises a first signal line and a first ground line, and the second outer circuit layer comprises a second signal line and a second ground line, the first signal line, the conductive via, and the second signal line define the signal path, and the first ground line, the first ring-shaped barrier, the first inner circuit layer, the conductive connection layer, the second inner circuit layer, the second ring-shaped barrier, and the second ground line define the ground path.

3. The circuit board structure according to claim 2, characterized by The conductive via comprises a via hole, a conductive material layer, and a via filling material, the via hole penetrates through the third dielectric layer, the second dielectric layer, and the fourth dielectric layer, the conductive material layer covers inner walls of the via hole and electrically connects the first outer circuit layer and the second outer circuit layer, the via filling material fills the via hole, and the first outer circuit layer and the second outer circuit layer cover upper and lower surfaces of the via filling material opposite to each other, respectively.

4. The circuit board structure according to claim 1, characterized by Comprising:

5. A circuit board structure, characterized by, ​ A first substrate includes a first dielectric layer, a first external circuit layer, a first conductive via, and a first internal circuit layer, wherein the first external circuit layer and the first internal circuit layer are respectively located on opposite sides of the first dielectric layer, and the first conductive via penetrates the first dielectric layer and electrically connects the first external circuit layer and the first internal circuit layer; A second substrate includes a second dielectric layer, a second external circuit layer, a second conductive via, and a second internal circuit layer, wherein the second external circuit layer and the second internal circuit layer are respectively located on opposite sides of the second dielectric layer, and the second conductive via penetrates the second dielectric layer and electrically connects the second external circuit layer and the second internal circuit layer; A third dielectric layer covers the first internal circuit layer; A fourth dielectric layer covers the second internal circuit layer; A first ring-shaped barrier wall is disposed in the third dielectric layer and electrically connected to the first internal circuit layer, wherein the first ring-shaped barrier wall has a projection on the first substrate that surrounds the first conductive via; and A second ring-shaped barrier wall is disposed in the fourth dielectric layer and electrically connected to the second internal circuit layer, wherein the second ring-shaped barrier wall has a projection on the second substrate that surrounds the second conductive via, the third dielectric layer is connected to the fourth dielectric layer, and part of the first ring-shaped barrier wall is connected to part of the second ring-shaped barrier wall, so that the first substrate is connected to the second substrate.

6. The circuit board structure according to claim 5, characterized by Further comprising: A first joint and a second joint are disposed on the first internal circuit layer, and the first ring-shaped barrier wall surrounds the first joint and the second joint, wherein the first joint is provided corresponding to the first conductive via; and A third joint and a fourth joint are disposed on the second internal circuit layer, and the second ring-shaped barrier wall surrounds the third joint and the fourth joint, wherein the third joint is provided corresponding to the second conductive via; Wherein the first internal circuit layer includes a first signal line and a first ground line, the first ring-shaped barrier wall is disposed on the first ground line, and the first joint and the second joint are disposed on the first signal line, and the second internal circuit layer includes a second signal line and a second ground line, the second ring-shaped barrier wall is disposed on the second ground line, and the third joint and the fourth joint are disposed on the second signal line.

7. The circuit board structure according to claim 6, characterized in that When the first substrate is connected to the second substrate, the first joint is connected to the third joint, part of the first ring-shaped barrier wall is connected to part of the second ring-shaped barrier wall, the first conductive via overlaps the second conductive via, the first joint, and the third joint, the first ground line, the first ring-shaped barrier wall, the second ring-shaped barrier wall, and the second ground line define a ground path, and the ground path surrounds the first joint and the third joint.

8. The circuit board structure of claim 6, wherein When the first substrate is docked to the second substrate, the first bonding portion is bonded to the fourth bonding portion, part of the first ring-shaped barrier wall is bonded to part of the second ring-shaped barrier wall, the first conductive via does not overlap the second conductive via, and the first conductive via overlaps the first bonding portion and the fourth bonding portion.

9. The circuit board structure of claim 6, wherein, When the first substrate is docked to the second substrate, the second bonding portion is bonded to the third bonding portion, part of the first ring-shaped barrier wall is bonded to part of the second ring-shaped barrier wall, the first conductive via does not overlap the second conductive via, and the second conductive via overlaps the third bonding portion and the second bonding portion.

10. The circuit board structure of claim 6, wherein, When the first substrate is docked to the second substrate, the second bonding portion is bonded to the fourth bonding portion, part of the first ring-shaped barrier wall is bonded to part of the second ring-shaped barrier wall, the first conductive via does not overlap the second conductive via, the second bonding portion and the fourth bonding portion.

11. The circuit board structure of claim 5, wherein the first conductive via includes a first through-hole, a first conductive material layer and a first via-filling material, the first through-hole penetrates the first dielectric layer, the first conductive material layer covers inner walls of the first through-hole and electrically connects the first external circuit layer and the first internal circuit layer, the first via-filling material fills the first through-hole, and the first internal circuit layer and the first external circuit layer respectively cover first upper and lower surfaces of the first via-filling material opposite to each other; and the second conductive via includes a second through-hole, a second conductive material layer and a second via-filling material, the second through-hole penetrates the second dielectric layer, the second conductive material layer covers inner walls of the second through-hole and electrically connects the second external circuit layer and the second internal circuit layer, the second via-filling material fills the second through-hole, and the second internal circuit layer and the second external circuit layer respectively cover second upper and lower surfaces of the second via-filling material opposite to each other. ​

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