Method for manufacturing image display device and image display device

Abstract

The manufacturing method of the image display device according to the embodiment includes the steps of: preparing a semiconductor layer; bonding the semiconductor layer to a first substrate via a first metal layer; bonding the semiconductor layer to a light-transmissive substrate; removing the first substrate and etching the semiconductor layer to form a light-emitting element including a light-emitting surface and an upper surface; etching the first metal layer to form a light-blocking electrode covering the upper surface; forming a first insulating film covering the light-emitting element and the light-blocking electrode; forming a circuit element on the first insulating film; forming a second insulating film covering the first insulating film and the circuit element; forming a first through-hole penetrating the first insulating film and the second insulating film; and forming a first wiring layer on the second insulating film.

Description

Technical Field

[0001] The embodiments of the present invention relate to a method for manufacturing an image display device and an image display device. Background Technology

[0002] There is a growing demand for thin image display devices that offer high brightness, wide viewing angles, high contrast, and low power consumption. To meet these market demands, the development of display devices utilizing self-emissive elements is underway.

[0003] As self-emissive elements, the emergence of display devices using micro-LEDs, which are tiny light-emitting elements, is anticipated. A method for manufacturing display devices using micro-LEDs has been described, which involves sequentially transferring individually formed micro-LEDs to a driving circuit. However, as high-definition formats such as Full HD, 4K, and 8K become more demanding and the number of micro-LEDs increases, sequentially transferring many individually formed micro-LEDs to a substrate with driving circuitry would require a significant amount of time. Furthermore, issues such as poor connections between the micro-LEDs and the driving circuitry may arise, leading to a decrease in yield.

[0004] The following techniques are known: growing a semiconductor layer including a light-emitting layer on a Si substrate, forming electrodes on the semiconductor layer, and then attaching it to a circuit board on which a driving circuit is formed (for example, see Patent Document 1).

[0005] Existing technical documents

[0006] Patent documents

[0007] Patent Document 1: Japanese Patent Application Publication No. 2002-141492 Summary of the Invention

[0008] The technical problem that the invention aims to solve

[0009] One embodiment of the present invention provides a method for manufacturing an image display device and an image display device that shortens the transfer process of the light-emitting element and improves the yield.

[0010] Technical solutions for solving technical problems

[0011] An embodiment of the present invention relates to a method for manufacturing an image display device, comprising: a step of preparing a semiconductor layer including a light-emitting layer; a step of bonding the semiconductor layer to a first substrate via a first metal layer; a step of attaching the semiconductor layer to a first surface of a light-transmitting substrate; a step of removing the first substrate; a step of etching the semiconductor layer to form a light-emitting element including a light-emitting surface on the first surface and an upper surface disposed on the opposite side of the light-emitting surface; a step of etching the first metal layer to form a light-shielding electrode covering the upper surface and electrically connected to the upper surface; a step of forming a first insulating film covering the first surface, the light-emitting element, and the light-shielding electrode; a step of forming a circuit element on the first insulating film; a step of forming a second insulating film covering the first insulating film and the circuit element; a step of forming a first via penetrating the first insulating film and the second insulating film; and a step of forming a first wiring layer on the second insulating film. The first via is disposed between the first wiring layer and the light-shielding electrode, electrically connecting the first wiring layer and the light-shielding electrode.

[0012] An embodiment of the present invention relates to a method for manufacturing an image display device, comprising: a step of preparing a semiconductor layer including a light-emitting layer; a step of bonding the semiconductor layer to a first surface of a light-transmitting substrate; a step of forming a second metal layer on the semiconductor layer after removing the first substrate; a step of etching the semiconductor layer to form a light-emitting element including a light-emitting surface on the first surface and an upper surface disposed on the opposite side of the light-emitting surface; a step of etching the second metal layer to form a light-shielding electrode covering the upper surface and electrically connected to the upper surface; a step of forming a first insulating film covering the first surface, the light-emitting element, and the light-shielding electrode; a step of forming a circuit element on the first insulating film; a step of forming a second insulating film covering the circuit element and the first insulating film; a step of forming a first via penetrating the first insulating film and the second insulating film; and a step of forming a first wiring layer on the second insulating film. The first via is disposed between the first wiring and the light-shielding electrode, electrically connecting the first wiring and the light-shielding electrode.

[0013] An embodiment of the present invention relates to an image display device comprising: a light-transmitting component having a first surface; a light-emitting element including a light-emitting surface on the first surface and an upper surface opposite to the light-emitting surface; a light-shielding electrode covering the upper surface and electrically connected to the upper surface; a first insulating film covering the first surface, the light-emitting element, and the light-shielding electrode; a circuit element disposed on the first insulating film; a second insulating film covering the first insulating film and the circuit element; a first via disposed through the first insulating film and the second insulating film; and a first wiring layer disposed on the second insulating film. The first via is disposed between the first wiring layer and the light-shielding electrode, electrically connecting the first wiring layer and the light-shielding electrode.

[0014] An embodiment of the present invention relates to an image display device comprising: a light-transmitting component having a first surface; a first semiconductor layer having a light-emitting surface on the first surface capable of forming a plurality of light-emitting regions; a plurality of light-emitting layers disposed on and spaced apart from the first semiconductor layer; a plurality of second semiconductor layers respectively disposed on the plurality of light-emitting layers and having a conductivity type different from the first semiconductor layer; a plurality of light-shielding electrodes respectively disposed on and electrically connected to the plurality of second semiconductor layers; a first insulating film covering the first surface, the first semiconductor layer, the plurality of light-emitting layers, the plurality of second semiconductor layers, and the plurality of light-shielding electrodes; a plurality of transistors disposed spaced apart from each other on the first insulating film; a second insulating film covering the first insulating film and the plurality of transistors; a plurality of first vias disposed in a manner penetrating the first insulating film and the second insulating film; and a first wiring layer disposed on the second insulating film. The plurality of second semiconductor layers and the plurality of light-emitting layers are separated by the first insulating film. The plurality of first vias are respectively disposed between the first wiring layer and the plurality of light-shielding electrodes, electrically connecting the first wiring layer and the plurality of light-shielding electrodes respectively.

[0015] An embodiment of the present invention relates to an image display device comprising: a light-transmitting component having a first surface; a plurality of light-emitting elements including a light-emitting surface on the first surface and an upper surface opposite to the light-emitting surface; a plurality of light-shielding electrodes covering the upper surface and electrically connected to the upper surface; a first insulating film covering the first surface, the plurality of light-emitting elements, and the plurality of light-shielding electrodes; a circuit element disposed on the first insulating film; a second insulating film covering the first insulating film and the circuit element; a plurality of first vias disposed through the first insulating film and the second insulating film; and a first wiring layer disposed on the second insulating film. The plurality of first vias are disposed between the first wiring layer and the plurality of light-shielding electrodes, electrically connecting the first wiring layer and the plurality of light-shielding electrodes respectively.

[0016] The effects of the invention

[0017] According to one embodiment of the present invention, a method for manufacturing an image display device can be realized that shortens the transfer process of the light-emitting element and improves the yield.

[0018] According to one embodiment of the present invention, an image display device can be realized that shortens the transfer process of the light-emitting element and improves the yield. Attached Figure Description

[0019] Figure 1 This is a schematic cross-sectional view illustrating a portion of the image display device according to the first embodiment.

[0020] Figure 2 This is a schematic block diagram illustrating the image display device according to the first embodiment.

[0021] Figure 3 This is a schematic plan view illustrating a portion of the image display device according to the first embodiment.

[0022] Figure 4A This is a schematic cross-sectional view illustrating a part of the manufacturing method of the image display device according to the first embodiment.

[0023] Figure 4B This is a schematic cross-sectional view illustrating a part of the manufacturing method of the image display device according to the first embodiment.

[0024] Figure 5A This is a schematic cross-sectional view illustrating a part of the manufacturing method of the image display device according to the first embodiment.

[0025] Figure 5B This is a schematic cross-sectional view illustrating a part of the manufacturing method of the image display device according to the first embodiment.

[0026] Figure 6 This is a schematic perspective view illustrating a part of the manufacturing method of the image display device according to the first embodiment.

[0027] Figure 7A This is a schematic cross-sectional view illustrating a part of the manufacturing method of the image display device according to the first embodiment.

[0028] Figure 7B This is a schematic cross-sectional view illustrating a part of the manufacturing method of the image display device according to the first embodiment.

[0029] Figure 8A This is a schematic cross-sectional view illustrating a part of the manufacturing method of the image display device according to the first embodiment.

[0030] Figure 8BThis is a schematic cross-sectional view illustrating a part of the manufacturing method of the image display device according to the first embodiment.

[0031] Figure 9 This is a schematic perspective view illustrating the image display device according to the first embodiment.

[0032] Figure 10 This is a schematic cross-sectional view illustrating a portion of the image display device according to the second embodiment.

[0033] Figure 11 This is a schematic block diagram illustrating the image display device according to the second embodiment.

[0034] Figure 12A This is a schematic cross-sectional view illustrating a part of the manufacturing method of the image display device according to the second embodiment.

[0035] Figure 12B This is a schematic cross-sectional view illustrating a part of the manufacturing method of the image display device according to the second embodiment.

[0036] Figure 13 This is a schematic cross-sectional view illustrating a part of the manufacturing method of the image display device according to the second embodiment.

[0037] Figure 14A This is a schematic cross-sectional view illustrating a part of the manufacturing method of the image display device according to the second embodiment.

[0038] Figure 14B This is a schematic cross-sectional view illustrating a part of the manufacturing method of the image display device according to the second embodiment.

[0039] Figure 15A This is a schematic cross-sectional view illustrating a part of the manufacturing method of the image display device according to the second embodiment.

[0040] Figure 15B This is a schematic cross-sectional view illustrating a part of the manufacturing method of the image display device according to the second embodiment.

[0041] Figure 16A This is a schematic cross-sectional view illustrating a part of the manufacturing method of the image display device according to the second embodiment.

[0042] Figure 16B This is a schematic cross-sectional view illustrating a part of the manufacturing method of the image display device according to the second embodiment.

[0043] Figure 17A This is a schematic cross-sectional view illustrating a part of the manufacturing method of the image display device according to the second embodiment.

[0044] Figure 17BThis is a schematic cross-sectional view illustrating a part of the manufacturing method of the image display device according to the second embodiment.

[0045] Figure 18 This is a schematic cross-sectional view illustrating a portion of the image display device according to the third embodiment.

[0046] Figure 19 This is a schematic block diagram illustrating the image display device according to the third embodiment.

[0047] Figure 20A This is a schematic cross-sectional view illustrating a part of the manufacturing method of the image display device according to the third embodiment.

[0048] Figure 20B This is a schematic cross-sectional view illustrating a part of the manufacturing method of the image display device according to the third embodiment.

[0049] Figure 21A This is a schematic cross-sectional view illustrating a part of the manufacturing method of the image display device according to the third embodiment.

[0050] Figure 21B This is a schematic cross-sectional view illustrating a part of the manufacturing method of the image display device according to the third embodiment.

[0051] Figure 22A This is a schematic cross-sectional view illustrating a part of the manufacturing method of the image display device according to the third embodiment.

[0052] Figure 22B This is a schematic cross-sectional view illustrating a part of the manufacturing method of the image display device according to the third embodiment.

[0053] Figure 23A This is a schematic cross-sectional view illustrating a part of the manufacturing method of the image display device according to the third embodiment.

[0054] Figure 23B This is a schematic cross-sectional view illustrating a part of the manufacturing method of the image display device according to the third embodiment.

[0055] Figure 24A This is a schematic cross-sectional view illustrating a part of the manufacturing method of the image display device according to the third embodiment.

[0056] Figure 24B This is a schematic cross-sectional view illustrating a part of the manufacturing method of the image display device according to the third embodiment.

[0057] Figure 24C This is a schematic cross-sectional view illustrating a part of the manufacturing method of the image display device according to the third embodiment.

[0058] Figure 24D This is a schematic cross-sectional view illustrating a part of the manufacturing method of the image display device according to the third embodiment.

[0059] Figure 25 This is a schematic perspective view illustrating the image display device according to the third embodiment.

[0060] Figure 26 This is a schematic cross-sectional view illustrating a portion of the image display device according to the fourth embodiment.

[0061] Figure 27 This is a schematic block diagram illustrating the image display device according to the fourth embodiment.

[0062] Figure 28A This is a schematic cross-sectional view illustrating a part of the manufacturing method of the image display device according to the fourth embodiment.

[0063] Figure 28B This is a schematic cross-sectional view illustrating a part of the manufacturing method of the image display device according to the fourth embodiment.

[0064] Figure 29A This is a schematic cross-sectional view illustrating a part of the manufacturing method of the image display device according to the fourth embodiment.

[0065] Figure 29B This is a schematic cross-sectional view illustrating a part of the manufacturing method of the image display device according to the fourth embodiment.

[0066] Figure 30A This is a schematic cross-sectional view illustrating a part of the manufacturing method of the image display device according to the fourth embodiment.

[0067] Figure 30B This is a schematic cross-sectional view illustrating a part of the manufacturing method of the image display device according to the fourth embodiment.

[0068] Figure 31 This is a schematic cross-sectional view illustrating a part of the manufacturing method of the image display device according to the fourth embodiment.

[0069] Figure 32 This is a schematic cross-sectional view illustrating a portion of the image display device according to the fifth embodiment.

[0070] Figure 33 This is a schematic cross-sectional view illustrating a portion of the image display device according to the fifth embodiment.

[0071] Figure 34 This is a schematic cross-sectional view illustrating a portion of the image display device according to the sixth embodiment.

[0072] Figure 35This is a schematic cross-sectional view illustrating a portion of the image display device according to the sixth embodiment.

[0073] Figure 36 This is a block diagram illustrating an image display device according to the seventh embodiment.

[0074] Figure 37 This is a block diagram illustrating a variation of the seventh embodiment involving an image display device. Detailed Implementation

[0075] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0076] It should be noted that the accompanying drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the sizes between parts, etc., may not be the same as in reality. In addition, even when representing the same parts, there are cases where the accompanying drawings show them in different ways with different dimensions and ratios.

[0077] It should be noted that in this application specification and figures, the same reference numerals are used for the same elements as those mentioned in the figures that have already appeared, and detailed descriptions are appropriately omitted.

[0078] (First Implementation)

[0079] Figure 1 This is a schematic cross-sectional view illustrating a portion of the image display device involved in this embodiment.

[0080] exist Figure 1 The structure of the sub-pixel 20 of the image display device according to this embodiment is schematically shown. In the second, fifth, and sixth embodiments described below, examples are shown where a color filter is not installed. Therefore, in image display devices that are set to black and white, for example, the sub-pixel becomes one pixel. In this specification, whether one pixel is formed using one sub-pixel or one pixel is formed using multiple sub-pixels, the light-emitting element including one light-emitting element is referred to as a sub-pixel.

[0081] The following explanations will sometimes use a three-dimensional coordinate system of XYZ. (As will be discussed later.) Figure 9 As shown, the light-emitting elements 150 are arranged in a two-dimensional plane. Each light-emitting element 150 is configured for each sub-pixel 20. The two-dimensional plane with the sub-pixels 20 arranged is designated as the XY plane. The sub-pixels 20 are arranged along the X-axis and Y-axis directions. Figure 1 This indicates what will be described later. Figure 3 The view section at line AA' is a sectional view obtained by connecting sections at multiple planes perpendicular to the XY plane on a single plane. The same applies to other figures. Figure 1 Therefore, in the sectional views at multiple planes perpendicular to the XY plane, the X and Y axes are not shown, but the Z axis, which is perpendicular to the XY plane, is shown. That is, in these drawings, the plane perpendicular to the Z axis is designated as the XY plane.

[0082] In the following text, the positive direction of the Z-axis will sometimes be referred to as "up" or "above," and the negative direction as "down" or "below." However, the direction along the Z-axis is not necessarily limited to the direction in which gravity is applied. Sometimes, the length along the Z-axis is called the height.

[0083] Sub-pixel 20 has a light-emitting surface 151S that is substantially parallel to the XY plane. The light-emitting surface 151S is a surface that emits light primarily in the negative direction of the Z-axis, which is orthogonal to the XY plane. In this embodiment and all embodiments described below, the light-emitting surface emits light in the negative direction of the Z-axis.

[0084] like Figure 1 As shown, the sub-pixel 20 of the image display device includes a substrate 102, a light-emitting element 150, a light-shielding electrode 160a, a first interlayer insulating film 156, a transistor (circuit element) 103, a second interlayer insulating film 108, a via 161a, and a first wiring layer 110.

[0085] In this embodiment, the substrate 102 has two surfaces, and an adhesive layer 303 is provided on one surface 102a. The adhesive layer 303 has a first surface 103a. The first surface 103a is a flat surface that is substantially parallel to the XY plane. In the case where a color filter is provided in the image display device of this embodiment, the color filter is formed on the other surface 102b of the substrate 102. The other surface 102b is the surface opposite to the surface 102a. Regarding other embodiments described later, even without a color filter, the color filter may also be provided on the surface opposite to the surface on which the light-emitting element is formed among the two surfaces of the substrate, as described above.

[0086] The substrate 102 is a light-transmitting component, such as a glass substrate. The bonding layer 303 is formed of a light-transmitting material, such as a layer formed of an oxide or nitride of an inorganic material like SiO2. The bonding layer 303 provides a flat surface for arranging a plurality of light-emitting elements 150 on the first surface 103a. The bonding layer 303 is provided to facilitate bonding in the wafer bonding process of the manufacturing method of the image display device of this embodiment.

[0087] A light-emitting element 150 is disposed on the first surface 103a. The light-emitting element 150 is driven by a transistor 103 disposed with a first interlayer insulating film 156 in between. The transistor 103 is a thin-film transistor (TFT) and is formed on the first interlayer insulating film 156. The process of forming circuit elements including TFTs on a large glass substrate has been established for the manufacture of liquid crystal panels, organic EL panels, etc., and has the advantage of being able to utilize existing factories.

[0088] The structure of subpixel 20 will be explained in detail below.

[0089] The light-emitting element 150 includes a light-emitting surface 151S disposed on the first surface 103a. The light-emitting element 150 also includes an upper surface 153U disposed on the opposite side of the light-emitting surface 151S. In this example, the outer periphery of the light-emitting surface 151S and the upper surface 153U, when viewed in the XY plane, is square or rectangular, and the light-emitting element 150 is a prism-shaped element having the light-emitting surface 151S on the first surface 103a. The cross-section of the prism can also be a polygon with a pentagon or larger shape. The light-emitting element 150 is not limited to a prism-shaped element; it can also be a cylindrical element.

[0090] The light-emitting element 150 includes an n-type semiconductor layer 151, a light-emitting layer 152, and a p-type semiconductor layer 153. The n-type semiconductor layer 151, the light-emitting layer 152, and the p-type semiconductor layer 153 are stacked sequentially from the light-emitting surface 151S toward the upper surface 153U. The light-emitting surface 151S of the n-type semiconductor layer 151 is arranged in contact with the first surface 103a. Therefore, the light-emitting element 150 emits light in the negative Z-axis direction via the bonding layer 303 and the substrate 102.

[0091] The n-type semiconductor layer 151 includes a connection portion 151a. The connection portion 151a is provided such that it protrudes in one direction from the n-type semiconductor layer 151 on the first surface 103a. The height of the connection portion 151a from the first surface 103a is the same as, or lower than, the height of the n-type semiconductor layer 151 from the first surface 103a. The n-type semiconductor layer 151 includes the connection portion 151a. The connection portion 151a is a part of the n-type semiconductor layer 151. The connection portion 151a is connected to one end of a via 161k, and the n-type semiconductor layer 151 is electrically connected to the via 161k via the connection portion 151a.

[0092] When the light-emitting element 150 is prismatic, its shape when viewed in the XY plane is, for example, approximately square or rectangular. When the shape of the light-emitting element 150 when viewed in the XY plane is a polygon including a square, the corners of the light-emitting element 150 may also be rounded. When the shape of the light-emitting element 150 when viewed in the XY plane is cylindrical, its shape is not limited to a circle; for example, it may be elliptical. By appropriately selecting the shape, arrangement, etc., of the light-emitting element when viewed from above, the freedom of wiring layout, etc., is increased.

[0093] For the light-emitting element 150, it is preferred to use, for example, In X Al Y Ga 1-X-Y Gallium nitride (GaN) compound semiconductors with a light-emitting layer of N (0≤X, 0≤Y, X+Y<1), etc. Hereinafter, the aforementioned gallium nitride compound semiconductors are sometimes simply referred to as gallium nitride (GaN). In one embodiment of the present invention, the light-emitting element 150 is a so-called light-emitting diode (LED). The wavelength of the light emitted by the light-emitting element 150 can be within the near-ultraviolet to visible light range, for example, approximately 467 nm ± 30 nm. The wavelength of the light emitted by the light-emitting element 150 can also be set to approximately 410 nm ± 30 nm, emitting blue-violet light. The wavelength of the light emitted by the light-emitting element 150 is not limited to the above values ​​and can be set to suitable values.

[0094] A light-shielding electrode 160a is provided all over the upper surface 153U. The light-shielding electrode 160a is located between the upper surface 153U and one end of the via 161a. The light-shielding electrode 160a is formed of a conductive material with light-shielding properties and is formed to a sufficient thickness to achieve its light-shielding function. The light-shielding electrode 160a is ohmically connected to the p-type semiconductor layer 153 and blocks upward-radiated and scattered light. By providing the light-shielding electrode 160a, light can be suppressed from reaching the transistor 103, which is located above the light-emitting element 150.

[0095] A first interlayer insulating film (first insulating film) 156 covers the first surface 103a, the light-emitting element 150, and the light-shielding electrode 160a. The first interlayer insulating film 156 electrically separates adjacent light-emitting elements 150. The first interlayer insulating film 156 also electrically separates the light-shielding electrode 160a disposed on the electrically separated light-emitting elements 150. The first interlayer insulating film 156 electrically separates the light-emitting element 150 and the light-shielding electrode 160a from circuit elements such as the transistor 103. The first interlayer insulating film 156 provides a flat surface for forming a circuit 101 including circuit elements such as the transistor 103. The first interlayer insulating film 156 protects the light-emitting element 150 from thermal stress and other factors encountered during the formation of the transistor 103 by covering it.

[0096] The first interlayer insulating film 156 is formed of an organic insulating material. The organic insulating material used in the first interlayer insulating film 156 is preferably a white resin. By using a white resin for the first interlayer insulating film 156, it is possible to reflect the lateral emitted light from the light-emitting element 150, as well as the reflected light caused by the interfaces between the bonding layer 303 and the substrate 102. Therefore, the luminous efficiency of the light-emitting element 150 is substantially improved.

[0097] White resin is formed by dispersing scattering particles exhibiting Mie scattering effect in a transparent resin such as a silicone-based resin (SOG, Spin-on Glass) or a phenolic varnish-type phenolic resin. The scattering particles are colorless or white and have a diameter approximately 1 / 10 to several times the wavelength of the light emitted by the light-emitting element 150. Preferably, the scattering particles have a diameter approximately 1 / 2 the wavelength of the light. Examples of such scattering particles include TiO2, Al2O3, and ZnO.

[0098] Alternatively, white resin can also be formed by utilizing numerous fine pores dispersed within transparent resin. When whitening the first interlayer insulating film 156, it can also be superimposed on SOG or the like, using SiO2 films formed by ALD (Atomic Layer Deposition) or CVD.

[0099] The first interlayer insulating film 156 can also be made of black resin. By making the first interlayer insulating film 156 black resin, light scattering within the sub-pixel 20 is suppressed, and stray light is suppressed more effectively. Image display devices with suppressed stray light are able to display sharper images.

[0100] A TFT lower layer film 106 is formed over the first interlayer insulating film 156. The TFT lower layer film 106 is provided to ensure flatness during the formation of the transistor 103 and to protect the TFT channel 104 of the transistor 103 from contamination during heat treatment. The TFT lower layer film 106 is, for example, an insulating film such as SiO2.

[0101] Transistor 103 is formed on the lower TFT film 106. Besides transistor 103, other circuit elements such as transistors and capacitors are formed on the lower TFT film 106, and circuit 101 is constructed using wiring, etc. For example, as described later... Figure 2 In this configuration, transistor 103 corresponds to driving transistor 26. Furthermore, in... Figure 2 In the circuit, transistor 24, capacitor 28, etc. are selected as circuit elements. Circuit 101 includes TFT channel 104, insulating layer 105, second interlayer insulating film 108, vias 111s and 111d, and first wiring layer 110.

[0102] In this example, transistor 103 is a p-channel TFT. Transistor 103 includes a TFT channel 104 and a gate 107. The TFT channel 104 is preferably formed using a low-temperature polysilicon (LTPS) process. In the LTPS process, the TFT channel 104 is formed by polycrystallineizing and activating a region of amorphous Si formed on the lower TFT film 106. For example, laser-based laser annealing is used for the polycrystallineization and activation of the amorphous Si region. TFTs formed using the LTPS process have sufficiently high mobility.

[0103] The TFT channel 104 includes regions 104s, 104i, and 104d. Regions 104s, 104i, and 104d are all disposed on the lower TFT film 106. Region 104i is disposed between regions 104s and 104d. Regions 104s and 104d are doped with boron ions (B). + ) or boron fluoride ions (BF) 2+ P-type impurities, such as those found in the guide holes 111s and 111d, are connected to the guide holes.

[0104] The gate 107 is disposed on the TFT channel 104 through an insulating layer 105. The insulating layer 105 is disposed to insulate the TFT channel 104 and the gate 107 and from other adjacent circuit elements. If a potential lower than that of region 104s is applied to the gate 107, a channel is formed in region 104i, thereby enabling control of the current flowing between regions 104s and 104d.

[0105] The insulating layer 105 is, for example, SiO2. The insulating layer 105 may also be a multilayer insulating layer containing SiO2, Si3N4, etc., depending on the area it covers.

[0106] The gate 107 can be formed, for example, from polycrystalline Si or from high-melting-point metals such as W or Mo. When the gate 107 is formed from a polycrystalline Si film, it is formed, for example, by CVD or the like.

[0107] A second interlayer insulating film 108 is disposed on the gate 107 and the insulating layer 105. The second interlayer insulating film 108 is formed, for example, of the same material as the first interlayer insulating film 156. That is, the second interlayer insulating film 108 is formed of an inorganic film such as white resin or SiO2. The second interlayer insulating film 108 also functions as a planarization film for the formation of the first wiring layer 110.

[0108] Vias 111s and 111d are provided to penetrate the second interlayer insulating film 108 and the insulating layer 105. A first wiring layer 110 is formed on the second interlayer insulating film 108. The first wiring layer 110 includes multiple wires with potentially different potentials. In this example, the first wiring layer 110 includes wires 110s, 110d, and 110k. These wires 110s, 110d, and 110k are formed separately.

[0109] A portion of wiring 110s is positioned above area 104s. Other portions of wiring 110s are connected, for example, to [the area described later]. Figure 2 The power cord 3 is shown. A portion of the wiring (first wiring) 110d is disposed above region 104d. The remaining portion of wiring 110d is disposed above the upper surface 153U. A portion of wiring (second wiring) 110k is disposed above the connection portion 151a. The remaining portion of wiring 110k is connected, for example, to the connection described later. Figure 2 The grounding wire 4 is shown in the circuit diagram.

[0110] exist Figure 1 In subsequent sectional views, unless otherwise specified, the reference numerals indicating the wiring layer will be displayed next to the wiring that constitutes the wiring layer.

[0111] A via 111s is disposed between wiring 110s and area 104s, electrically connecting wiring 110s and area 104s. A via 111d is disposed between wiring 110d and area 104d, electrically connecting wiring 110d and area 104d.

[0112] Wiring 110s is connected to region 104s via via 111s. Region 104s is the source region of transistor 103. Therefore, the source region of transistor 103 is electrically connected to power line 3 via via 111s and wiring 110s.

[0113] Wiring 110d is connected to region 104d via via 111d. Region 104d is the drain region of transistor 103.

[0114] A via (first via) 161a is provided to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the first interlayer insulating film 156. The via 161a is disposed between the wiring (first wiring) 110d and the light-shielding electrode 160a, electrically connecting the wiring 110d and the light-shielding electrode 160a. Therefore, the p-type semiconductor layer 153 is electrically connected to the drain region of the transistor 103 via the light-shielding electrode 160a, the via 161a, the wiring 110d, and the via 111d.

[0115] The via (second via) 161k is provided in such a manner that it penetrates the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the first interlayer insulating film 156. The via 161k is disposed between the wiring (second wiring) 110k and the connection portion 151a, electrically connecting the wiring 110k and the connection portion 151a. Therefore, the n-type semiconductor layer 151 is connected, for example, to the connection portion 151a, the via 161k, and the wiring 110k. Figure 2 The grounding wire 4 of the circuit is electrically connected.

[0116] The first wiring layer 110 and the vias 111s, 111d, and 161k are formed, for example, from Al, an alloy of Al, or a laminated film of Al and Ti. For example, in an Al and Ti laminated film, Al is laminated on a thin film of Ti, and Ti is laminated on Al.

[0117] Alternatively, a protective layer covering them to protect them from the external environment may be provided across the second interlayer insulation film 108 and the first wiring layer 110.

[0118] Figure 2 This is a schematic block diagram illustrating the image display device according to this embodiment.

[0119] like Figure 2 As shown, the image display device 1 of this embodiment includes a display area 2. Subpixels 20 are arranged in the display area 2. The subpixels 20 are arranged in a grid pattern, for example. For example, n subpixels 20 are arranged along the X-axis and m subpixels are arranged along the Y-axis.

[0120] The image display device 1 also includes a power supply line 3 and a grounding line 4. The power supply line 3 and the grounding line 4 are arranged in a grid pattern along the arrangement of the sub-pixels 20. The power supply line 3 and the grounding line 4 are electrically connected to each sub-pixel 20, supplying power to each sub-pixel 20 from a DC power supply connected between the power supply terminal 3a and the GND terminal 4a. The power supply terminal 3a and the GND terminal 4a are respectively located at the ends of the power supply line 3 and the grounding line 4, and are connected to a DC power supply circuit located outside the display area 2. The power supply terminal 3a is supplied with a positive voltage with reference to the GND terminal 4a.

[0121] The image display device 1 also includes scan lines 6 and signal lines 8. The scan lines 6 are arranged in a direction parallel to the X-axis. That is, the scan lines 6 are arranged along the row direction of the sub-pixels 20. The signal lines 8 are arranged in a direction parallel to the Y-axis. That is, the signal lines 8 are arranged along the column direction of the sub-pixels 20.

[0122] The image display device 1 also includes a row selection circuit 5 and a signal voltage output circuit 7. The row selection circuit 5 and the signal voltage output circuit 7 are disposed along the outer edge of the display area 2. The row selection circuit 5 is disposed along the Y-axis direction of the outer edge of the display area 2. The row selection circuit 5 is electrically connected to the sub-pixels 20 of each column via scan lines 6 and supplies selection signals to each sub-pixel 20.

[0123] The signal voltage output circuit 7 is arranged along the X-axis direction of the outer edge of the display area 2. The signal voltage output circuit 7 is electrically connected to the sub-pixels 20 of each row via the signal line 8, and supplies signal voltage to each sub-pixel 20.

[0124] Sub-pixel 20 includes a light-emitting element 22, a selection transistor 24, a driving transistor 26, and a capacitor 28. Figure 2 And as will be discussed later Figure 3 In this context, sometimes the selection transistor 24 is denoted as T1, the drive transistor 26 as T2, and the capacitor 28 as Cm.

[0125] The light-emitting element 22 is connected in series with the driving transistor 26. In this embodiment, the driving transistor 26 is a p-channel TFT, and the anode electrode of the light-emitting element 22 is connected to the drain electrode of the driving transistor 26. The main electrodes of the driving transistor 26 and the selection transistor 24 are the drain electrode and the source electrode, respectively. The anode electrode of the light-emitting element 22 is connected to a p-type semiconductor layer. The cathode electrode of the light-emitting element 22 is connected to an n-type semiconductor layer. The series circuit of the light-emitting element 22 and the driving transistor 26 is connected between the power supply line 3 and the ground line 4. The driving transistor 26 corresponds to... Figure 1 In the transistor 103, the light-emitting element 22 corresponds to Figure 1 The light-emitting element 150 in the light-emitting element 22. The current flowing to the light-emitting element 22 is determined by the voltage applied between the gate and source of the driving transistor 26, and the light-emitting element 22 emits light with a brightness corresponding to the current flowing to the light-emitting element 22.

[0126] Select transistor 24 is connected via the main electrode between the gate electrode of drive transistor 26 and signal line 8. The gate electrode of select transistor 24 is connected to scan line 6. A capacitor 28 is connected between the gate electrode of drive transistor 26 and power supply line 3.

[0127] The row selection circuit 5 selects one row from the arrangement of m rows of sub-pixels 20 and supplies a selection signal to the scan line 6. The signal voltage output circuit 7 supplies a signal voltage with the required analog voltage value to each sub-pixel 20 of the selected row. The signal voltage is applied between the gate and source of the driving transistor 26 of the sub-pixel 20 of the selected row. The signal voltage is held by the capacitor 28. The driving transistor 26 causes a current corresponding to the signal voltage to flow to the light-emitting element 22. The light-emitting element 22 emits light with a brightness corresponding to the flowing current.

[0128] The row selection circuit 5 sequentially switches the selected rows by supplying selection signals. That is, the row selection circuit 5 scans the rows in which the sub-pixels 20 are arranged. The light-emitting elements 22 of the sequentially scanned sub-pixels 20 emit light by current flowing to them in accordance with the signal voltage. The brightness of the sub-pixels 20 is determined by the current flowing to the light-emitting elements 22. The sub-pixels 20 emit light at a grayscale based on the determined brightness, displaying an image in the display area 2.

[0129] Figure 3 This is a schematic top view illustrating a portion of the image display device of this embodiment.

[0130] exist Figure 3 In the middle, the AA' line represents Figure 1 The cut line in the sectional view. In this embodiment, the light-emitting element 150 and the driving transistor 103 are stacked in the Z-axis direction separated by a first interlayer insulating film 156. Figure 2 The corresponding element is the light-emitting element 22. The driving transistor 103 is located in... Figure 2 The one corresponding to the driving transistor 26 is also denoted as T2.

[0131] like Figure 3 As shown, the cathode electrode of the light-emitting element 150 is provided by a connection portion 151a. The connection portion 151a is disposed below the transistor 103 and the first wiring layer 110. The connection portion 151a is electrically connected to the wiring 110k via a via 161k. More specifically, one end of the via 161k is connected to the connection portion 151a. The other end of the via 161k is connected to the wiring 110k via a contact hole 161k1.

[0132] The anode electrode of the light-emitting element 150 is made of Figure 1 A p-type semiconductor layer 153 is provided. A light-shielding electrode 160a is disposed on the upper surface 153U of the p-type semiconductor layer 153. The light-shielding electrode 160a is connected to the wiring 110d via a via 161a. More specifically, one end of the via 161a is connected to the light-shielding electrode 160a. The other end of the via 161a is connected to the wiring 110d via a contact hole 161a1.

[0133] The other end of wiring 110d is via Figure 1 The via 111d shown is connected to the drain electrode of transistor 103. The drain electrode of transistor 103 is... Figure 1 The region shown is 104d. The source electrode of transistor 103 is via... Figure 1 The via 111s shown is connected to wiring 110s. The source electrode of transistor 103 is... Figure 1The area 104s is shown. In this example, the first wiring layer 110 includes power line 3, and wiring 110s is connected to power line 3.

[0134] In this example, the grounding wire 4 is positioned further above the first wiring layer 110. Although in Figure 1 The diagram is omitted, but an interlayer insulating film is also provided on the first wiring layer 110. The grounding wire 4 is provided on the uppermost interlayer insulating film and is insulated from the power line 3.

[0135] In this way, the light-emitting element 150 can be electrically connected to the first wiring layer 110 disposed above the light-emitting element 150 by using vias 161k and 161a.

[0136] The manufacturing method of the image display device 1 of this embodiment will be described.

[0137] Figures 4A to 5B This is a schematic cross-sectional view illustrating a part of the manufacturing method of the image display device according to this embodiment.

[0138] like Figure 4A As shown, in the manufacturing method of the image display device 1 of this embodiment, a semiconductor growth substrate 1194 is prepared. The semiconductor growth substrate 1194 includes a crystal growth substrate 1001 and a semiconductor layer 1150. The crystal growth substrate 1001 is, for example, a Si substrate, a sapphire substrate, etc. Preferably, a Si substrate is used as the crystal growth substrate 1001. In addition, when using a low-temperature crystal growth process such as low-temperature sputtering as described later, a cheaper glass substrate or the like can also be used.

[0139] A semiconductor layer 1150 is formed on a crystal growth substrate 1001. The semiconductor layer 1150 includes an n-type semiconductor layer 1151, a light-emitting layer 1152, and a p-type semiconductor layer 1153. The n-type semiconductor layer 1151, the light-emitting layer 1152, and the p-type semiconductor layer 1153 are stacked sequentially from the crystal growth substrate 1001 side.

[0140] In the formation of the semiconductor layer 1150, chemical vapor deposition (CVD) is used, preferably metal-organic chemical vapor deposition (MOCVD). Alternatively, epitaxial crystal growth of the semiconductor layer 1150 can be achieved even at process temperatures below 700°C using cryogenic sputtering. By using such cryogenic sputtering, glass substrates and devices with low heat resistance can be used, thus reducing manufacturing costs.

[0141] Semiconductor layer 1150, for example, contains GaN, and more specifically, contains In. X Al Y Ga 1-X-Y N(0≤X, 0≤Y, X+Y<1), etc.

[0142] In the early stages of crystal growth, crystal defects sometimes occur due to lattice constant mismatch, resulting in an n-type crystal. Therefore, in the case where the semiconductor layer 1150 is formed from the n-type semiconductor layer 1151 on the crystal growth substrate 1001 as in this example, there is a large margin in the manufacturing process, thus offering the advantage of easily improving the yield.

[0143] A metal layer (first metal layer) 1161 is formed on the p-type semiconductor layer 1153. The metal layer 1161 is formed on the exposed surface 1153E of the p-type semiconductor layer 1153.

[0144] When a semiconductor layer 1150 is formed on a crystal growth substrate 1001, the semiconductor layer 1150 can also be formed with a buffer layer in between. The buffer layer may be, for example, a nitride such as AlN. By growing the semiconductor layer 1150 on the crystal growth substrate 1001 with a buffer layer in between, the mismatch at the interface between the GaN crystal and the crystal growth substrate 1001 can be mitigated. Therefore, the quality of the semiconductor crystal in the semiconductor layer 1150 can be improved. On the other hand, in this embodiment, since the n-type semiconductor layer 1151 is bonded to the first surface 103a, a step of removing the buffer layer before bonding is added. The same applies to the other embodiments described later.

[0145] like Figure 4B As shown, a support substrate (first substrate) 1190 is prepared. A metal layer (first metal layer) 1162 is formed on one surface 1190E of the support substrate 1190. The support substrate 1190 is formed, for example, from quartz glass, Si, etc.

[0146] The semiconductor growth substrate 1194 is arranged such that the metal layer 1161 formed on the semiconductor growth substrate 1194 and the metal layer 1162 formed on the support substrate 1190 face each other. The semiconductor layer 1150 is bonded to the support substrate 1190 via the metal layers 1161 and 1162. The metal layers 1161 and 1162 can be any conductive material with light-shielding properties, and can be the same material or different materials. The metal layers only need to be formed into Figure 1 In the case of the light-shielding electrode 160a shown, it can be made to have sufficient thickness to provide light shielding, and it can also be formed on either the semiconductor growth substrate 1194 or the support substrate 1190.

[0147] After the semiconductor layer 1150 is bonded to the support substrate 1190 via the metal layer (first metal layer) 1163, the crystal growth substrate 1001 is removed, as follows: Figure 5A As shown, substrate 1195 is formed. Metal layer 1163 is a bonding formation of two metal layers 1161 and 1162. Figure 4B In the removal of the crystal growth substrate 1001 shown, wet etching or laser stripping may be used, for example.

[0148] The semiconductor layer 1150 of substrate 1195 is bonded to the first surface 103a of substrate 102, which serves as a light-transmitting substrate. The surface bonded to the first surface 103a is the exposed surface 1151E of the n-type semiconductor layer 1151. Then, as... Figure 5B As shown, the support substrate 1190 is removed. The support substrate 1190 is also removed using wet etching and laser stripping.

[0149] In the substrate bonding process, for example, the substrates are bonded together by heating and hot-pressing each substrate. In addition to the above, the bonding surfaces of each substrate can be planarized by chemical mechanical polishing (CMP) or the like, and then the bonding surfaces can be cleaned and sealed by plasma treatment in a vacuum.

[0150] When bonding the semiconductor layer 1150 to the substrate 102, there are cases where one semiconductor layer 1150 is bonded to one substrate 102 and cases where multiple semiconductor layers 1150 are bonded to one substrate 102. When bonding one semiconductor layer 1150 to one substrate 102, the size of the substrate 102 can be, for example, a rectangular shape or a square shape with a side length of about 10 mm to 150 mm. In this case, the semiconductor layer 1150 formed on the substrate 1195 can be set to a size corresponding to the size of the substrate 102.

[0151] When multiple semiconductor layers 1150 are bonded to a substrate 102, the substrate 102 can be, for example, a roughly rectangular glass substrate of about 1500 mm × 1800 mm. The semiconductor layers 1150 formed on the substrate 1195 are rectangular or square with side lengths of about 10 mm to 150 mm, which, in wafer size, can be, for example, about 4 inches to 6 inches. The size of the substrate 102 is appropriately selected according to the size of the image display device, etc.

[0152] Figure 6 This is a perspective view illustrating a part of the manufacturing method of the image display device according to this embodiment.

[0153] Figure 6 An example of bonding multiple semiconductor layers 1150 to a substrate 102 is illustrated schematically.

[0154] Figure 6 The diagram above the arrow shows multiple substrates 1195 arranged in a grid pattern. Figure 6 The figure below the arrow shows a substrate 102 with an adhesive layer 303 formed thereon. Figure 6 Arrows indicate that multiple substrates 1195, configured in a grid pattern, are bonded to the positions indicated by the double-dotted lines.

[0155] The quality of the semiconductor crystal degrades at and near the end of the semiconductor layer 1150, so care must be taken to avoid forming the light-emitting element 150 at and near the end of the semiconductor layer 1150.

[0156] like Figure 6 As shown, the ends of the semiconductor layer 1150 are formed in a manner that substantially coincides with the ends of the support substrate 1190. Therefore, the plurality of substrates 1195 are arranged in a manner that minimizes the creation of sharp points between adjacent substrates 1195, for example as... Figure 6 The semiconductor layer 1150 is arranged in a lattice pattern opposite to the substrate 102, as shown by the solid lines. Figure 6 As shown by the double-dotted line, it is attached to the first surface 103a of the substrate 102.

[0157] When multiple semiconductor layers 1150 are bonded to a single substrate 102, the substrate 102 with the multiple semiconductor layers 1150 bonded can be divided in a subsequent process to form an image display device with a number and size corresponding to the number of divisions. Since the ends of the semiconductor layers 1150 where the quality of the semiconductor crystal degrades are preferably the ends of the display area, the division units are preferably set in a manner consistent with the shape of the substrate 1195.

[0158] The processes up to the formation of the semiconductor growth substrate 1194 and the processing processes after the substrate 1195 is formed can be performed in the same factory or in different factories. For example, the substrate 1195 can be manufactured in a first factory and then transported to a second factory, which is different from the first factory, to perform a bonding process.

[0159] The method for bonding the semiconductor layer 1150 to the substrate 102 is not limited to the above, and can also be configured as follows: After forming the semiconductor layer 1150 on the crystal growth substrate 1001, it is placed in a container, for example, a support substrate 1190 is assembled inside the container for storage. After storage, the semiconductor layer 1150 is removed from the container and bonded to the substrate 102. Alternatively, the semiconductor layer 1150 is stored in a container without being assembled to the support substrate 1190. After storage, the semiconductor layer 1150 is removed from the container and directly bonded to the substrate 102.

[0160] Figures 7A to 8BThis is a schematic cross-sectional view illustrating a part of the manufacturing method of the image display device according to this embodiment.

[0161] like Figure 7A As shown, Figure 5B The metal layer 1163 shown is etched into a desired shape to form a light-shielding electrode 160a. Dry etching and wet etching are used in the formation of the light-shielding electrode 160a.

[0162] Will Figure 5B The semiconductor layer 1150 shown is etched into a desired shape to form a light-emitting element 150. A connection portion 151a is formed in the light-emitting element 150, and then other portions are formed by further etching. Thus, a light-emitting element 150 having a connection portion 151a protruding from the first surface 103a of the n-type semiconductor layer 151 in the positive X-axis direction can be formed. In the formation of the light-emitting element 150, a dry etching process is used, for example, and anisotropic plasma etching (RIE) is preferred.

[0163] A first interlayer insulating film (first insulating film) 156 is formed in such a way that it covers the first surface 103a, the light-emitting element 150 and the light-shielding electrode 160a.

[0164] like Figure 7B As shown, a TFT lower layer 106 is formed on the first interlayer insulating film 156, for example by CVD or the like. A Si layer 1104 is formed on the formed TFT lower layer 106. The Si layer 1104 is an amorphous Si layer during film formation, but after film formation, a polycrystalline Si layer 1104 is formed, for example by scanning multiple excimer laser pulses.

[0165] like Figure 8A As shown, Figure 7B The polycrystalline Si layer 1104 shown is processed into islands to form the TFT channel 104. An insulating layer 105 is formed to cover the TFT underlayer 106 and the TFT channel 104. The insulating layer 105 functions as a gate insulating film. A gate 107 is formed on the TFT channel 104, separated by the insulating layer 105. The gate 107 is selectively doped with boron. + Impurities are removed and thermally activated to form a transistor (circuit element) 103. Regions 104s and 104d are designated as p-type active regions, serving as the source and drain regions of transistor 103, respectively. Region 104i is designated as an n-type active region, serving as the channel.

[0166] When using the LTPS process, transistors 103 are formed at desired locations on the lower TFT film 106.

[0167] like Figure 8B As shown, a second interlayer insulating film (second insulating film) 108 is provided to cover the insulating layer 105 and the gate 107. In forming the second interlayer insulating film 108, a suitable fabrication method is applied depending on the material of the second interlayer insulating film 108. For example, when the second interlayer insulating film 108 is formed of SiO2, techniques such as ALD and CVD are used.

[0168] The flatness of the second interlayer insulating film 108 can be sufficient to form the first wiring layer 110, or a planarization process can be omitted. By not performing a planarization process on the second interlayer insulating film 108, the number of processes can be reduced. For example, if there are areas around the light-emitting element 150 where the thickness of the second interlayer insulating film 108 thins, the depth of the vias 161a and 161k can be shallow, thus ensuring a sufficient aperture. Consequently, electrical connections achieved through the vias are easily ensured, and a decrease in yield due to poor electrical characteristics can be suppressed.

[0169] Vias 161a and 161k are formed in a manner that penetrates the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the first interlayer insulating film 156. Via 161a (first via) is formed to reach the light-shielding electrode 160a. Via 161k (second via) is formed to reach the connecting portion 151a.

[0170] Vias 111s and 111d are formed in a manner that penetrates the second interlayer insulating film 108 and the insulating layer 105. Vias 111s is formed to reach region 104s. Vias 111d is formed to reach region 104d. In the formation of through holes 161a, 161k, 111s, and 111d, for example, a resonant interconnect (RIE) is used.

[0171] A first wiring layer 110 is formed on the second interlayer insulating film 108. Wirings 110k, 110d, and 110s are formed. Wiring 110k is connected to one end of via 161k. Wiring 110d is connected to one end of via 161a and one end of via 111d. Wiring 110s is connected to one end of via 111s. The first wiring layer 110 may also be formed simultaneously with the formation of vias 161k, 111d, and 111s.

[0172] In this way, sub-pixels 20 are formed, thus forming an image display device.

[0173] Figure 9 This is a schematic perspective view illustrating the image display device of this embodiment.

[0174] like Figure 9As shown, the image display device of this embodiment has a light-emitting circuit section 172 having a plurality of light-emitting elements 150 provided on a substrate 102. The light-emitting circuit section 172 includes, in addition to the light-emitting elements 150, a plurality of light-emitting elements 150. Figure 1 The diagram shows a structure of a light-shielding electrode 160a and a first interlayer insulating film 156 covering them. A driving circuit section 100 is provided on the light-emitting circuit section 172. The driving circuit section 100 includes... Figure 1 The circuit 101, the second interlayer insulating film, and the TFT lower layer film 106 are shown in the diagram. As described above, the light-emitting circuit section 172 and the driving circuit section 100 are electrically connected by vias 161a and 161k.

[0175] Figure 9 The structure shown is an example of an image display device according to the first embodiment, specifically an example without a color filter. It is applicable to other embodiments described later where a color filter is not provided.

[0176] The effects of the image display device 1 in this embodiment will be explained.

[0177] In the manufacturing method of the image display device 1 of this embodiment, after the semiconductor layer 1150 is bonded to the substrate 102, the semiconductor layer 1150 is etched to form a light-emitting element 150. Then, the light-emitting element 150 is covered with a first interlayer insulating film 156, and a circuit 101 including circuit elements such as a transistor 103 driving the light-emitting element 150 is fabricated on the first interlayer insulating film 156. Therefore, compared to separately transferring a monolithic light-emitting element to the substrate 102, the manufacturing process is significantly shortened.

[0178] For example, in a 4K image display device, the number of subpixels exceeds 24 million, and in an 8K image display device, the number of subpixels exceeds 99 million. If such a large number of light-emitting elements were individually formed and mounted onto a circuit board, it would require a considerable amount of time. Therefore, it is difficult to realize an image display device based on micro-LEDs at a realistic cost. Furthermore, if a large number of light-emitting elements are individually mounted, a decrease in yield due to poor connection during mounting is unavoidable, leading to further cost increases. However, in the manufacturing method of the image display device of this embodiment, the following effects are achieved.

[0179] As described above, in the manufacturing method of the image display device 1 of this embodiment, since the light-emitting element is formed by etching after the semiconductor layer 1150 is entirely bonded to the substrate 102, the transfer process is completed in one step. Therefore, in the manufacturing method of the image display device 1 of this embodiment, the time of the transfer process can be shortened and the number of processes can be reduced compared to conventional manufacturing methods.

[0180] Furthermore, the semiconductor layer 1150 is not pre-monolithized or electrodes are formed at positions corresponding to circuit elements; instead, it is laminated to the substrate 102 at the wafer level. Therefore, alignment during the lamination stage is unnecessary. Consequently, the lamination process can be easily performed in a short time. Since alignment is not required during lamination, miniaturization of the light-emitting element 150 is also easy, making it suitable for high-resolution displays.

[0181] In this embodiment, for example, a glass substrate formed as described above can be covered with a first interlayer insulating film 156, and driving circuits, scanning circuits, etc., including TFTs can be formed on the planarized surface using LTPS processes or the like. Therefore, there is the advantage of being able to utilize existing flat panel display manufacturing processes and factories.

[0182] In this embodiment, the light-emitting element 150, formed on a layer lower than transistor 103, can be electrically connected to power lines, ground lines, driving transistors, etc., formed on the upper layer through vias 161a and 161k that penetrate the first interlayer insulating film 156, the lower TFT film 106, the insulating layer 105, and the second interlayer insulating film 108. By using this technically established multilayer wiring technique, a uniform connection structure can be easily achieved, and the yield can be improved. Therefore, the decrease in yield caused by poor connection of the light-emitting element, etc., is suppressed.

[0183] In the image display device 1 of this embodiment, a transistor 103 is formed above the light-emitting element 150, but a light-shielding electrode 160a is formed throughout the upper surface 153U of the light-emitting element 150. Therefore, the light-shielding electrode 160a suppresses upward scattered light emitted from the light-emitting element 150 from reaching the transistor 103. Thus, malfunction of the transistor 103 can be prevented.

[0184] By appropriately selecting a conductive material, the light-shielding electrode 160a can be made to have high light reflectivity. Because the light-shielding electrode 160a has light reflectivity, upwardly scattered light can be reflected isotropically toward the light-emitting surface 151S, thereby substantially improving the luminous efficiency.

[0185] (Second Implementation)

[0186] Figure 10 This is a schematic cross-sectional view illustrating a portion of the image display device involved in this embodiment.

[0187] like Figure 10As shown, the image display device of this embodiment includes a sub-pixel 220, which differs from the other embodiments in that the sub-pixel 220 provides a light-emitting surface 253S on the p-type semiconductor layer 253. In this embodiment, the structure of the light-emitting element 250 differs from the other embodiments, and the structure of the transistor 203 driving the light-emitting element 250 also differs. For components that are the same as in other embodiments, the same reference numerals are used, and detailed descriptions are omitted where appropriate.

[0188] The sub-pixel 220 of the image display device in this embodiment includes a substrate 102, a light-emitting element 250, a light-shielding electrode 260k, a first interlayer insulating film 156, a transistor 203, a second interlayer insulating film 108, a via 261k, and a first wiring layer 110.

[0189] A light-emitting element 250 is disposed on a first surface 103a. The light-emitting element 250 includes a light-emitting surface 253S disposed on the first surface 103a. The light-emitting surface 253S is in contact with the first surface 103a. The light-emitting element 250 includes an upper surface 251U disposed on the opposite side of the light-emitting surface 253S. Similar to the other embodiments described above, the light-emitting element 250 is a prismatic or cylindrical element.

[0190] The light-emitting element 250 includes a p-type semiconductor layer 253, a light-emitting layer 252, and an n-type semiconductor layer 251. The p-type semiconductor layer 253, the light-emitting layer 252, and the n-type semiconductor layer 251 are stacked sequentially from the light-emitting surface 253S toward the upper surface 251U. In this embodiment, the light-emitting surface 253S is provided by the p-type semiconductor layer 253.

[0191] The light-emitting element 250 includes a connecting portion 253a. The connecting portion 253a is provided such that it protrudes in one direction from the p-type semiconductor layer 253 on the first surface 103a. The height of the connecting portion 253a from the first surface 103a is the same as or lower than the height of the p-type semiconductor layer 253 from the first surface 103a. The connecting portion 253a is p-type and electrically connected to the p-type semiconductor layer 253. The connecting portion 253a is connected to one end of a via 261a, electrically connecting the p-type semiconductor layer 253 to the via 261a.

[0192] The light-emitting element 250 has the same shape viewed in the XY plane as the light-emitting element 150 in the other embodiments described above. A suitable shape is selected based on the layout of the circuit elements, etc.

[0193] The light-emitting element 250 is the same light-emitting diode as the light-emitting element 150 in the other embodiments described above. That is, the wavelength of the light emitted by the light-emitting element 250 is, for example, blue light emission of about 467nm ± 30nm or blue-violet light emission of about 410nm ± 30nm. The wavelength of the light emitted by the light-emitting element 250 is not limited to the above values ​​and can be set to suitable values.

[0194] Transistor 203 is disposed on the lower TFT film 106. Transistor 203 is an n-channel TFT. Transistor 203 includes a TFT channel 204 and a gate 107. Preferably, transistor 203 is formed by LTPS process or the like, similar to the other embodiments described above. In this embodiment, circuit 101 includes TFT channel 204, insulating layer 105, second interlayer insulating film 108, vias 111s and 111d, and first wiring layer 110.

[0195] The TFT channel 204 includes regions 204s, 204i, and 204d. Regions 204s, 204i, and 204d are disposed on the lower TFT film 106. Regions 204s and 204d are doped with phosphorus ions (P). - Type n impurities, etc. Region 204s is ohmically connected to via 111s. Region 204d is ohmically connected to via 111d.

[0196] The gate 107 is disposed on the TFT channel 204 through the insulating layer 105. The insulating layer 105 insulates the TFT channel 204 and the gate 107.

[0197] In transistor 203, if a voltage higher than that in region 204s is applied to the gate 107, a channel is formed in region 204i. The current flowing between regions 204s and 204d is controlled by the voltage in region 204s relative to the gate 107. The TFT channel 204 and the gate 107 are formed using the same materials and manufacturing methods as those used in the other embodiments described above.

[0198] The first wiring layer 110 includes wirings 210s, 210d, and 210a. A portion of wiring 210a (the second wiring) is disposed above the connection portion 253a. Other portions of wiring 210a are connected, for example, to [the following description is missing]. Figure 11 The power cord shown is 3.

[0199] Vias 111s and 111d are provided in a manner that penetrates the second interlayer insulating film 108. Via 111s is provided between wiring 110s and region 204s. Via 111s electrically connects wiring 110s and region 204s. Via 111d is provided between wiring 110d and region 204d. Via 111d electrically connects wiring 110d and region 204d. Vias 111s and 111d are formed using the same materials and manufacturing methods as in the other embodiments described above.

[0200] The via 261k is provided in a manner that penetrates the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the first interlayer insulating film 156. The via 261k is disposed between the wiring 210d and the light-shielding electrode 260k, electrically connecting the wiring 210d and the light-shielding electrode 260k. Therefore, the n-type semiconductor layer 251 is electrically connected to the drain region of the transistor 203 via the light-shielding electrode 260k, the via 261k, the wiring 210d, and the via 111d.

[0201] The via 261a is provided in a manner that penetrates the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the first interlayer insulating film 156. The via 261a is disposed between the wiring 210a and the connection portion 253a, electrically connecting the wiring 210a and the connection portion 253a. Therefore, the p-type semiconductor layer 253 is connected, for example, to the connection portion 253a, the via 261a, and the wiring 210a. Figure 11 The power supply line 3 of the circuit is electrically connected.

[0202] Figure 11 This is a schematic block diagram illustrating the image display device according to this embodiment.

[0203] like Figure 11 As shown, the image display device 201 of this embodiment includes a display area 2, a row selection circuit 205, and a signal voltage output circuit 207. In the display area 2, similar to the other embodiments described above, for example, the sub-pixels 220 are arranged in a grid pattern on the XY plane.

[0204] Sub-pixel 220 includes a light-emitting element 222, a selection transistor 224, a driving transistor 226, and a capacitor 228. Figure 11 In this context, sometimes the select transistor 224 is denoted as T1, the drive transistor 226 is denoted as T2, and the capacitor 228 is denoted as Cm.

[0205] In this embodiment, the light-emitting element 222 is disposed on the power line 3 side, and the driving transistor 226, which is connected in series with the light-emitting element 222, is disposed on the ground line 4 side. That is, the driving transistor 226 is connected to a lower potential side than the light-emitting element 222. The driving transistor 226 is an n-channel transistor.

[0206] A select transistor 224 is connected between the gate electrode of the drive transistor 226 and the signal line 208. A capacitor 228 is connected between the gate electrode of the drive transistor 226 and the ground line 4.

[0207] The row selection circuit 205 and the signal voltage output circuit 207 supply a signal voltage of a different polarity than that described in the other embodiments to the signal line 208 in order to drive the driving transistor 226, which is an n-channel transistor.

[0208] In this embodiment, since the driving transistor 226 is n-channel, the polarity of the signal voltage differs from that in the other embodiments described above. Specifically, the row selection circuit 205 supplies a selection signal to the scan line 206 in a manner that sequentially selects one row from the arrangement of m rows of sub-pixels 220. The signal voltage output circuit 207 supplies a signal voltage with the desired analog voltage value to each sub-pixel 220 of the selected row. The driving transistor 226 of the sub-pixel 220 of the selected row causes a current corresponding to the signal voltage to flow into the light-emitting element 222. The light-emitting element 222 emits light with a brightness corresponding to the current flowing into it.

[0209] The manufacturing method of the image display device according to this embodiment will be described.

[0210] Figures 12A-13 This is a schematic cross-sectional view illustrating a part of the manufacturing method of the image display device according to this embodiment.

[0211] like Figure 12A As shown, in the manufacturing method of the image display device of this embodiment, a semiconductor growth substrate 1194 is prepared. Although with Figure 4A As has been described in connection, but in this embodiment, the semiconductor growth substrate 1194 does not form a metal layer on the semiconductor layer 1150.

[0212] Next, as Figure 12B As shown, the semiconductor layer 1150 of the semiconductor growth substrate 1194 is bonded to the substrate 102. In this bonding process, the exposed surface 1153E of the p-type semiconductor layer 1153 is bonded to the first surface 103a.

[0213] Then, the crystal growth substrate 1001 is removed from the semiconductor growth substrate 1194, such as... Figure 13 As shown, a metal layer (second metal layer) 1164 is formed on the semiconductor layer 1150 attached to the first surface 103a. The metal layer 1164 is formed on the exposed surface 1151E of the n-type semiconductor layer 1151. The metal layer 1164 can be made of the same material as the metal layers 1161 and 1162 in the other embodiments described above.

[0214] Figures 14A to 15B This is a schematic cross-sectional view illustrating a part of the manufacturing method of the image display device according to this embodiment.

[0215] exist Figures 14A to 15B In the process shown, with Figures 12A-13 The processes shown are different. After the semiconductor layer 1150 is transferred to the support substrate 1190, it is bonded to the substrate 102. The metal layers 1161 and 1162 are formed before the semiconductor layer 1150 is bonded to the substrate 102.

[0216] like Figure 14A As shown, a semiconductor growth substrate 1294 is prepared. The semiconductor growth substrate 1294 has a... Figure 4A , Figure 12A The semiconductor growth substrate 1194 shown has different structures. In the semiconductor growth substrate 1294, the semiconductor layer 1150 is stacked from the crystal growth substrate 1001 side in the order of p-type semiconductor layer 1153, light-emitting layer 1152, and n-type semiconductor layer 1151. The metal layer 1161 is formed on the exposed surface 1151E of the n-type semiconductor layer 1151.

[0217] Next, as Figure 14B As shown, a support substrate 1190 is prepared. A metal layer 1162 is formed on one side 1190E of the support substrate 1190. A semiconductor layer 1150 is bonded to the support substrate 1190 via the metal layers 1161 and 1162.

[0218] Afterwards, remove the crystal growth substrate 1001, such as Figure 15A As shown, substrate 1295 is bonded to substrate 102. Semiconductor layer 1150 is bonded to substrate 1190 via metal layer 1163 on substrate 1295. The bonding surface with first surface 103a is the exposed surface 1153E of p-type semiconductor layer 1153.

[0219] like Figure 15B As shown, the support substrate 1190 is removed. The removal of the support substrate 1190 is performed using wet etching and laser lift-off, as in the other embodiments described above. This allows the p-type semiconductor layer 1153 to be bonded to the substrate 102.

[0220] Figures 16A-17B This is a schematic cross-sectional view illustrating a part of the manufacturing method of the image display device according to this embodiment.

[0221] like Figure 16A As shown, Figure 13 and Figure 15B The metal layers 1163 and 1164 shown are etched into the desired shape to form the light-shielding electrode 260k.

[0222] Will Figure 13 and Figure 15B The semiconductor layer 1150 shown is processed into a desired shape to form a light-emitting element 250. In the formation of the light-emitting element 250, as in the other embodiments described above, a connecting portion 253a is formed, and other portions are formed.

[0223] In the formation of the light-shielding electrode 260k and the light-emitting element 250, the same etching process as in the other embodiments described above is used.

[0224] A first interlayer insulating film 156 is formed in such a way that it covers the first surface 103a, the light-emitting element 250 and the light-shielding electrode 260k.

[0225] like Figure 16B As shown, a TFT lower layer 106 is formed on the first interlayer insulating film 156. An amorphous Si layer is formed on the TFT lower layer 106, and a polycrystalline Si layer 1104 is formed by laser annealing using an excimer laser or the like.

[0226] like Figure 17A As shown, Figure 16B The polycrystalline Si layer 1104 shown is as follows Figure 3 The transistor 103 shown is fabricated in an island shape to form a TFT channel 204. An insulating layer 105 is formed to cover the TFT underlayer 106 and the TFT channel 204. A gate 107 is formed on the TFT channel 204, separated by the insulating layer 105. The gate 107 is selectively doped with P. - Impurities are removed and thermally activated to form transistor 203. Regions 204s and 204d are designated as n-type active regions, functioning as the source and drain regions of transistor 203, respectively. Region 204i is designated as a p-type active region, functioning as the channel.

[0227] like Figure 17B As shown, a second interlayer insulating film 108 is provided to cover the insulating layer 105 and the gate 107. Vias 261k and 261a are formed to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer 106, and the first interlayer insulating film 156. Via 261k is formed to reach the light-shielding electrode 260k. Via 261a is formed to reach the connection portion 253a.

[0228] Guide holes 111s and 111d are formed in a manner that penetrates the second interlayer insulating film 108 and the insulating layer 105. Guide hole 111s is formed in a manner that reaches region 204s. Guide hole 111d is formed in a manner that reaches region 204d.

[0229] A first wiring layer 110 is formed on the second interlayer insulating film 108. Wirings 210a, 210d, and 210s are formed. Wiring 210a is connected to one end of via 261a. Wiring 210d is connected to one end of via 261k and one end of via 111d. Wiring 210s is connected to one end of via 111s. The first wiring layer 110 may also be formed simultaneously with the formation of vias 261a, 261k, 111d, and 111s.

[0230] In this way, sub-pixels 220 are formed, forming an image display device 201.

[0231] The effects of the image display device in this embodiment will be explained.

[0232] In the image display device of this embodiment, similar to the other embodiments described above, the time for the transfer process used to form the light-emitting element 250 can be shortened and the number of processes can be reduced. Furthermore, in the crystal growth process of the semiconductor layer 1150, when the crystal is grown from the n-type semiconductor layer 1151, the transfer to the support substrate 1190 is not required, thus reducing the number of processes.

[0233] In the image display device 201 of this embodiment, the p-type semiconductor layer 253 can be set as the light-emitting surface 253S, thus increasing the degree of freedom in the circuit structure and improving the design efficiency of the product.

[0234] (Third Implementation)

[0235] Figure 18 This is a schematic cross-sectional view illustrating a portion of the image display device involved in this embodiment.

[0236] In this embodiment, the light-emitting element 150, whose light-emitting surface 151 is set as the light-emitting surface 151S1, is driven by an n-type transistor 203. In this embodiment, a light-shielding layer 330 is included. In this embodiment, a color filter 180 is mounted on the light-emitting surface 151S1 side. For components that are the same as in the other embodiments described above, the same reference numerals are used, and detailed descriptions are omitted where appropriate.

[0237] like Figure 18 As shown, the sub-pixel 320 of the image display device in this embodiment includes a color filter 180, a light-emitting element 150, a light-shielding electrode 160a, a first interlayer insulating film 156, a transistor 203, a second interlayer insulating film 108, a light-shielding layer 330, a via 361a, and a first wiring layer 110. The transistor 203 is an n-channel TFT. The light-emitting element 150 provides a light-emitting surface 151S1 implemented by an n-type semiconductor layer 151. In this embodiment, the light-emitting surface 151S1 is roughened.

[0238] The color filter 180 includes a light-blocking section 181 and a color conversion section 182. Thus, the color filter (transparent component) 180 is a light-transmitting component because it includes the light-transmitting color conversion section 182. The color conversion section 182 is positioned directly below the light-emitting surface 151S1 of the light-emitting element 150, according to the shape of the light-emitting surface 151S1. In the color filter 180, the portion other than the color conversion section 182 constitutes the light-blocking section 181. The light-blocking section 181 is a so-called black matrix, capable of reducing color bleeding caused by color mixing from adjacent color conversion sections 182, thereby displaying a sharp image.

[0239] The color conversion unit 182 is configured with one or two or more layers. Figure 18 The diagram shows a case where the color conversion unit 182 has two layers. Whether the color conversion unit 182 has one or two layers is determined by the color, i.e., the wavelength, of the light emitted by the sub-pixel 320. When the emitted color of the sub-pixel 320 is red, it is preferable that the color conversion unit 182 consists of two layers: a color conversion layer 183 and a color filter layer 184 that allows red light to pass through. When the emitted color of the sub-pixel 320 is green, it is preferable that the color conversion unit 182 consists of two layers: a color conversion layer 183 and a color filter layer 184 that allows green light to pass through. When the emitted color of the sub-pixel 320 is blue, it is preferable to have only one layer.

[0240] In the case where the color conversion unit 182 has two layers, the first layer is the color conversion layer 183, and the second layer is the color filter layer 184. The first color conversion layer 183 is located closer to the light-emitting element 150. The color filter layer 184 is stacked on top of the color conversion layer 183.

[0241] The color conversion layer 183 converts the wavelength of light emitted by the light-emitting element 150 to a desired wavelength. In the case of a sub-pixel 320 emitting red light, the wavelength of light emitted by the light-emitting element 150, i.e., 467nm ± 30nm, is converted to light with a wavelength of approximately 630nm ± 20nm. In the case of a sub-pixel 320 emitting green light, the wavelength of light emitted by the light-emitting element 150, i.e., 467nm ± 30nm, is converted to light with a wavelength of approximately 532nm ± 20nm.

[0242] The color filter layer 184 cuts off the wavelength components of blue light that remain after being color converted by the color conversion layer 183.

[0243] When the light emitted by sub-pixel 320 is blue, sub-pixel 320 can output light via color conversion layer 183 or directly output light without color conversion layer 183. When the wavelength of the light emitted by light-emitting element 150 is approximately 467nm ± 30nm, sub-pixel 320 can also output light without color conversion layer 183. When the wavelength of the light emitted by light-emitting element 150 is set to 410nm ± 30nm, in order to convert the wavelength of the output light to approximately 467nm ± 30nm, it is preferable to provide one color conversion layer 183.

[0244] Even in the case of the blue sub-pixel 320, the sub-pixel 320 can have a color filter layer 184. By providing a color filter layer 184 through which blue light passes through the blue sub-pixel 320, the minute external light reflection other than blue light generated on the surface of the light-emitting element 150 is suppressed.

[0245] The color filter 180 has a first surface 180a. A transparent film adhesive layer 188 is provided on the first surface 180a. The light-emitting element 150 and the first interlayer insulating film 156 are disposed on the first surface 180a through the transparent film adhesive layer 188.

[0246] In the light-emitting element 150, the light-emitting surface 151S1 is roughened. A transparent planarization film 155 is provided between the light-emitting surface 151S1 and the transparent film adhesive layer 188. The transparent planarization film 155 planarizes the roughened light-emitting surface 151S1.

[0247] The light-emitting element 150 is a prism-shaped or cylindrical element including a light-emitting surface 151S1 and an upper surface 153U. The light-emitting surface 151S1 is in contact with the transparent thin film adhesive layer 188 via a transparent planarization film 155. The upper surface 153U is a surface disposed on the opposite side of the light-emitting surface 151S1.

[0248] The light-emitting element 150 includes an n-type semiconductor layer 151, a light-emitting layer 152, and a p-type semiconductor layer 153. The n-type semiconductor layer 151, the light-emitting layer 152, and the p-type semiconductor layer 153 are stacked sequentially from the light-emitting surface 151S1 toward the upper surface 153U.

[0249] The light-emitting element 150 includes a connecting portion 151a. The connecting portion 151a is formed protruding in one direction from the n-type semiconductor layer 151 on the first surface 180a, separated by a transparent thin-film adhesive layer 188. A transparent planarization film 155 is also disposed between the connecting portion 151a and the transparent thin-film adhesive layer 188. The connecting portion 151a is an n-type semiconductor layer and is connected to the n-type semiconductor layer 151. The connecting portion 151a is the same as in the other embodiments described above in that it is connected to one end of the via 361k and has the function of connecting the n-type semiconductor layer 151 to the first wiring layer 110, which is located above the light-emitting element 150, via the via 361k. The structure of the light-emitting element 150 is the same as in the first embodiment described above, except that the light-emitting surface 151S1 is roughened; therefore, further detailed description is omitted.

[0250] A light-shielding electrode 160a is provided all over the upper surface 153U. The light-shielding electrode 160a is provided between the upper surface 153U and one end of the guide hole 361a. The light-shielding electrode 160a has the same function as in the first embodiment described above in blocking scattered light toward the upper surface 153U side of the light-emitting element 150, and further detailed description is omitted.

[0251] In this embodiment, an n-channel transistor 203 is formed on the lower TFT film 106. The transistor 203 is a TFT, and its structure is the same as in the second embodiment described above, so detailed description is omitted.

[0252] In this embodiment, a light-shielding layer 330 is disposed between the first interlayer insulating film 156 and the second interlayer insulating film 108. In this example, the light-shielding layer 330 is disposed over the entire surface except for a portion on the first interlayer insulating film 156. The light-shielding layer 330 can be made of any light-shielding material, regardless of its conductivity, but it can be formed, for example, from a light-reflective metallic material. The light-shielding layer 330 can also be formed using black resin. When the light-shielding layer 330 is formed using black resin, it is possible to form a through hole with a diameter larger than the via beforehand, and to form the via together with the first interlayer insulating film 156, etc., without having to pre-form a through hole.

[0253] The guide holes 361a and 361k are arranged to penetrate the first interlayer insulating film 156 and the second interlayer insulating film 108. Therefore, the light-shielding layer 330 has through holes 331a and 331k with diameters larger than those of the guide holes 361a and 361k. The guide hole 361a penetrates the through hole 331a, and the guide hole 361k penetrates the through hole 331k.

[0254] The light-shielding layer 330 includes a first portion 330a, on which the TFT channel 204 is disposed. The first portion 330a has a region that includes the outer periphery of the TFT channel 204 when projected onto the first portion 330a in an XY plane view. Through the first portion 330a, even when upward scattered light or the like is emitted from the light-emitting element 150 disposed below the TFT channel 204, the scattered light or the like is blocked by the first portion 330a, and the scattered light or the like can hardly reach the TFT channel, thus suppressing malfunction of the transistor 203.

[0255] It is preferable from the viewpoint of light-shielding that the light-shielding layer 330, as in this example, covers the entire surface of the first interlayer insulating film 156. However, the light-shielding layer 330 is not limited to being a single physical component. For example, the light-shielding layer 330 may also be separately disposed on the lower portion of the TFT channel 204 and the upper portion of the light-emitting element 150. In this example, the light-shielding layer 330 is not connected to any potential, but it may be connected to a specific potential such as ground potential or power supply potential. When the light-shielding layer 330 has multiple separate portions, they may all be set to a common potential, or each portion may be connected to a different potential.

[0256] A via 111s is disposed between wiring 310s and area 204s, electrically connecting wiring 310s and area 204s. A via 111d is disposed between wiring 310d and area 204d, electrically connecting wiring 310d and area 204d.

[0257] Wiring 310s is connected to region 204s via via 111s. Region 204s is the source region of transistor 203. Therefore, the source region of transistor 203 is electrically connected to ground wire 4 via via 111s and wiring 310s.

[0258] Wiring 310d is connected to region 204d via via 111d. Region 204d is the drain region of transistor 203.

[0259] The via 361k is provided in a manner that penetrates the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the first interlayer insulating film 156. The via 361k is provided between the wiring 310d and the connection portion 151a, electrically connecting the wiring 310d and the connection portion 151a. Therefore, the drain region of the transistor 203 is electrically connected to the n-type semiconductor layer 151 via the via 111d, the wiring 310d, the via 361k, and the connection portion 151a.

[0260] The via 361a is provided in a manner that penetrates the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the first interlayer insulating film 156. The via 361a is disposed between the wiring 310a and the light-shielding electrode 160a, electrically connecting the wiring 310a and the light-shielding electrode 160a. Therefore, the p-type semiconductor layer 153 is electrically connected to the power line 3 via the light-shielding electrode 160a, the via 361a, and the wiring 310a.

[0261] Figure 19 This is a schematic block diagram illustrating the image display device of this embodiment.

[0262] like Figure 19 As shown, in the image display device 301 of this embodiment, sub-pixels 320 are arranged in the display area 2. The sub-pixels 320 are arranged in a grid pattern, for example. For example, n sub-pixels 320 are arranged along the X-axis and m sub-pixels are arranged along the Y-axis.

[0263] Pixel 10 comprises multiple sub-pixels 320 that emit different colors of light. Sub-pixel 320R emits red light. Sub-pixel 320G emits green light. Sub-pixel 320B emits blue light. The emission color and luminance of one pixel 10 are determined by the three sub-pixels 320R, 320G, and 320B emitting light at the desired luminance.

[0264] One pixel 10 comprises three subpixels 320R, 320G, and 320B, which are arranged in a straight line, for example, on the X-axis. Regarding each pixel 10, subpixels of the same color can be arranged in the same column, or, as in this example, subpixels of different colors can be arranged for each column.

[0265] In the image display device 301 of this embodiment, the structures of the power line 3, ground line 4, scan line 206, and signal line 208 are the same as in the second embodiment described above. However, the image display device 301 differs from the second embodiment in that the emission color and brightness of one pixel 10 are determined by causing the three sub-pixels to emit light at a set brightness. Aside from possible differences in the structure of the signals used for this purpose, the structure differs from the second embodiment. Figure 11 The examples are the same, so a detailed description of the circuit structure is omitted.

[0266] The manufacturing method of the image display device according to this embodiment will be described.

[0267] Figures 20A to 23B This is a schematic cross-sectional view illustrating a part of the manufacturing method of the image display device according to this embodiment.

[0268] In the manufacturing method of the image display device of this embodiment, preparation is made until the semiconductor layer is transferred to the support substrate. Figure 5A The processes up to substrate 1195 shown are the same as in the first embodiment described above. Hereinafter, from the point where substrate 1195 is formed... Figure 4B The next step will be explained.

[0269] like Figure 20A As shown, will remove Figure 4B The exposed n-type semiconductor layer 1151 on the crystal growth substrate 1001 shown is roughened to form a roughened exposed surface 1151E1. A transparent planarization film 1155 is formed throughout the roughened exposed surface 1151E1, and the exposed surface 1155E of the transparent planarization film 1155 is planarized. In the planarization of the exposed surface 1155E, CMP is used, for example.

[0270] like Figure 20B As shown, the semiconductor layer 1150 is bonded to the substrate 102. Regarding the bonding surfaces, in the semiconductor layer 1150, it is the exposed surface 1155E of the transparent planarization film 1155, and in the substrate 102, it is the first surface 103a of the bonding layer 303.

[0271] The above describes the process of "forming a metal layer on at least one of the semiconductor layer 1150 and the support substrate 1190, transferring the semiconductor layer 1150 onto the support substrate 1190 via the metal layer, and then bonding the semiconductor layer 1150 to the substrate 102". As used in the second embodiment... Figures 12A-13 As explained, it is also possible to form a metal layer on the semiconductor layer 1150 without transferring the semiconductor layer 1150 to the support substrate 1190, and instead attach the semiconductor layer 1150 to the substrate 102.

[0272] like Figure 21A As shown, Figure 20B The metal layer 1163 and semiconductor layer 1150 are etched into the desired shape to form a light-shielding electrode 160a and a light-emitting element 150. The formation process of the light-shielding electrode 160a and the light-emitting element 150 is the same as in the other embodiments described above. This is achieved by processing the light-emitting element 150 simultaneously with the formation of the semiconductor layer 1163. Figure 20B The transparent planarization film 1155 shown is formed before processing.

[0273] A first interlayer insulating film 156 is formed in such a way that it covers the first surface 103a, the light-emitting element 150, and the light-shielding electrode 160a. When the transparent planarization film 155 is exposed on the side of the light-emitting element 150, the first interlayer insulating film 156 is also provided to cover the transparent planarization film 155.

[0274] A light-shielding layer 330 is formed on the first interlayer insulating film 156. During the formation process of the light-shielding layer 330, through-holes 331a and 331k are formed by etching or the like. The portion of the light-shielding layer 330 other than the through-holes 331a and 331k remains on the first interlayer insulating film 156, and the first portion 330a is provided at the location where the transistor is formed in subsequent processes. If the light-shielding layer 330 is made of an insulating material such as black resin, insulation between the light-shielding layer 330 and the vias is not required, so the formation of through-holes 331a and 331k is unnecessary.

[0275] like Figure 21B As shown, a TFT lower layer film 106 is formed on the light-shielding layer 330 by CVD or the like. The portions where through holes 331a and 331k are formed are embedded in the TFT lower layer film 106, and the surface of the TFT lower layer film 106 is planarized. A polycrystalline Si layer 1104 is formed on the planarized TFT lower layer film 106.

[0276] like Figure 22A As shown, processing Figure 21B The Si layer 1104 shown forms a TFT channel 204, an insulating layer 105, a gate 107, and regions 204s, 204d, and 204i of the TFT channel 204. These manufacturing processes are the same as in the second embodiment described above. Preferably, an LTPS process is used.

[0277] like Figure 22B As shown, vias 111s, 111d, 361k, and 361a are formed to form the first wiring layer 110. These manufacturing processes are the same as those in the second embodiment described above.

[0278] like Figure 23A As shown, an adhesive layer 1170 is formed on the second interlayer insulating film 108 and the first wiring layer 110, and a reinforcing substrate 1180 is bonded to the adhesive layer 1170. Then, Figure 22B The substrate 102 and the bonding layer 303 are removed together to expose the formation surface 1192A of the color filter 180. The removal of the substrate 102 and the bonding layer 303 is carried out using wet etching and laser stripping.

[0279] like Figure 23B As shown, the color filter (wavelength conversion component) 180 is bonded to the forming surface 1192A via a transparent thin film adhesive layer 188.

[0280] The purpose of removing the substrate 102 and the bonding layer 303 is to reduce the transmission loss of emitted light from the light-emitting surface 151S1. Therefore, when removing the substrate 102 and the bonding layer 303, it is not limited to removing them completely; for example, a portion of the substrate 102 may be removed to form a color filter 180. Removing a portion of the substrate 102 involves thinning the substrate 102 by etching or the like.

[0281] Figures 24A-24D This is a schematic cross-sectional view illustrating a part of the manufacturing method of the image display device according to this embodiment.

[0282] exist Figures 24A-24D The image shows a method for forming color filters using inkjet printing. This manufacturing process replaces the above-described method. Figure 23B The process shown is applied.

[0283] like Figure 24A As shown, the substrate 102 and the bonding layer 303 are removed, exposing the structure 1192 with the forming surface 1192A. (As shown in...) Figure 23A As described, the structure 1192 includes a light-emitting element 150, a first interlayer insulating film 156, a light-shielding layer 330, a TFT lower layer film 106, a TFT channel 204, an insulating layer 105, a gate 107, vias 111s, 111d, 361k, 361a and a first wiring layer 110.

[0284] like Figure 24B As shown, a light-shielding portion 181 is formed on the forming surface 1192A of the color filter, excluding the light-emitting surface 151S1. The light-shielding portion 181 is formed, for example, using screen printing, photolithography, or other techniques.

[0285] like Figure 24C As shown, a phosphor corresponding to the emitted color is ejected from the inkjet nozzle to form a color conversion layer 183. The phosphor colors the area on the color filter formation surface 1192A where the light-shielding portion 181 is not formed. The phosphor uses a fluorescent coating material, such as a general phosphor material, a perovskite phosphor material, or a quantum dot phosphor material. Using perovskite phosphor materials or quantum dot phosphor materials allows for the realization of various emitted colors and provides high monochromaticity, thus improving color reproducibility, and is therefore preferred. After the inkjet nozzle is used for painting, a drying process is performed at a suitable temperature and time. The thickness of the coating film during coloring is set to be thinner than the thickness of the light-shielding portion 181.

[0286] As already explained, for the blue emitting subpixel, the color conversion layer 183 is not formed if a color conversion section is not formed. Furthermore, when a blue color conversion layer is formed for the blue emitting subpixel, and the color conversion section can be a single layer, it is preferable that the thickness of the blue phosphor coating is the same as the thickness of the color filter layer 184 stacked on the color conversion layer 183, and is set to the same thickness as the light-shielding section 181.

[0287] like Figure 24D As shown, the paint for the color filter layer 184 is ejected from the inkjet nozzle. The paint is applied in an overlapping manner to the phosphor coating. The combined thickness of the phosphor and the paint coating is set to be the same as the thickness of the light-shielding portion 181.

[0288] Whether it's a film-type color filter or an inkjet-type color filter, to improve color conversion efficiency, it's desirable for the color conversion layer 183 to be as thick as possible. On the other hand, if the color conversion layer 183 is too thick, the emitted light after color conversion will approximate a Lambertian angle, while the blue light that is not color-converted will have its emission angle limited by the light-shielding portion 181. This will result in a viewing angle dependency problem in the displayed color of the image. To ensure that the light distribution of the sub-pixels where the color conversion layer 183 is located is consistent with the light distribution of the blue light that is not color-converted, the thickness of the color conversion layer 183 is preferably set to approximately half the opening size of the light-shielding portion 181.

[0289] For example, in the case of a high-resolution image display device with a pixel density of around 250 ppi, the spacing between sub-pixels 20 is approximately 30 μm, therefore the thickness of the color conversion layer 183 is preferably around 15 μm. Here, when the color conversion material is composed of spherical phosphor particles, in order to suppress light leakage from the light-emitting element 150, it is preferable to stack them in the densest possible configuration. For this purpose, at least three layers of particles are required. Therefore, the particle size of the phosphor material constituting the color conversion layer 183 is preferably, for example, around 5 μm or less, and more preferably around 3 μm or less.

[0290] Figure 25 This is a schematic perspective view illustrating the image display device of this embodiment.

[0291] like Figure 25 As shown, the image display device of this embodiment has a light-emitting circuit section 172 having a plurality of light-emitting elements 150 provided on the color filter 180. A driving circuit section 100 is provided on the light-emitting circuit section 172. The driving circuit section 100 includes... Figure 18 The circuit 101 shown has the following structure. As described above, the light-emitting circuit section 172 and the driving circuit section 100 are electrically connected by vias 361a and 361k.

[0292] In this embodiment, a color filter 180 is provided to enable the formation of a full-color image display device 301. However, similar to the other embodiments described above, the image display device may be formed without a color filter. In this case, for example, the substrate 102 and the bonding layer 303 may not be removed and may remain intact.

[0293] The effects of the image display device 301 in this embodiment will be explained.

[0294] In the manufacturing method of the image display device 301 in this embodiment, in addition to the effect of shortening the time of the transfer process for forming the light-emitting element 150 and reducing the number of processes, just like in the other embodiments described above, since the light-emitting surface 151S1 is made of an n-type semiconductor layer 151 with a lower resistance than the p-type, the n-type semiconductor layer 151 can be formed thick, and the light-emitting surface 151S1 can be sufficiently roughened.

[0295] In the image display device 301 of this embodiment, by roughening the light-emitting surface 151S1, the emitted light is diffused. Therefore, even a small light-emitting element 150 can be used as a light source with a sufficient light-emitting area.

[0296] In the image display device 301 of this embodiment, an n-channel transistor 203 can be used to drive a light-emitting element 150 whose light-emitting surface 151S1 is an n-type semiconductor layer 151. Therefore, the degree of freedom of circuit structure is increased, and design efficiency can be improved.

[0297] In the image display device 301 of this embodiment, a light-shielding layer 330 is disposed between the first interlayer insulating film 156 and the second interlayer insulating film 108. That is, the light-shielding layer 330 is disposed between the light-emitting element 150 and the transistor 203. Therefore, even if scattered light or the like is emitted upward from the light-emitting element 150, the emitted light is unlikely to reach the TFT channel 204, thus preventing malfunction of the transistor 203.

[0298] The light-shielding layer 330 can be formed using a conductive material such as metal, and can be connected to any potential. For example, by placing a portion of the light-shielding layer 330 directly below a switching element such as a transistor 203 and connecting it to a ground potential, a power supply potential, etc., noise suppression can also be aided.

[0299] The light-shielding layer 330 is not limited to the application in this embodiment, and can be applied to sub-pixels in other embodiments described above and in other embodiments described later. When applied to other embodiments, the same effect as described above can also be obtained.

[0300] In the above examples, the structure and manufacturing method of a light-emitting element with a roughened light-emitting surface have been described. In light-emitting elements having connecting portions, a roughened light-emitting surface can be applied as in this embodiment. Specifically, this applies to the light-emitting element 150 in the first embodiment, the light-emitting element 250 in the second embodiment, the light-emitting element 550 in the fifth embodiment (described later), and the semiconductor layer 650 in the sixth embodiment. By applying roughening to the light-emitting surface of these constituent elements, the aforementioned effects can be achieved.

[0301] (Fourth Implementation)

[0302] Figure 26 This is a schematic cross-sectional view illustrating a portion of the image display device of this embodiment.

[0303] In this embodiment, a second wiring layer 440 is included between the light-emitting element 150 and the first surface 403a. The second wiring layer 440 is formed of a light-transmitting conductive film and is electrically connected to the light-emitting element 150. The light-emitting element 150 is connected to the second wiring layer 440 with its light-emitting surface 151S. This embodiment differs from the other embodiments described above in that a structure including the light-emitting element 150 is formed on an organic transparent resin substrate 402 and a color filter 180 is disposed across the substrate 402. Otherwise, it is the same as the other embodiments described above; for the same constituent elements, the same reference numerals are used, and detailed descriptions are appropriately omitted.

[0304] like Figure 26 As shown, the sub-pixel 420 of the image display device in this embodiment includes a substrate 402, a second wiring layer 440, a light-emitting element 150, a light-shielding electrode 160a, a first interlayer insulating film 156, a transistor 103, a second interlayer insulating film 108, a via 161k, a first wiring layer 110, and a color filter 180.

[0305] The substrate 402 is a light-transmitting component and is a substrate made of transparent resin. Preferably, as in this example, a Si compound layer 403 is formed on one side 402a of the substrate 402. A color filter 180 is provided on the other side (second side) 402b of the substrate 402. The layer 403 functions as an adhesive layer for bonding semiconductor layers. The side of the layer 403 facing the side on which the substrate 402 is provided is designated as the first side 403a.

[0306] A second wiring layer 440 is disposed on the first surface 403a. The second wiring layer 440 includes wirings 440a. The wirings 440a are disposed between the light-emitting element 150 and the first surface 403a. The second wiring layer 440 includes a plurality of wirings 440a depending on the plurality of light-emitting elements 150; in this example, each wiring 440a is separate.

[0307] The second wiring layer 440 is formed of a transparent conductive film. The conductive film may be, for example, a transparent conductive film such as ITO or ZnO. Wiring 440a is also formed of the same material.

[0308] The second wiring layer 440 and wiring 440a are connected to the first surface 403a. The light-emitting element 150 is connected to and electrically connected to wiring 440a via its light-emitting surface 151S. The outer periphery of wiring 440a is configured such that when the light-emitting element 150 is projected onto wiring 440a in an XY plane view, the outer periphery of the light-emitting element 150 is included. Wiring 440a is configured to protrude in one direction from directly below the light-emitting surface 151S onto the first surface 403a. One end of via 161k is connected to the protruding area of ​​wiring 440a. Therefore, the n-type semiconductor layer 151 is connected via wiring 440a, via 161k, and wiring 110k, for example, to the [described later] Figure 27 The grounding wire 4 of the circuit is electrically connected.

[0309] A color filter 180 is disposed on another surface 402b of the substrate 402. The color filter 180 is the same as the color filter described in the third embodiment. The color filter 180 can be a film-type color filter or a color filter formed by inkjet printing.

[0310] The other structures are the same as in the first embodiment, and detailed descriptions are omitted.

[0311] Figure 27 This is a schematic block diagram illustrating the image display device of this embodiment.

[0312] like Figure 27 As shown, in the image display device 401 of this embodiment, sub-pixels 420 are arranged in the display area 2. The sub-pixels 420 are arranged in a grid pattern, for example. For example, n sub-pixels 420 are arranged along the X-axis and m sub-pixels are arranged along the Y-axis.

[0313] Pixel 10 includes multiple sub-pixels 420 that emit light of different colors. Sub-pixel 420R emits red light. Sub-pixel 420G emits green light. Sub-pixel 420B emits blue light. The emission color and luminance of one pixel 10 are determined by the three sub-pixels 420R, 420G, and 420B emitting light at a desired luminance. The configuration of each color, etc., is the same as in the third embodiment.

[0314] In the image display device 401 of this embodiment, the structures of the power line 3, ground line 4, scan line 6, and signal line 8 are the same as in the first embodiment. However, the image display device 401 differs from the first embodiment in that the emission color and brightness of one pixel 10 are determined by causing the three types of sub-pixels to emit light at a set brightness. Aside from possible differences in the structure of the signals used for this purpose, the structure differs from the first embodiment. Figure 2 The examples are the same, so a detailed description of the circuit structure is omitted.

[0315] The manufacturing method of the image display device according to this embodiment will be described.

[0316] Figures 28A to 31 This is a schematic cross-sectional view illustrating a part of the manufacturing method of the image display device according to this embodiment.

[0317] In the manufacturing method of the image display device of this embodiment, the method used in the first embodiment is applied. Figure 4A and Figure 4B The following instructions apply to the procedures described. Figure 4B The subsequent procedures.

[0318] like Figure 28A As shown, a transparent conductive layer 1440 is formed on the semiconductor layer 1150. The conductive layer 1440 is formed on the exposed surface 1151E of the n-type semiconductor layer 1151.

[0319] like Figure 28B As shown, the semiconductor layer 1150 is bonded to the first surface 403a via the conductive layer 1440.

[0320] like Figure 29A As shown, Figure 28B The metal layer 1163 and semiconductor layer 1150 shown are respectively etched into desired shapes to form a light-shielding electrode 160a and a light-emitting element 150.

[0321] Will Figure 28B The conductive layer 1440 shown is processed into a shape including wiring 440a to form a second wiring layer 440. The formation process of the second wiring layer 440 and wiring 440a can be performed before or after the formation process of the light-shielding electrode 160a and the light-emitting element 150.

[0322] Subsequently, as in other embodiments, a first interlayer insulating film 156 is formed. The first interlayer insulating film 156 covers the first surface 403a, the second wiring layer 440, the light-emitting element 150, and the light-shielding electrode 160a.

[0323] like Figure 29BAs shown, a TFT lower layer 106 is formed on the first interlayer insulating film 156, and a polycrystalline Si layer 1104 is formed on the TFT lower layer 106.

[0324] Subsequently, the Si layer 1104 is processed into island-like structures using processes such as LTPS. Figure 30A As shown, a TFT channel 104, an insulating layer 105, a gate 107, and regions 104s, 104d, and 104i are formed.

[0325] like Figure 30B As shown, vias 111s, 111d, 161a, and 161k are formed, and a first wiring layer 110 is formed on the second interlayer insulating film 108. The via (second via) 161k is formed by filling a through-hole, which is formed to reach wiring 440a, with a conductive material. The via 161k electrically connects wiring 110k and wiring 440a.

[0326] Figures 29A to 30B The details of each manufacturing process can be fully applied to the techniques described in the manufacturing method of the image display device in other embodiments.

[0327] like Figure 31 As shown, an adhesive layer 1170 is provided on the second interlayer insulating film and the first wiring layer 110, and the reinforcing substrate 1180 is bonded using the adhesive layer 1170. Figure 30B The substrate 102 shown is removed using wet etching and laser stripping. A color filter (wavelength conversion component) 180 is formed on the other side (second side) 402b of the substrate 402.

[0328] In this embodiment, the organic transparent resin substrate 402 can be replaced, and similar to the third embodiment, the glass substrate can be thinned or the entire glass substrate can be removed, and a color filter 180 can be provided on the surface after the glass substrate is removed.

[0329] The effects of the image display device 401 in this embodiment will be explained.

[0330] In the image display device 401 of this embodiment, the time for the transfer process to form the light-emitting element 150 and the number of processes can be shortened in the same way as in the other embodiments described above.

[0331] The second wiring layer 440 and wiring 440a are formed from a transparent conductive film such as ITO, which makes them easy to process and can sometimes shorten a series of manufacturing steps for the light-emitting element 150, the light-shielding electrode 160a and the second wiring layer 440.

[0332] In this embodiment, since the second wiring layer 440 and wiring 440a are used to lead out the electrodes on the light-emitting surface 151S side, the light-emitting element 150 can be configured as a vertical light-emitting element. In the vertical light-emitting element 150, the current flowing in the semiconductor layer can be configured to flow approximately along the Z-axis instead of the component along the XY plane, thus having the advantage of reducing losses in the semiconductor layer.

[0333] In this embodiment, the substrate 402 is formed of an organic transparent resin, and therefore has flexibility. As a result, the image display device 401 can be bent, and can be seamlessly applied to curved surfaces and utilized in wearable terminals, etc.

[0334] In this embodiment, the image display device includes a color filter 180, but it may also be configured without a color filter as in the other embodiments described above.

[0335] (Fifth Implementation)

[0336] Figure 32 This is a schematic cross-sectional view illustrating a portion of the image display device of this embodiment.

[0337] In this embodiment, the structure of the light-emitting element 550 differs from that in other embodiments. Other constituent elements are the same as in the other embodiments described above. For the same constituent elements, the same reference numerals are used, and detailed descriptions are omitted where appropriate.

[0338] like Figure 32 As shown, the second wiring layer 440 includes wiring 540a. The second wiring layer 440 and wiring 540a are connected to the first surface 103a. The light-emitting element 550 is connected to and electrically connected to wiring 540a via its light-emitting surface 551S. The outer periphery of wiring 540a is arranged such that, when viewed in the XY plane, the outer periphery of the light-emitting element 550 is included when projected onto wiring 540a. Wiring 540a is arranged to protrude in one direction from directly below the light-emitting surface 551S onto the first surface 103a. One end of via 161k is connected to the protruding region of wiring 540a. Therefore, the n-type semiconductor layer 551 is connected, for example, to the aforementioned... Figure 2 The grounding wire 4 of the circuit is electrically connected.

[0339] In this embodiment, the light-shielding layer 330 is disposed between the lower TFT film 106 and the first interlayer insulating film 156. The light-shielding layer 330 is similar to that used in the third embodiment. Figure 18The same filter layer is described. The light-shielding layer 330 includes a second portion 530a. The second portion 530a has a region that includes the outer periphery of the TFT channel 104 when the TFT channel 104 is projected onto the second portion 530a when viewed in the XY plane.

[0340] A light-emitting element 550 is disposed on wiring 540a. The light-emitting element 550 is a frustum-shaped or truncated cone-shaped element formed such that its area decreases towards the positive Z-axis when viewed in the XY plane. The light-emitting element 550 includes a light-emitting surface 551S on a first surface 103a and an upper surface 553U disposed on the opposite side of the light-emitting surface 551S. The light-emitting surface 551S is disposed on the first surface 103a. The light-emitting element 550 includes an n-type semiconductor layer 551, a light-emitting layer 552, and a p-type semiconductor layer 553. The n-type semiconductor layer 551, the light-emitting layer 552, and the p-type semiconductor layer 553 are stacked sequentially from the first surface 103a side. A light-shielding electrode 560a is disposed throughout the upper surface 553U.

[0341] Figure 33 yes Figure 32 An enlarged view of a portion of the light-emitting element 550 shows the detailed positional relationship between the first surface 103a and the light-emitting element 550.

[0342] like Figure 33 As shown, the first surface 103a is a plane that is approximately parallel to the XY plane. A light-emitting element 550 is disposed on the first surface 103a, and a light-emitting surface 551S is a surface that is approximately parallel to the first surface 103a. A wiring 540a is disposed on the first surface 103a, and the light-emitting surface 551S is disposed on the first surface 103a across the wiring 540a. The wiring 540a is sufficiently thin, resulting in minimal light reflection and absorption.

[0343] The light-emitting element 550 has a side surface 555a. Side surface 555a is the surface between the upper surface 553U and the first surface 103a, and is adjacent to the light-emitting surface 551S. The interior angle θ between side surface 555a and the first surface 103a is less than 90°. Preferably, the interior angle θ is approximately 70°. More preferably, the interior angle θ is smaller than the critical angle at side surface 555a, which is determined based on the refractive index of the light-emitting element 550 and the refractive index of the first interlayer insulating film 156. The light-emitting element 550 is covered by the first interlayer insulating film 156, and side surface 555a is in contact with the first interlayer insulating film 156.

[0344] The critical angle θc of the interior angle θ formed by the side surface 555a and the first surface 103a of the light-emitting element 550 is determined, for example, as follows.

[0345] If the refractive index n0 of the light-emitting element 550 and the refractive index n1 of the first interlayer insulating film 156 are set, the critical angle θc of the light emitted from the light-emitting element 550 to the first interlayer insulating film 156 is obtained by the following formula (1).

[0346] θc=90°-sin -1 (n1 / n0) (1)

[0347] For example, it is known that the refractive index of common transparent organic insulating materials such as acrylic resin is around 1.4 to 1.5. Therefore, when the light-emitting element 550 is formed of GaN and the first interlayer insulating film 156 is formed of a common transparent organic insulating material, the refractive index of the light-emitting element 550 can be set to n0 = 2.5 and the refractive index of the first interlayer insulating film 156 to n = 1.4. By substituting these values ​​into equation (1), the critical angle θc = 56° is obtained.

[0348] This means that when the interior angle θ between the first surface 103a and the side surface 555a is set to θc = 56°, the light emitted from the light-emitting layer 552 that is parallel to the first surface 103a is totally reflected by the side surface 555a. Furthermore, this means that the light emitted from the light-emitting layer 552 with the positive Z-axis component is also totally reflected by the side surface 555a. In the above, for simplicity, the first interlayer insulating film 156 is set to a transparent resin; however, even if the transparent resin is set to a white resin, the scattering particles used in the white resin have a small effect on the refractive index, and therefore are ignored in the above calculations.

[0349] On the other hand, the light component with the negative Z-axis in the light emitted from the light-emitting layer 552 exits from the side 555a at an exit angle corresponding to the refractive index. The light incident on the first interlayer insulating film 156 exits from the first interlayer insulating film 156 at an angle determined by the refractive index of the first interlayer insulating film 156.

[0350] The light, after total internal reflection by side surface 555a, is reflected again by light-shielding electrode 560a. The light component with the negative Z-axis direction in the reflected light exits from the light-emitting surface 551S and side surface 555a. The light parallel to the first surface 103a and the light component with the positive Z-axis direction are total internally reflected by side surface 555a.

[0351] In this way, the light emitted from the light-emitting layer 552 that is parallel to the first surface 103a and has a component in the positive direction of the Z-axis is converted by the side surface 555a and the light-shielding electrode 160a into light with a component in the negative direction of the Z-axis. Therefore, in the light emitted from the light-emitting element 550, the proportion that goes towards the light-emitting surface 551S increases, and the substantial luminous efficiency of the light-emitting element 550 is improved.

[0352] By setting θ < θc, most of the light with a component parallel to the first surface 103a can be totally internally reflected into the light-emitting element 550. If the refractive index of the first interlayer insulating film 156 is set to n = 1.4, the critical angle θc becomes about 56°. Therefore, the interior angle θ is more preferably set to 45°, 30°, etc. In addition, if the material has a larger refractive index n, the critical angle θc becomes smaller. However, even if the interior angle θ is set to about 70°, most of the light with a component in the negative direction of the Z-axis can be converted into light with a component in the positive direction of the Z-axis. Therefore, manufacturing deviations can be taken into account, and for example, the interior angle θ can be set to 80° or less.

[0353] The manufacturing method of the image display device according to this embodiment will be described.

[0354] In this embodiment, the manufacturing process of the light-emitting element 550 and the light-shielding electrode 560a differs from that in other embodiments, although the other manufacturing processes can be implemented as described in the other embodiments. Hereinafter, the different parts of the manufacturing process will be explained.

[0355] In this embodiment, in order to set as Figure 32 The following steps are performed on the light-emitting element 550, which has the shape shown.

[0356] Will Figure 28B The semiconductor layer 1150 shown is bonded to the first surface 103a and then etched to form... Figure 32 The shape of the light-emitting element 550 is shown. In the forming of the light-emitting element 550, to make... Figure 33 The etching rate is selected such that the side surface 555a forms an interior angle θ with respect to the surface of the first surface 103a. For example, with respect to etching, a higher etching rate is selected the closer to the upper surface 553U. Preferably, the etching rate is set in a manner that increases linearly from the light-emitting surface 551S side toward the upper surface 553U side.

[0357] Specifically, for example, the resist mask pattern during dry etching is planned in advance during exposure so that it gradually thins towards its ends. Therefore, during dry etching, by gradually retreating from the thinner resist portion, the etching amount can be increased from the light-emitting surface 551S towards the upper surface 553U. Consequently, the side surface 555a of the light-emitting element 550 is formed at an angle relative to the first surface 103a. Therefore, in the light-emitting element 550, the area of ​​each layer from the upper surface 553U, when viewed in the XY plane, is formed such that the area increases in the order of p-type semiconductor layer 553, light-emitting layer 552, and n-type semiconductor layer 551.

[0358] Subsequently, as in other implementations, sub-pixel 520 is formed.

[0359] The effects of the image display device in this embodiment will be explained.

[0360] In addition to the effect of shortening the transfer process time for forming the light-emitting element 550 and reducing the number of processes, as in the other embodiments described above, the image display device of this embodiment also has the following effects.

[0361] In the image display device of this embodiment, the light-emitting element 550 is formed with a side surface 555a having an interior angle θ relative to the first surface 103a on which the light-emitting element 550 is disposed. The interior angle θ is less than 90° and is set based on a critical angle θc determined by the refractive index of the materials of the light-emitting element 550 and the first interlayer insulating film 156. The interior angle θ can convert light emitted from the light-emitting layer 552 that is directed to the side or top of the light-emitting element 550 into light that is directed to the light-emitting surface 551S and emitted. By making the interior angle θ sufficiently small, the luminous efficiency in the light-emitting element 550 is substantially improved.

[0362] In this embodiment, the light-emitting element 550 is a vertical element and is connected to the via 161k using the second wiring layer 440. However, it is not limited to this; alternatively, the light-emitting element may be connected to the via 161k via a connection portion formed on the first surface 103a.

[0363] (Sixth Implementation Method)

[0364] Figure 34 This is a schematic cross-sectional view illustrating a portion of the image display device of this embodiment.

[0365] In this embodiment, the image display device differs from other embodiments in that it includes a sub-pixel group 620 comprising multiple light-emitting regions on a single light-emitting surface. Detailed descriptions of the same components are omitted as appropriate, using the same reference numerals.

[0366] like Figure 34 As shown, the image display device of this embodiment includes a sub-pixel group 620. The sub-pixel group 620 includes a substrate 102, a semiconductor layer 650, a plurality of light-shielding electrodes 660a1, 660a2, a first interlayer insulating film 156, a plurality of transistors 103-1, 103-2, a second interlayer insulating film 108, a plurality of vias (first vias) 661a1, 661a2, and a first wiring layer 110. The semiconductor layer 650 is disposed on the first surface 103a.

[0367] In this embodiment, by turning on the p-channel transistors 103-1 and 103-2, holes are injected from one side of the semiconductor layer 650 via the first wiring layer 110 and vias 661a1 and 661a2. Electrons are injected from the other side of the semiconductor layer 650 via the first wiring layer 110 by turning on the p-channel transistors 103-1 and 103-2. With holes and electrons injected into the semiconductor layer 650, the separated light-emitting layers 652a1 and 652a2 emit light through the coupling of holes and electrons. The driving circuit used to drive the light-emitting layers 652a1 and 652a2 is applied for example... Figure 2 The circuit structure shown is also possible. Alternatively, the example of the second embodiment can be used, where the n-type and p-type semiconductor layers are interchanged, and a structure is constructed using an n-channel transistor to drive the semiconductor layers. In this case, the driving circuit applies... Figure 11 The circuit structure.

[0368] The structure of sub-pixel group 620 is described in detail.

[0369] The semiconductor layer 650 has a light-emitting surface 651S that is in contact with the first surface 103a. The light-emitting surface 651S is a surface of the n-type semiconductor layer 651. The light-emitting surface 651S includes a plurality of light-emitting regions 651R1 and 651R2.

[0370] Semiconductor layer 650 includes an n-type semiconductor layer 651, light-emitting layers 652a1 and 652a2, and p-type semiconductor layers 653a1 and 653a2. Light-emitting layer 652a1 is disposed on the n-type semiconductor layer 651. Light-emitting layer 652a1 and light-emitting layer 652a2 are disposed separately and spaced apart on the n-type semiconductor layer 651. P-type semiconductor layer 653a1 is disposed on the light-emitting layer 652a1. P-type semiconductor layer 653a2 and p-type semiconductor layer 653a1 are disposed separately and spaced apart on the light-emitting layer 652a2.

[0371] The p-type semiconductor layer 653a1 has an upper surface 653U1 disposed on the side opposite to the surface on which the light-emitting layer 652a1 is disposed. The p-type semiconductor layer 653a2 has an upper surface 653U2 disposed on the side opposite to the surface on which the light-emitting layer 652a2 is disposed.

[0372] The luminescent region 651R1 is approximately the same as the region on the opposite side of the upper surface 653U1 in the luminescent surface 651S. The luminescent region 651R2 is approximately the same as the region on the opposite side of the upper surface 653U2 in the luminescent surface 651S.

[0373] Figure 35 This is a schematic cross-sectional view illustrating a portion of the image display device of this embodiment.

[0374] Figure 35This is a schematic diagram used to illustrate the light-emitting regions 651R1 and 651R2.

[0375] like Figure 35 As shown, the light-emitting regions 651R1 and 651R2 are surfaces on the light-emitting surface 651S. Figure 35 In this design, the portions of semiconductor layer 650 including light-emitting regions 651R1 and 651R2 are referred to as light-emitting portions R1 and R2, respectively. Light-emitting portion R1 includes a portion of n-type semiconductor layer 651, a light-emitting layer 652a1, and a p-type semiconductor layer 653a1. Light-emitting portion R2 includes a portion of n-type semiconductor layer 651, a light-emitting layer 652a2, and a p-type semiconductor layer 653a2.

[0376] Semiconductor layer 650 includes a connection portion R0. The connection portion R0 is disposed between light-emitting portions R1 and R2 and is part of n-type semiconductor layer 651. At one end of the connection portion R0, a via 661k is connected, and the connection portion R0 provides a path for current from the via 661k to the light-emitting portions R1 and R2.

[0377] In the light-emitting section R1, electrons supplied via the connecting section R0 are supplied to the light-emitting layer 652a1. Holes supplied via the light-shielding electrode 660a1 are also supplied to the light-emitting layer 652a1 in the light-emitting section R1. The electrons and holes supplied to the light-emitting layer 652a1 couple to emit light. The light emitted from the light-emitting layer 652a1 passes through a portion of the n-type semiconductor layer 651 in the light-emitting section R1 and reaches the light-emitting surface 651S. The light travels approximately perpendicularly along the Z-axis within the light-emitting section R1; therefore, the portion of the light-emitting surface 651S that emits light becomes the light-emitting region 651R1. Thus, in this example, the light-emitting region 651R1, when viewed in the XY plane, approximately coincides with the region enclosed by the outer periphery of the light-emitting layer 652a1 projected onto the light-emitting surface 651S.

[0378] The light-emitting portion R2 is the same as that of the light-emitting portion R1. That is, in the light-emitting portion R2, electrons supplied via the connecting portion R0 are supplied to the light-emitting layer 652a2. In the light-emitting portion R2, holes supplied via the light-shielding electrode 660a2 are supplied to the light-emitting layer 652a2. The electrons and holes supplied to the light-emitting layer 652a2 couple to emit light. The light emitted from the light-emitting layer 652a2 passes through a portion of the n-type semiconductor layer 651 of the light-emitting portion R2 and reaches the light-emitting surface 651S. The light travels approximately perpendicularly along the Z-axis direction within the light-emitting portion R2, therefore the portion of the light emitting surface 651S that emits light becomes the light-emitting region 651R2. Therefore, in this example, the light-emitting region 651R2, when viewed in the XY plane, is approximately the same as the region surrounded by the outer periphery of the light-emitting layer 652a2 projected onto the light-emitting surface 651S.

[0379] In this way, in the semiconductor layer 650, an n-type semiconductor layer 651 can be shared, and multiple light-emitting regions 651R1 and 651R2 can be formed on the light-emitting surface 651S.

[0380] In this embodiment, the semiconductor layer 650 can be formed by setting a portion of the n-type semiconductor layer 651 as a connecting portion R0 among the plurality of light-emitting layers 652a1, 652a2 and the plurality of p-type semiconductor layers 653a1, 653a2 of the semiconductor layer 650. Therefore, the semiconductor layer 650 can be formed in the same way as the light-emitting elements 150, 250 in the first embodiment, second embodiment, etc. described above.

[0381] return Figure 34 And continue to explain.

[0382] The first interlayer insulating film 156 (first insulating film) is provided in such a way that it covers the first surface 103a, the semiconductor layer 650, and the light-shielding electrodes 660a1 and 660a2.

[0383] A TFT lower layer film 106 is formed on the first interlayer insulating film 156. The TFT lower layer film 106 is planarized, and TFT channels 104-1, 104-2, etc. are formed on the TFT lower layer film 106.

[0384] An insulating layer 105 covers the lower TFT film 106 and TFT channels 104-1 and 104-2. A gate 107-1 is disposed on the TFT channel 104-1 through the insulating layer 105. A gate 107-2 is disposed on the TFT channel 104-2 through the insulating layer 105. A transistor 103-1 includes the TFT channel 104-1 and the gate 107-1. A transistor 103-2 includes the TFT channel 104-2 and the gate 107-2.

[0385] The second interlayer insulating film (second insulating film) 108 covers the insulating layer 105, gate 107-1, and gate 107-2.

[0386] TFT channel 104-1 includes p-type doped regions 104s1 and 104d1, which are the source and drain regions of transistor 103-1, respectively. Region 104i1 is doped to n-type, forming the channel of transistor 103-1. TFT channel 104-2 similarly includes p-type doped regions 104s2 and 104d2, which are the source and drain regions of transistor 103-2, respectively. Region 104i2 is doped to n-type, forming the channel of transistor 103-2. In this embodiment, circuit 101 includes TFT channels 104-1 and 104-2, insulating layer 105, second interlayer insulating film 108, vias 111s1, 111d1, 111s2, and 111d2, and a first wiring layer 110.

[0387] The first wiring layer 110 is disposed on the second interlayer insulating film 108. The first wiring layer 110 includes wirings 610s1, 610d1, 610k, 610d2, and 610s2.

[0388] Wiring 610k is disposed above n-type semiconductor layer 651. Via 661k is disposed between wiring 610k and n-type semiconductor layer 651, electrically connecting wiring 610k and n-type semiconductor layer 651. Wiring 610k is connected, for example, to... Figure 2 4. Grounding wire of the circuit.

[0389] Vias 111d1, 111s1, 111d2, and 111s2 are provided to penetrate the second interlayer insulating film 108 and the insulating layer 105. Via 111d1 is provided between region 104d1 and wiring 610d1, electrically connecting region 104d1 and wiring 610d1. Via 111s1 is provided between region 104s1 and wiring 610s1, electrically connecting region 104s1 and wiring 610s1. Via 111d2 is provided between region 104d2 and wiring 610d2, electrically connecting region 104d2 and wiring 610d2. Via 111s2 is provided between region 104s2 and wiring 610s2, electrically connecting region 104s2 and wiring 610s2. Wiring 610s1 and 610s2 are connected, for example, to... Figure 2 3. Power supply line of the circuit.

[0390] Wiring 610d1 is disposed above light-shielding electrode 660a1. Via 661a1 is disposed between wiring 610d1 and light-shielding electrode 660a1, electrically connecting them. Therefore, the p-type semiconductor layer 653a1 is electrically connected to the drain region of transistor 103-1 via light-shielding electrode 660a1, via 661a1, wiring 610d1, and via 611d1.

[0391] Wiring 610d2 is disposed above light-shielding electrode 660a2. Via 661a2 is disposed between wiring 610d2 and light-shielding electrode 660a2, electrically connecting them. Therefore, the p-type semiconductor layer 653a2 is electrically connected to the drain region of transistor 103-2 via light-shielding electrode 660a2, via 661a2, wiring 610d2, and via 611d2.

[0392] For example, transistors 103-1 and 103-2 are driving transistors for adjacent sub-pixels and are driven sequentially. If holes supplied from transistor 103-1 are injected into the light-emitting layer 652a1, and electrons supplied from wiring 610k are injected into the light-emitting layer 652a1, then the light-emitting layer 652a1 emits light, emitting light from the light-emitting region 651R1. If holes supplied from transistor 103-2 are injected into the light-emitting layer 652a2, and electrons supplied from wiring 610k are injected into the light-emitting layer 652a2, then the light-emitting layer 652a2 emits light, emitting light from the light-emitting region 651R2.

[0393] The effects of the image display device in this embodiment will be explained.

[0394] The image display device of this embodiment achieves the same effect as the image display devices of the other embodiments described above, by shortening the transfer process time for forming the semiconductor layer 650 and reducing the number of processes. Furthermore, since the multiple light-emitting portions R1 and R2 can share a common connection portion R0, the number of vias 661k provided in the connection portion R0 can be reduced. By reducing the number of vias, the spacing between the light-emitting portions R1 and R2 constituting the sub-pixel group 620 can be reduced, enabling the creation of a small, high-resolution image display device. In this example, the case of two light-emitting regions has been described, but the number of light-emitting regions formed on the light-emitting surface is not limited to two; it can be any number of three or more.

[0395] (Seventh Implementation)

[0396] The aforementioned image display device can be used as an image display module with a suitable number of pixels, for example, as a computer monitor, television, portable terminal such as a smartphone, or car navigation system.

[0397] Figure 36 This is a block diagram illustrating an image display device according to this embodiment.

[0398] exist Figure 36 The diagram shows the main structural components of a computer monitor.

[0399] like Figure 36As shown, the image display device 701 includes an image display module 702. The image display module 702 is, for example, an image display device with the structure described in the first embodiment. The image display module 702 includes a display area 2 having a plurality of sub-pixels, including sub-pixels 20, a row selection circuit 5, and a signal voltage output circuit 7.

[0400] The image display device 701 also includes a controller 770. The controller 770 takes in a control signal separated and generated by an interface circuit (not shown) as input, and controls the driving of each sub-pixel and the driving sequence of the row selection circuit 5 and the signal voltage output circuit 7.

[0401] (Modified Example)

[0402] The aforementioned image display device can be used as an image display module with a suitable number of pixels, for example, as a computer monitor, television, portable terminal such as a smartphone, or car navigation system.

[0403] Figure 37 This is a block diagram illustrating a variation of the image display device described in this embodiment.

[0404] exist Figure 37 The image shows the structure of a high-resolution, thin-film television.

[0405] like Figure 37 As shown, the image display device 801 includes an image display module 802. The image display module 802 is, for example, the image display device 1 with the structure described in the first embodiment. The image display device 801 includes a controller 870 and a frame memory 880. The controller 870 controls the driving order of each sub-pixel of the display area 2 based on control signals supplied by the bus 840. The frame memory 880 stores one frame of display data and is used for smooth video playback and other processing.

[0406] The image display device 801 includes an I / O circuit 810. The I / O circuit 810 is in Figure 37 This is abbreviated as "I / O". The I / O circuit 810 provides interface circuits for connecting to external terminals, devices, etc. The I / O circuit 810 includes, for example, a USB interface for connecting peripheral devices such as hard disk devices, an audio interface, etc.

[0407] The image display device 801 includes a receiving unit 820 and a signal processing unit 830. An antenna 822 is connected to the receiving unit 820, and the received radio waves are separated and the required signals are generated. The signal processing unit 830 includes a DSP (Digital Signal Processor), a CPU (Central Processing Unit), etc., and the signals separated and generated by the receiving unit 820 are separated by the signal processing unit 830 and generated into image data, voice data, etc.

[0408] By configuring the receiver 820 and signal processing unit 830 as high-frequency communication modules such as mobile phone transceivers, WiFi receivers, and GPS receivers, they can also be configured as other image display devices. For example, an image display device with an image display module having a suitable screen size and resolution can be configured as a portable information terminal such as a smartphone or a car navigation system.

[0409] The image display module in this embodiment is not limited to the structure of the image display device in the first embodiment, and may also be configured as a variant or other embodiment. The image display module in this embodiment and its variants is as follows: Figure 9 and Figure 25 As shown, it is configured as a structure that includes many sub-pixels.

[0410] According to the embodiments described above, a method for manufacturing an image display device and an image display device can be realized that shortens the transfer process of the light-emitting element and improves the yield.

[0411] The foregoing has described some embodiments of the present invention, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in a wide variety of other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and are included within the scope of the invention and its equivalents as described in the claims. Furthermore, the foregoing embodiments can be combined with each other.

[0412] Explanation of reference numerals in the attached figures

[0413] 1. Image display device (201, 301, 401, 701, 801); 2. Display area; 3. Power line; 4. Ground line; 5. 205. Row selection circuit; 6. 206. Scan line; 7. 207. Signal voltage output circuit; 8. 208. Signal line; 10. Pixel; 20, 220, 320, 420, 520 sub-pixels; 22. 222. Light-emitting element; 24. 224. Selection transistor; 26. 226. Driver transistor. 28, 228 capacitors, 100 driving circuit section, 101 circuit, 102, 402 substrate, 103a, 180a, 403a first surface, 103, 103-1, 103-2, 203 transistors, 104, 104-1, 104-2, 204 TFT channels, 105 insulating layer, 107, 107-1, 107-2 gate, 108 second interlayer insulating film, 110 first wiring layer, 1 50, 250, 550 light-emitting elements; 151a, 253a, R0 connecting parts; 151S, 151S1, 253S, 551S, 651S light-emitting surfaces; 156 first interlayer insulating film; 160a, 260k, 560a, 660a1, 660a2 light-shielding electrodes; 161a, 161k, 261a, 261k, 361a, 361k, 661a1, 661a2, 661k Vias, 172 Light-emitting circuit section, 180 Color filter, 330 Light-shielding layer, 440 Second wiring layer, 620 Sub-pixel group, 1001 Crystal growth substrate, 1150 Semiconductor layer, 1155 Transparent planarization film, 1161, 1162, 1163, 1164 Metal layers, 1180 Reinforcing substrate, 1190 Supporting substrate, 1192 Structure, 1194, 1294 Semiconductor growth substrate, 1440 Conductive layer.

Claims

1. A method for manufacturing an image display device, characterized in that, have: The process of preparing the semiconductor layer, including the light-emitting layer; The process of bonding the semiconductor layer to the first substrate via the first metal layer; The process of bonding the semiconductor layer to the first side of a light-transmitting substrate; The process of removing the first substrate; The process of etching the semiconductor layer to form a light-emitting element including a light-emitting surface on the first surface and an upper surface disposed on the opposite side of the light-emitting surface; The process of etching the first metal layer to form a light-shielding electrode that covers the upper surface and is electrically connected to the upper surface; The process of forming a first insulating film covering the first surface, the light-emitting element, and the light-shielding electrode; The process of forming circuit elements on the first insulating film; The process of forming a second insulating film covering the first insulating film and the circuit elements; The process of forming a first guide hole that penetrates the first insulating film and the second insulating film; The process of forming the first wiring layer on the second insulating film; The first via is disposed between the first wiring layer and the light-shielding electrode, electrically connecting the first wiring layer and the light-shielding electrode.

2. The method for manufacturing the image display device according to claim 1, The process of preparing the semiconductor layer includes the process of forming the first metal layer on the semiconductor layer.

3. The method for manufacturing the image display device according to claim 1, It also includes a step of forming the first metal layer on the bonding surface of the first substrate before the step of bonding the semiconductor layer to the first substrate.

4. The method for manufacturing the image display device according to claim 1, It also includes a step of roughening the exposed surface of the semiconductor layer and forming a light-transmitting film on the roughened surface before the step of bonding the semiconductor layer.

5. The method for manufacturing the image display device according to claim 1, It also includes a step of forming a second guide hole that penetrates the first insulating film and the second insulating film. The light-emitting element includes a connecting portion. The second guide hole is disposed between the first wiring layer and the connection part, electrically connecting the first wiring layer and the connection part.

6. The method for manufacturing an image display device according to claim 1, further comprising: The process of forming a light-transmitting conductive layer on the semiconductor layer prior to the process of bonding the semiconductor layer; The process of etching the conductive layer to form the second wiring layer after the process of removing the first substrate.

7. The method for manufacturing the image display device according to claim 6, It also includes a step of forming a second guide hole that penetrates the first insulating film and the second insulating film. The second via is disposed between the first wiring layer and the second wiring layer to electrically connect the first wiring layer and the second wiring layer.

8. The method for manufacturing the image display device according to claim 1, It also includes a step of forming a light-shielding layer on the first insulating film prior to the step of forming the circuit element.

9. The method for manufacturing the image display device according to claim 1, The semiconductor layer comprises a gallium nitride-based compound semiconductor.

10. The method for manufacturing the image display device according to claim 1, It also includes a process of forming a wavelength conversion component on a second surface opposite to the first surface.

11. The method for manufacturing the image display device according to claim 1, It also includes a process of removing the light-transmitting substrate and replacing it to form a wavelength conversion component.

12. A method for manufacturing an image display device, characterized in that, have: The process of preparing a semiconductor growth substrate having a semiconductor layer including a light-emitting layer and a substrate for crystal growth; The process of bonding the semiconductor layer to the first side of a light-transmitting substrate; The process of forming a second metal layer on the semiconductor layer after the process of removing the crystal growth substrate from the semiconductor growth substrate; The process of etching the semiconductor layer to form a light-emitting element including a light-emitting surface on the first surface and an upper surface disposed on the opposite side of the light-emitting surface; The process of etching the second metal layer to form a light-shielding electrode that covers the upper surface and is electrically connected to the upper surface; The process of forming a first insulating film covering the first surface, the light-emitting element, and the light-shielding electrode; The process of forming circuit elements on the first insulating film; The process of forming a second insulating film covering the circuit elements and the first insulating film; The process of forming a first guide hole that penetrates the first insulating film and the second insulating film; The process of forming the first wiring layer on the second insulating film; The first via is disposed between the first wiring layer and the light-shielding electrode, electrically connecting the first wiring layer and the light-shielding electrode.

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