Switching FET body current management apparatus and method

Abstract

Methods and apparatuses to reduce gate-induced drain leakage current in RF switch stacks are disclosed. The described apparatuses utilize multiple discharge paths and / or less negative bulk bias voltages without compromising the non-linear performance and power handling capability of the power switches. Furthermore, more compact bias voltage generation circuits with less amount of space can be implemented as part of the disclosed apparatuses.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. Patent Application No. 16 / 945,283, filed July 31, 2020, entitled “Methods And Devices To GenerateGate Induced Drain Leakage Current Sink Or Source Path For Switch FETs”; U.S. Patent Application No. 17 / 386,374, filed July 27, 2021, entitled “Switch FET Current Management Devices and Methods”; and U.S. Patent Application No. 17 / 386,409, filed July 27, 2021, entitled “Switch FET Current Management Devices and Methods”, all of which are incorporated herein by reference in their entirety. Background Technology (1) Technical Field

[0004] This disclosure relates to switching FETs, and more specifically to switching FETs with discharge paths using body current management methods and apparatus, and / or switching FETs that implement reduced negative body bias voltages for body current management.

[0005] (2) Background

[0006] When designing communication systems, RF switches are often implemented in a stacked configuration due to the high RF power handling requirements of such switch stacks. Figure 1A This illustrates a prior art field-effect transistor (FET) switch stack (100), which includes transistors (T1, ..., T2). n A series arrangement of resistors (R). As shown, a series arrangement of resistors (R) is used. B1 , ..., R Bn+1 The body resistor ladder, including the drain-source resistor (R) DS1 , ..., R DSN The FET switch stack (100) is biased using a drain-source resistor ladder and a gate resistor structure on the gate side of the transistor. The switch stack (100) is biased using bias voltages (VB, VG) generated by a bias generator circuit (not shown).

[0007] In practical applications, more specifically, in stacked switches experiencing large RF swings during the off-state, each transistor within the stack will generate an undesirable gate-induced drain / body leakage current (GIDL) that increases with the peak value of the RF swing. The GIDL current, as... Figure 1A The arrow (110) shown indicates the flow through the body resistor step. Due to the flow of unwanted GIDL current, the DC voltage distribution across the body resistor step is modified. In other words, the various switch stack nodes within the body resistor step will experience an undesirable DC bias voltage that would be supplied to such nodes by the bias circuit in the absence of such leakage current. Throughout this disclosure, the undesirable effect of the GIDL current on the DC bias voltage distribution across the entire stack is referred to as the "debiasing" effect.

[0008] Depend on Figure 1B Curve (102) further illustrates the debiasing effect. Figure 1B The curve represents Figure 1A An exemplary average DC voltage distribution of the body of the transistors in the switch stack (100) is shown, plotted with reference to the positions of the transistors in the stack. The DC voltage at the body terminals of the FET decreases from the top to the bottom of the stack. In other words, due to the unbalanced voltage distribution caused by undesirable GIDL currents, the transistor (T) n The voltage at the body terminal of transistor (T1) is the most positive, while the voltage at the body terminal of transistor (T2) is the most negative.

[0009] As described above, body debiasing leads to early breakdown of transistors within the FET switch stack, especially for those positioned closer to the top of the stack. Additionally, the GIDL current needs to be absorbed by the bias circuitry that provides the bias voltage to the switch stack. Higher GIDL currents require a more complex bias generator design due to the increased current capability needed. This may necessitate more design area to accommodate the bias generator. Furthermore, the DC current consumption of the bias circuitry will also increase.

[0010] Reference Figure 1A Under operating conditions, applying a more negative bias voltage (VB) when the RF switch is off will result in improved linearity. However, a more negative bias voltage (VB) will require more complex biasing circuitry, which occupies a larger area on the chip. DC current consumption will also increase.

[0011] Therefore, there is a need for methods and apparatuses that, without compromising power handling capability and linearity when the RF switch stack operates in the off state, reduce the undesirable effects of GIDL current while maintaining simpler, cheaper, and more compact bias circuitry. Methods and apparatuses that help maintain proper voltage distribution across the stack are also needed to prevent early potential voltage breakdown. Summary of the Invention

[0012] The disclosed methods and apparatus solve the problems mentioned above and provide solutions to the challenges described.

[0013] According to a first aspect of this disclosure, a field-effect transistor (FET) switch stack is provided, the FET switch stack comprising: FETs connected in series, one end coupled to a first terminal and the other end coupled to a second terminal, the first terminal being configured to receive an input radio frequency (RF) signal; a body resistance ladder coupled to the first terminal, the body resistance ladder including a plurality of body resistors connected in series, each body resistor being coupled across the body terminal of a corresponding adjacent FET in the series-connected FETs; and a first diode stack including one or more diodes, the diode stack having a first cathode terminal connected to the first terminal and a first anode terminal connected to the body terminal of the first FET in the series-connected FETs.

[0014] According to a second aspect of this disclosure, a field-effect transistor (FET) switch stack is provided, the FET switch stack comprising: FETs connected in series, one end coupled to a first terminal and the other end coupled to a second terminal, the first terminal being configured to receive an input radio frequency (RF) signal; a drain-source resistor ladder coupled to the first terminal, the drain-source resistor ladder including a plurality of drain-source resistors connected in series, each drain-source resistor being coupled across the drain-source terminals of a corresponding adjacent FET in the series-connected FETs; and a first diode stack including one or more diodes, the diode stack having a first anode terminal connected to the first terminal and a first cathode terminal connected to the source terminal of the first FET in the series-connected FETs.

[0015] According to a third aspect of this disclosure, a method is disclosed for driving a bias voltage of a FET switch stack toward a voltage distribution across the FET switch stack, the method comprising: generating an RF voltage source across the FET switch stack based on a radio frequency (RF) signal; and generating a current discharge path thereby forming a voltage distribution across the FET switch stack.

[0016] According to a fourth aspect of this disclosure, a field-effect transistor (FET) switch stack is disclosed, the FET switch stack comprising: FETs connected in series, one end coupled to a first terminal and the other end coupled to a second terminal, the first terminal being configured to receive an input radio frequency (RF) signal; a body resistor ladder coupled to the first terminal, the body resistor ladder including a plurality of body resistor elements connected in series, each body resistor element coupled across the body terminal of a corresponding adjacent FET in the series-connected FETs; and a body current management circuit coupled to the body resistor ladder, wherein: the FET switch stack is configured to receive a first bias voltage at a gate bias terminal of the FET switch stack and a second bias voltage at a body bias terminal of the FET switch stack; in an off-state of the FET switch stack, the first bias voltage and the second bias voltage are negative bias voltages; in the off-state, the second bias voltage is less negative than the first bias voltage, and the body current management circuit is configured to provide one or more current discharge paths for gate-sensing drain leakage current.

[0017] According to a fifth aspect of this disclosure, a method for biasing a radio frequency (RF) field-effect transistor (FET) switch stack in an off-state is disclosed, the RF FET switch stack including a series-connected FET coupled at one end to a first terminal and at the other end to a second terminal, the first terminal being configured to receive an input radio frequency (RF) signal, the method comprising: applying a negative gate bias voltage to the gate terminal of the series-connected FET; applying a negative body bias voltage to the body terminal of the series-connected FET, the body bias voltage being less negative than the gate bias voltage; applying an RF signal across the RF FET switch stack in an off-state; and, while the RF signal is applied, discharging a gate-induced drain leakage current through one or more current discharge paths, the discharge pulling down the voltage at the body terminal of the series-connected FET to a voltage much more negative than the body bias.

[0018] According to a sixth aspect of this disclosure, a field-effect transistor (FET) switch stack is disclosed, the FET switch stack comprising: FETs connected in series, one end coupled to a first terminal and the other end coupled to a second terminal, the first terminal being configured to receive a radio frequency (RF) signal; a body resistor step coupled to the first terminal, the body resistor step including a plurality of body resistor elements connected in series, each body resistor element coupled across the body terminal of a corresponding adjacent FET in the series-connected FETs; and a first diode element arrangement comprising: i) a diode element stack including two or more diode elements, the diode element stack being coupled between the body resistor step and the first terminal, and ii) one or more additional diode elements coupled to the body resistor step.

[0019] According to a seventh aspect of this disclosure, a method for controlling gate-induced drain leakage current in an off-state of a radio frequency (RF) switch stack is disclosed, the RF switch stack including i) a series-connected FET configured to receive an RF signal and ii) a body resistor step coupled to the body terminals of the series-connected FET, the method comprising: applying an RF signal to the RF switch stack; generating a first current discharge path for the gate-induced drain leakage current through the body resistor step during a first time interval in the off-state of the RF switch stack; and generating a second current discharge path for the gate-induced drain leakage current through the body resistor step during a second time interval in the off-state of the RF switch stack, wherein the second time interval partially overlaps with the first time interval in time during a first overlap time interval in the off-state of the RF switches that generate both the first and second current discharge paths.

[0020] Details of one or more embodiments of the invention are set forth in the accompanying drawings and the following description. Other features, objects, and advantages of the invention will become apparent from the specification, the drawings, and the claims. Attached Figure Description

[0021] Figure 1A A prior art FET switch stack is shown.

[0022] Figure 1B The diagram illustrates the prior art average DC voltage distribution of the body of the transistors in the FET switch stack relative to the location of such transistors within the stack when the FET switch stack is in the off state.

[0023] Figure 2A An exemplary FET switch stack according to an embodiment of this disclosure is shown.

[0024] Figure 2B Simulation results of exemplary RF signal waveforms illustrating embodiments according to this disclosure are shown.

[0025] Figure 2C An exemplary variation of the DC voltage of a node within a bulk resistor ladder of a switch stack according to an embodiment of this disclosure is shown.

[0026] Figure 3A An exemplary FET switch stack according to an embodiment of this disclosure is shown.

[0027] Figure 3B The diagram illustrates the variation of the DC voltage of a node within a drain-source resistor ladder according to an embodiment of this disclosure, relative to the location of such a node within an exemplary FET switch stack.

[0028] Figure 3CAn exemplary FET switch stack according to an embodiment of this disclosure is shown.

[0029] Figures 4A to 4B An exemplary FET switch stack implemented in a series configuration according to an embodiment of this disclosure is shown.

[0030] Figure 5A An exemplary FET switch stack according to an embodiment of this disclosure is shown.

[0031] Figure 5B A portion of an exemplary FET switch stack according to an embodiment of this disclosure is shown.

[0032] Figure 5C An exemplary graph illustrating an implementation according to this disclosure is shown.

[0033] Figure 5D A portion of an exemplary FET switch stack according to an embodiment of this disclosure is shown.

[0034] Figure 5E An exemplary graph illustrating an implementation according to this disclosure is shown.

[0035] Figure 5F A portion of an exemplary FET switch stack according to an embodiment of this disclosure is shown.

[0036] Figures 5G to 5H as well as Figure 6 An exemplary FET switch stack according to an embodiment of this disclosure is shown.

[0037] Figure 7 An exemplary graph illustrating an implementation according to this disclosure is shown.

[0038] Figure 8 A block diagram of an exemplary RF circuit according to an embodiment of the present disclosure is shown.

[0039] Figure 9 The bias generation circuit is shown.

[0040] Figures 10 to 11 An exemplary graph illustrating an implementation according to this disclosure is shown.

[0041] Figure 12 A block diagram of an exemplary RF circuit according to an embodiment of the present disclosure is shown.

[0042] Similar reference numerals and names in the various figures indicate similar elements. Detailed Implementation

[0043] Figure 2AAn exemplary FET switch stack (200A), particularly a stack of at least four switches, is shown according to an embodiment of this disclosure. The FET switch stack (200A) is coupled at one end to an RF port (RF) and at the other end to a reference voltage (e.g., ground (GND)). During operating conditions, an RF signal is transmitted to the RF switch stack (200A) via the RF port (RF). The FET switch stack (200A) includes transistors (T1, ..., T2). N A series arrangement of resistors (R) can be used. B1 , ..., R Bn+1 The body resistor ladder, including the drain-source resistor (R) DS1 , ..., R DSn The FET switch stack is biased by a drain-source resistor ladder and a gate resistor structure on the gate side of the transistor. Figure 2A The diagram also shows the bias voltages (VB, VG) used to bias the FET switch stack (200A). The bias voltages (VB, VG) can be generated by a bias voltage generator circuit (not shown for simplicity). Under operating conditions, when the FET switch stack (200A) is in the off state, the bias voltages (VB, VG) can be negative bias voltages.

[0044] Continue to refer to Figure 2A The FET switch stack (200A) includes diode stacks (201) and (202), each of which is coupled across one or more resistors in a body resistor ladder. According to an embodiment of this disclosure, the diode stack (201) includes one or more diodes (D1, ..., D2) connected in series. M The diode stack (201) has terminals (A1, K1) and is connected to the bulk resistor ladder via these terminals (A1, K1). Furthermore, the diode stack (202) includes one or more diodes (D'1, ..., D') connected in series. NThe diode stack (202) has terminals (A2, K2) and is connected to the bulk resistor ladder via these terminals. Throughout this disclosure, the term diode will be used not only to refer to a diode itself but also to a transistor connected to a diode. A minimum number of diodes in series can be used in the diode stack (201) provided that when a maximum positive voltage RF signal is applied to the FET switch stack (200A) and the diode stack (202) is in the off state, the voltage across the node of each diode in the diode stack (201) is within the diode's voltage reliability limit. A minimum number of diodes in series can be used in the diode stack (202) provided that when a maximum negative voltage RF signal is applied to the FET switch stack (200A) and the diode stack (202) is in the off state, the voltage across the node of each diode in the diode stack (202) is within the diode's voltage reliability limit.

[0045] Other embodiments are also conceivable, based on the teachings of this disclosure and including only one of two diode stacks (201) or (202), wherein only one existing diode stack may have one or more diodes. In a preferred embodiment, terminal (K1) is connected to the RF port (RF), terminal (A1) is connected to a node within the body resistor ladder, terminal (A2) is connected to a node within the body resistor ladder, and terminal (K2) is connected to a reference voltage (e.g., ground). Furthermore, the resistor (R... B1 , ..., R Bn+1 Any resistor in the array can be divided into two or more resistors. Terminals (A1) or (A2) can be connected to the node between these separate resistors. Also, Figure 2A As shown, the diode stack (201, 202) can be connected across the bulk resistor step with opposite polarities. For example, as will be described in more detail later, under operating conditions, the diode stack (202) conducts current from top to bottom, while the diode stack (201) conducts current from bottom to top. Also as mentioned above, any diode within the diode stack (201) or (202) can be implemented using diode-connected transistors.

[0046] As previously mentioned, unwanted GIDL currents in the switch stack cause debiasing problems, leading to potential premature breakdown of transistors within the stack, especially those closer to the RF port. Furthermore, the GIDL current needs to be absorbed, i.e., discharged from the stack. See also... Figure 2A The diode stack (201) solves the debiasing problem by absorbing the GIDL current to the RF port, while the diode stack (202) solves the debiasing problem by absorbing the GIDL current to ground.

[0047] Continue to refer to Figure 2A The FET switch stack (200A) receives an RF signal through an RF port (RF). When the FET switch stack (200A) is off and during the negative swing of the RF signal, the diode stack (201) is on, thereby creating a discharge path for GIDL current through the RF port (RF). Conversely, during the positive swing, the diode stack (202) is on to create a discharge path for GIDL current through ground. Those skilled in the art will recognize that the synergistic use of the two diode stacks (201, 202) also provides more symmetry to the structure of the FET switch stack (200A), thus improving the nonlinear distortion performance of the switch stack (e.g., reducing harmonics). It is also understood that such symmetry is an optional feature, not a requirement.

[0048] In the following paragraphs:

[0049] ·V RF+ and V RF- These represent the positive and negative peak values ​​of the applied RF voltage, respectively.

[0050] ·R B1 =R Bn+1 =R / 2 and R B2 =R B3 =......=R Bn =R,

[0051] ·V RB+ and V RB- Let R and RF represent the positive and negative peak values ​​of the voltage drop across the body resistor R in the body resistor step, respectively.

[0052] ·m and k represent the number of diodes in the diode stack (201, 202), where m and k may be the same or different, and

[0053] Vth represents the threshold voltage of the diodes within the diode stack (201) or (202).

[0054] • By way of example, rather than limitation, if an RF voltage with a peak value of 100V is applied to a stack of switches with 25 transistors, then V RB+ =100 / 25 = 4V, and V RB- =-100 / 25=-4V.

[0055] Return to reference Figure 2A And using the definitions mentioned above, during the negative swing of the applied RF voltage, when (X*V RB-When -VB < m*Vth, the diode stack (201) begins to conduct, thus discharging the GIDL current. The parameter X is a ratio defined based on the resistance of the body resistor coupled across the diode stack (201). To further illustrate and as an example, for Figure 2A In the implementation shown, parameter X is defined as X = (R Bn +R Bn+1 ) / R Bn = (R + R / 2) / R = 3 / 2. During the positive oscillation of the applied RF voltage, when (Y*V RB+ When )+VB>k*Vth, the diode stack (202) starts to conduct, where for the diode stack (202), Y is defined similarly to the above case as Y=(R B1 +R B2 ) / R B2 = (R / 2 + R) / R = 3 / 2. During the positive swing of the applied RF signal, the diode stack (201) is in the off state, and the peak voltage Vr1 across each diode in the diode stack (201) can be obtained as Vr1 = ((X*V RB+ )-VB) / m. On the other hand, during the negative swing of the applied RF voltage, the diode stack (202) is in the off state, and the peak voltage Vr2 across each diode in the diode stack (202) can be obtained as Vr2=(-Y*V RB- According to an embodiment of this disclosure, Vr1 and Vr2 are less than the peak voltage reliability limit of the reverse bias diodes within the diode stack (201, 202).

[0056] Figure 2B Some simulation results illustrating the RF current flowing from the RF port to ground as a function of time through a bulk resistor step are shown. Curve (210) represents the case before the teachings of this disclosure are implemented (i.e., without diode stacking). As can be seen, curve (210) is asymmetrical about the time axis (i.e., amplitudes a1 and a2 are not equal). On the other hand, curve (220) represents the case after diode stacking is implemented. As can be noted, the RF current becomes more symmetrical in terms of the behavior of the positive peak relative to the negative peak due to the implementation of diode stacking. Finally, curve (230) shows the difference between curves (210, 220) to highlight the positive effects of implementing diode stacking, thereby mitigating the negative effects of undesirable GIDL current.

[0057] Figure 2C The diagram illustrates the variation of the DC voltage at a node within a bulk resistor ladder relative to the location of such a node within the stack. Curves (260, 270) represent the changes in voltage at a node without and with the teachings of this disclosure (i.e., with and without implementation of this disclosure). Figure 2A This variation occurs in the case of a diode stack (201, 202). As previously mentioned, without implementing the teachings of this disclosure, the DC voltage of each element from top to bottom decreases as a function of its position within the stack. On the other hand, with the diode stack implemented, the element-by-element variation of the DC voltage position is significantly smaller: the curve is flatter, and the voltage distribution is more uniform.

[0058] Figure 3A An exemplary FET switch stack (300A) according to another embodiment of this disclosure is shown, specifically a stack of at least four switches. Although the structure of the FET switch stack (300A) is similar to... Figure 2A There is a similarity in the structure of the FET switch stack (200A), but the bias scheme of the FET switch stack (300A) is different in the sense that the FET switch stack (300A) is operating in positive logic. In other words, in the preferred embodiment, during operation and when the FET switch stack (300A) is in the off state, the bias voltage (VG) is 0V, and the bias voltage (VD) applied to the drain-source resistor step is a positive bias voltage. Furthermore, in Figure 3A In the implementation method, the previously set Figure 2A The capacitors (C1, C2) in the bulk resistor ladder are now represented by (C'1, C'2) and are placed in the drain-source resistor ladder. Similar to... Figure 2A The implementation described herein, aside from the different direction of the current in the drain-source resistor ladder and that it flows from bottom to top, exhibits the same negative impact on the debiased FET switch stack (300A). This difference arises because, in the switch stack FET, when in the off state, the GIDL current flows into the drain terminal of the FET and out of the body terminal. In other words, from the drain-source resistor (R... DS1 Starting from the drain-source resistor (R) DSn The average DC voltage at each node of the drain-source resistor ladder decreases. Figure 3A The diagram also shows a diode stack (301), which differs from the diode stack (201). The diode stack (301) is connected across one or more drain-source resistors in a drain-source resistor ladder. The diode stack (301) includes diodes (D1, ..., D2) connected in series. M It has terminals (A3, K3). In a preferred embodiment, the anode terminal (A3) is connected to the RF port (RF), and the cathode terminal (K3) is connected to a node in the drain-source resistor ladder other than ground.

[0059] Also refer to Figure 2A and Figure 3A The diode stack (301) functions similarly to the diode stack (201) previously described, except that such a diode stack is implemented with opposite polarities due to the fact that the drain is biased at a positive voltage and the current flowing in the drain-source ladder has the opposite direction to the current flowing in the body resistor ladder. Under operating conditions, when the FET switch stack (300A) is off, during the positive swing of the applied RF signal, the diode stack (301) is on (conducting), thereby generating an undesirable GIDL current flowing through the source path of the drain-source resistor ladder via the RF port (RF). During the negative swing of the applied RF signal, the diode stack (301) is off (non-conducting).

[0060] Figure 3B It shows Figure 3A The DC voltage at a node within the drain-source resistor ladder varies relative to the location of such a node within the stack. Curves (320, 330) represent the changes in voltage at a node without implementing the teachings of this disclosure and with implementing the teachings of this disclosure (i.e., with implementing the teachings of this disclosure). Figure 3A This variation occurs in the case of a diode stack (301). As previously mentioned, without implementing the diode stack as described above, the DC voltage is an increasing function of the position within the stack. Also as shown, with the diode stack implemented, the element-by-element variation of the DC voltage position is significantly smaller: the curve is flatter, and the voltage distribution is more uniform.

[0061] Figure 3C An exemplary FET switch stack (300C) according to another embodiment of this disclosure is shown, specifically a stack of at least four switches. The FET switch stack (300C) operates with positive logic, and its operation is similar to that described with respect to the FET switch stack (300A), except that the FET switch stack (300C) also includes a diode stack (302) for cooperating with the diode stack (301) to further overcome the negative effects of GIDL current. Under operating conditions, and when the FET switch stack (300C) is in the off state, during the negative swing of the applied RF signal, the diode stack (302) is turned on and provides a source path for unwanted GIDL current through ground. During the positive swing of the applied RF signal, the diode stack (302) is in the off state. Similar to what has been described previously, the increase in the stack (302) provides more symmetry to the structure, thus providing better overall nonlinear distortion performance.

[0062] exist Figure 2A , Figure 3A , Figure 3CIn the embodiments shown, FET switch stacking is implemented between RF terminals and reference or ground terminals according to a shunt configuration. However, the teachings of this disclosure are equally applicable to scenarios based on a series configuration, i.e., FET switch stacking is implemented between two RF terminals. Figure 4A An embodiment of the FET switch stack (400A) according to this disclosure is shown, particularly a stack of at least four switches. The FET switch stack (400A) is related to... Figure 2A The FET switch stack (200A) is essentially the same, but implemented in a series configuration. The RF signal is input from the RF port (RF1) and output from the RF port (RF2). Given the series configuration of the FET switch stack (400A), and for better symmetry, bias voltages (VG, VB) are applied in the middle of the respective gate and body steps, instead of as... Figure 2A The bias voltage (VG, VB) is applied at the bottom of such a step, as in the FET switch stack (200A). In a preferred embodiment, the bias voltage (VG, VB) can be a negative bias voltage during operation and when the FET switch stack (400A) is in the off state.

[0063] Figure 4B An embodiment of the FET switch stack (400B) according to this disclosure is shown, particularly a stack of at least four switches. The FET switch stack (400B) is related to... Figure 3C The FET switch stack (300C) is essentially the same, but implemented in a series configuration of RF1-RF2. An RF signal is input from the RF port (RF1) and output from the RF port (RF2). Given the series configuration of the FET switch stack (400B), and for better symmetry, bias voltages (VG, VD) are applied in the middle of the corresponding gate and drain-source steps, instead of as... Figure 3C The FET switch stack (300C) is located at the bottom of such a step. In a preferred embodiment, during operation and when the FET switch stack (400B) is in the off state, the bias voltage (VG) is approximately 0V, and the bias voltage (VD) can be a positive bias voltage.

[0064] Figure 5A An exemplary FET switch stack (500A) according to another embodiment of this disclosure is shown. Figure 5A The structure and function of the switch stack (500A) are similar to those of the switch stack (500A). Figure 2A The structure and function of the switch stack (200A) are described below, along with some additional components and functions, which will be described in detail below.

[0065] The FET switch stack (500A) includes diode stacks (501A) and (502A), each of which is coupled across one or more resistors in a body resistor ladder. According to an embodiment of this disclosure, the diode stack (501A) includes one or more diodes (D1, ..., D2) connected in series. M The diode stack (501A) has terminals (A1, K1) and is coupled to a bulk resistor step via these terminals. Connecting the diode (D1) to the resistor (R0) of the bulk resistor step is optional; that is, when the resistor (R0) is not used, the diode (D1) is directly connected to the bulk resistor step. The diode stack (502A) includes one or more diodes (D'1, ..., D') connected in series. N A diode stack (302A) with terminals (A2, K2) is connected to a bulk resistor step via these terminals (A2, K2). The diode (D') is then connected to the step. k The resistor (R0') connected to the body resistor step is optional.

[0066] As noted in the preceding embodiments, the term diode will be used not only to refer to the diode itself, but also to the transistor to which the diode is connected. Continuing to refer to... Figure 5A In this embodiment, the number of series-connected diodes used in the diode stack (501A) can vary, as long as the voltage across the node of each diode in the diode stack (501A) is within the diode's voltage reliability limit when the maximum positive voltage RF signal is applied to the FET switch stack (500A) and the diode stack (501A) is in the off state. A similar consideration applies to the diode stack (502A).

[0067] according to Figure 5A In the embodiment shown, the FET switch stack (500A) also includes a "horizontal" or "ladder" diode (D0) arranged in series with an optional resistor (R1) and a horizontal or ladder diode (D0') arranged in series with an optional resistor (R1'). The series combination of resistor (R1) and diode (D0) is connected at one end to a node (P1) of the body resistor ladder and at the other end to a node (P2) of the "vertical" or "rail" diode stack (501A). The series combination of resistor (R1') and diode (D0') is connected at one end to a node (P3) of the body resistor ladder and at the other end to a node (P4) of the "vertical" or "rail" diode stack (502A).

[0068] During the off-state of the FET switch stack, the presence of the ladder diodes (D0, D0') provides an additional discharge path (513A, 512A) for the GIDL current, besides the discharge path (510A, 511A) provided by the stack of rail diodes (501A, 502A). As will be described in detail later, when the FFT switch stack is off-state, two current discharge paths (510A, 513A) are formed during negative RF signal swings to at least partially carry the unwanted GIDL current. Similarly, during positive RF signal swings, two current discharge paths (511A, 512A) are formed to carry the GIDL current generated during such swings to ground.

[0069] Based on the teachings of this disclosure, Figure 5A The FET switch stack (500A) can be implemented in either a shunt configuration (as shown) or a series configuration (where the bottom terminal is coupled to the RF port instead of the reference voltage). Additionally, continue to refer to... Figure 5A Based on the teachings of this disclosure:

[0070] • Starting from the top to the bottom of the volume resistor step, nodes (P1, P3) can be located at any point within the volume resistor step.

[0071] • Node (P2) can be located at the cathode of diode (D1) at the bottom of the diode stack (501A) and at the cathode of diode (D2) at the top of the diode stack (501A). M At any point between the anodes;

[0072] • Node (P4) can be located at the bottom of the diode (D') in the diode stack (501A). N At any point between the anode of the diode and the cathode of the diode (D'1) at the top of the diode stack (502A);

[0073] Resistor (R) B1 , ..., R Bn+1 Any resistor in the circuit can be split into two or more resistors in series, with their common connection point serving as a tap. Nodes (P1, P3) can also be located at such tap points. As an example, such as Figure 5A As shown, the bulk resistor (R) B2 R B3 The series combination of resistors (T1, T2) is coupled across the body of transistors (T1, T2). In this example, node (P3) is located at the body resistor (R). B2 R B3 )between;

[0074] As noted in the next paragraph, by introducing ladder diodes (and optional associated resistors) in addition to the diodes (D0, D0'), alternative paths to the path (512A, 513A) can be designed.

[0075] Continue to refer to Figure 5A For simplicity and illustrative purposes, only one resistor-diode pair (R1, D0) is shown on the upper part of the FET switch stack (500A), connecting node P1 on the body resistor ladder to the corresponding node (P2) within the diode stack (501A). Similarly, only one resistor-diode pair (R1', D0') is shown on the lower part of the FET switch stack (500A), connecting node P3 on the body resistor ladder to the corresponding node (P4) within the diode stack (502A). However, other implementations are also conceivable, wherein two or more such ladder diodes or ladder diode-resistor combinations couple two or more nodes of the body resistor ladder to the corresponding node of the diode stack (501A), and / or two or more such ladder diodes or ladder diode-resistor combinations couple two or more nodes of the body resistor ladder to the corresponding node of the diode stack (502A). Additional diodes and / or diode-resistor pairs will result in additional current discharge paths, thereby further reducing the negative impact of unwanted GIDL currents.

[0076] To further clarify the concepts disclosed above, refer to Figure 5B It shows Figure 5A This is part of an exemplary implementation of a FET switch stack (500A). For simplicity, only a portion of the FET switch stack is shown. The diode stack (501B) is... Figure 5A An exemplary implementation of the diode stack (501A) is shown, including diodes (D1, ..., D6). A portion of a body resistor ladder including body resistors (RB11, ..., RB15) is also shown. As can be seen in this exemplary embodiment, two resistor-diode pairs (R11, D01) and (R12, D02) couple two corresponding nodes on the resistor body ladder to corresponding nodes within the diode stack (501B).

[0077] Figure 5C An exemplary graph is shown in accordance with the teachings of this disclosure. Curve (550) represents the passage of time. Figure 5A The curve represents the amplitude of the RF signal received by the RF port (RF). It includes positive RF signal swings (left) and negative RF signal swings (right). (Refer to...) Figure 5A , Figure 5B and Figure 5CWhen the FET switch stack (500A) is off and during the first time interval (ΔT1) of the negative swing of the RF signal, the diode stack (501B) is turned on, thereby creating a first discharge path for the GIDL current via resistor (R0), in direction (510B), and through the RF port (RF). Furthermore, during the second time interval (ΔT2), diode (DO2) can be turned on, thereby creating a second additional discharge path for the GIDL via resistor (R12), in direction (514B), and through the RF port (RF). During the third time interval (ΔT3), diode (DO1) can be turned on, thereby creating a third discharge path for the GIDL via resistor (R11), in direction (513B), and through the RF port (RF). In a preferred embodiment, and as... Figure 5C As shown, the first discharge path in direction (510B) is active during time intervals (ΔT1, ΔT2, ΔT3), the second discharge path (514B) is active during time intervals (ΔT2, ΔT3), and the third discharge path (513B) is active during time interval (ΔT3). In other words, in this preferred embodiment, during the negative swing of the RF voltage, the individual diodes are turned on at different times in the following order: the diode stack (501B) will be turned on first, then diode (D02) will be turned on at a later time, and the last diode to be turned on will be diode (D01).

[0078] Similar to the previous Figure 5B As shown in the figure, Figure 5D It shows Figure 5A This is another part of an exemplary implementation of the FET switch stack (500A). For simplicity, only a portion of the FET switch stack is shown. The diode stack (501D) is... Figure 5A An exemplary implementation of a diode stack (501A) is shown, the diode stack (501D) including diodes (D1', ..., D5'). A portion of a body resistor ladder including body resistors (RB11', ..., RB14') is also shown. As can be seen in this exemplary embodiment, two resistor-diode pairs (R11', D01') and (R12', D02') couple two corresponding nodes on the resistor body ladder to corresponding nodes within the diode stack (501D).

[0079] Similar to the previous Figure 5C As shown in the figure, Figure 5E An exemplary graph is shown in accordance with the teachings of this disclosure. Curve (550) represents the passage of time. Figure 5A The amplitude of the RF signal received by the RF port (RF). (Refer to...) Figure 5A , Figure 5D and Figure 5E When the FET switch stack (500A) is off and during the first time interval (ΔT1') of the positive swing of the RF signal, the diode stack (501D) is turned on, thereby creating a first discharge path for the GIDL current via resistor (R0'), in the direction (511D), and through ground. Furthermore, during the second time interval (ΔT2'), diode (D01') can be turned on, thereby creating a second discharge path for the GIDL current via resistor (R11'), in the direction (515D), and through ground. During the third time interval (ΔT3'), diode (D02') can be turned on, thereby creating a third discharge path for the GIDL current via resistor (R12'), in the direction (516D), and through ground. In a preferred embodiment, and as... Figure 5E As shown, the first discharge path in direction (511D) is active during time intervals (ΔT1', ΔT2', ΔT3'), the second discharge path (515D) is active during time intervals (ΔT2', ΔT3'), and the third discharge path (516D) is active during time interval (ΔT3'). In other words, in this preferred embodiment, during the positive swing of the RF voltage, the individual diodes are turned on at different times in the following order: the diode stack (501D) will be turned on first, then diode (D01') will be turned on at a later time, and the last diode to be turned on will be diode (D02'). In the following exemplary embodiments, the conditions that enable this sequence to occur will be discussed in more detail.

[0080] Figure 5F It shows Figure 5A This is part of an exemplary implementation of a FET stack (500A). The minimum RF voltage required at node (A) for the turn-on diode stack (501F) can be calculated as follows:

[0081] V A =6V th

[0082] Among them, V th Let represent the threshold voltage of each of the six diodes (D1, ..., D6), where, for simplicity, the voltage drop introduced due to the presence of (R0) is not considered. The RF voltage (V) at node (A) is given. A If the voltage (V) at node (B) is given, then the voltage (V) at node (B) is given. B It can be calculated as:

[0083]

[0084] However, the minimum voltage required to activate the discharge path (515F), i.e., to turn on the diodes (D0, D1, ..., D4), will be 5V. th This is because there are five diodes (one horizontal and four vertical) in such a discharge path. Based on the above, and... Figure 5C The representation is consistent, the discharge path (511F) will be activated first and before the discharge path (515F), wherein the duration of interval ΔT1 is longer than the duration of interval ΔT2.

[0085] Given the concepts disclosed above, those skilled in the art will recognize that, depending on the application, various design parameters such as the voltage distribution across the bulk resistor step, the number of discharge paths, and the number of diodes used in each path can be adjusted to achieve desired conditions for switching multiple discharge paths to resist unwanted GIDL currents (time and RF amplitude during positive and negative oscillations). This will provide further design flexibility when facing challenging performance requirements.

[0086] As noted in the paragraphs above, each ladder diode may also have its topmost and bottommost diodes in the orbital diode stack coupled to the body ladder via resistors. Such resistors are present for the purpose of limiting current. For example, as... Figure 5C and Figure 5E As shown, there will be time intervals during the positive and negative swings of the RF signal, during which more than one diode path will be turned on. For example, two diode paths will be turned on during interval (ΔT2), and three diode paths will be turned on during interval (ΔT3), with corresponding additional current stress on the track diode stack. The potential presence of resistors such as (R0, R0'), (R1, R1'), (R11, R12), etc., serves the purpose of providing those skilled in the art with a tool to limit the total current for specific implementations and design requirements of the diode paths according to this disclosure.

[0087] Regarding the FET switch stack (500A), an implementation in which only one diode stack (501A, 502A) exists, based on the teachings of this disclosure, is also conceivable. Figure 5G and Figure 5H An example of such an implementation is given in the document.

[0088] Figure 6 An exemplary FET switch stack (600) according to another embodiment of this disclosure is shown. The principle of operation of the FET switch stack (600) is similar to that regarding... Figure 5AAs disclosed in the FET switch (500A), except that the resistor-diode pair (R1, D0) is not connected to the node within the diode stack (601), but is connected through a separate diode (D0). m+1 , ..., D w The series stack of resistors and diodes (R1', D0') couples such a pair to the RF port. Similarly, the resistor-diode pair (R1', D0') is not connected to the node within the diode stack (401), but rather through a separate diode (D'). k+1 , ..., D' q The series stacking of components (601, 602, 610, 611, 612, 613) couples to ground (or the bottom RF port). Figure 5A The counterparts of the components (501A, 502A, 510A, 511A, 512A, 513A). Regarding... Figures 5A to 5H All the teachings described above also apply to Figure 6 The implementation method.

[0089] Figure 7 An exemplary graph (700) illustrating an implementation according to this disclosure is shown, demonstrating the application... Figures 5A to 5H as well as Figure 6 The change in GIDL current relative to the applied RF amplitude before and after the teaching is described in the figure. Curve (710) corresponds to the case of implementing only one discharge path. Figure 2A The FET switch stack (200A) is an example of this situation. On the other hand, curve (720) represents the case where two current discharge paths are achieved by adding a resistor-diode pair that couples a node on the body resistor ladder to a corresponding node within the diode stack. Figure 5A A FET switch stack (500A) is an example of this. As can be seen, by using resistor-diode pairs to add additional discharge paths, the GIDL current is suppressed and becomes relatively flat. The presence of such additional paths has the ability to improve the nonlinear performance of the switch stack and to provide a more balanced voltage distribution across the stack.

[0090] Reference Figure 2A RF switch (200A) and Figure 5A The RF switch (500A), as previously mentioned, has bias voltages (VB, VG) generated by a bias voltage generator circuit, which are not included in the circuit for simplicity. Figure 2A and Figure 5A The circuit for the bias voltage generator is shown above. Figure 8An RF circuit (800) illustrating an RF switch (200A, 500A) is shown, wherein a bias voltage generator circuit (801) is shown as separate from the core of such an RF switch. Throughout this disclosure, the term "body current management" refers to a mechanism that resists unwanted GIDL currents. As an example, see [reference]. Figure 2A The combination of diode stacks (201, 202) provides such a mechanism. As another example, see [reference needed]. Figure 5A Such a mechanism is provided by a combination of resistor-diode pairs (R1, D0), resistors (R0) and diode stacks (501A), resistor-diode pairs (R1', D0'), resistors (R0') and diode stacks (511A). As shown in the RF circuit (800), element (802) represents an RF switch (e.g., receiving a bias voltage (VB, VG) from the bias voltage generator circuit (801). Figure 5A RF switch stack (500A), or Figure 2A The RF switch stack (200A) is also shown in the RF circuit (800). As also shown in the RF circuit (800), the bias voltage generator circuit (801) is also a source of current (Iss), which represents the current supplied by the bias voltage generator circuit (801) due to the undesired GIDL current.

[0091] Also refer to Figure 2A and Figure 5A For RF switches (200A, 500A), as previously mentioned, the more negative the bias voltage (VB) is during the off-state of the RF switch, the better the overall linear performance of such a switch will be. However, the trade-off is that the design of the bias voltage generator circuit (801) becomes more complex, as... Figure 8 As shown in the overall diagram, it occupies more space and consumes more power. On the other hand, a more compact design to implement the bias voltage generator circuit (801) may undesirably lead to decreased nonlinear performance and worse power handling capability of the RF switch.

[0092] An exemplary value for the bias voltage (VB, VG) when the RF switch stack is in the off state is -3V. According to some embodiments of this disclosure, an RF switch is conceivable in which a less negative bias voltage (VB), for example -2V, is provided to the RF switch stack during the off state. In such an embodiment, body current management can be implemented such that, at least when a higher RF signal amplitude is applied, the body bias voltage of the transistors within the FET switch stack is pumped by the RF signal charge to a voltage more negative than the voltage provided by the bias voltage generator circuit (801), for example -2V (e.g., -3V). Therefore, a more compact bias voltage generator circuit (801) with less DC power consumption can be implemented without compromising the nonlinear performance and power handling capability of the RF switch stack. In other words, by implementing the diode-based body current management method disclosed to date as part of the RF switch stack design, a smaller, less complex, and cheaper bias voltage generator circuit can be used without compromising the overall linear performance of the RF switch stack.

[0093] Previously known switch stacks in the off state may require the same body bias voltage and gate bias voltage (i.e., VB = VG). There are several reasons for such an arrangement. First, it is generally easier to design with only one negative supply voltage than multiple negative supply voltages. Second, choosing a more negative value for the bias voltage (VG) will cause the FET to enter the off state more deeply, which in turn leads to improved power handling. Finally, a more negative value for the bias voltage (VB) will lead to improved linearity. Contrary to such general statements, one of the benefits of the teachings disclosed herein is that, by incorporating the body current approach as disclosed in the design of the switch stack, the amount of negative bias voltage required is reduced (relaxed) without affecting power handling requirements. Furthermore, as previously mentioned, such switch stacks benefit from better linearity when a more negative body bias voltage is applied. The teachings of this disclosure make it possible, without having to design with a more negative bias voltage, because the body bias voltage of the transistors within the FET switch stack is pumped by the RF signal charge to a voltage that is more negative than the voltage provided by the bias voltage generator circuitry. Those skilled in the art will recognize that the method according to this disclosure is counterintuitive because it requires separate and distinct processing of the gate bias voltage and body bias voltage under the off-state conditions of the FET switch, and therefore necessitates additional control logic work. On the other hand, the inventors have found that such a counterintuitive method yields the aforementioned advantages and benefits.

[0094] In view of the above, and also referring to Figure 2A and Figure 5A Furthermore, based on the teachings of this disclosure, the following implementation methods can be provided:

[0095] • The bias voltages (VB, VG) are not equal

[0096] The body bias voltage (VB) is less negative than the gate bias voltage (VG).

[0097] The body bias voltage (VB) is at least 1V less negative than the gate bias voltage (VG).

[0098] • The body bias voltage (VB) is adjustable.

[0099] • Adjust the body bias voltage (VB) based on the desired overall nonlinear performance and / or power handling requirements of the FET switch stack.

[0100] ·and Figure 2A Diode stack (201, 202) or Figure 5A The number of diodes in the diode stack (501A, 502A) and / or the position of such diode stacks in their respective RF switch stacks are adjusted accordingly to adjust the body bias voltage (VB).

[0101] Figure 9 A bias voltage generator circuit (900) according to an embodiment of the present disclosure is shown. The bias voltage generator circuit (900) is Figure 8 An exemplary implementation of a bias voltage generator circuit (801) is provided, including a multi-stage charge pump switch block (901), a low-dropout (LDO) voltage converter (902), a resistor divider (903), and an oscillator (904). The multi-stage charge pump switch block (901) includes charge pump switch blocks (SW1, SW2, SW3). The LDO (902) includes an operational transconductance amplifier (905) connected to a transistor (T0). Under operating conditions, different negative voltage levels (V_NEG1, V_NEG2, VSS) are generated at the outputs of the charge pump switches (SW1, SW2, SW3) in descending order (i.e., from less negative to more negative). In other words, V_NEG1 is the least negative bias voltage generated by the circuit, and VSS is the most negative bias voltage generated by the circuit.

[0102] For example Figure 9As shown, a negative voltage (VSS) is fed back to the first input of the OTA (905) through the top of a resistor divider (903). The bottom of the resistor divider (903) receives a reference voltage (VBG), which can be generated, for example, by a bandgap reference voltage circuit (not shown). Based on the difference between the voltage received at its first input and the reference voltage (e.g., ground) at its second input, the OTA (905) generates a signal at its output to control the conductivity of the transistor (T0), thus regulating the voltage (V_LDO) applied to the input of the charge pump switch block (901). The oscillator (904) includes a variable-rate clock for regulating the output current source of the bias voltage generator circuit (900).

[0103] Reference Figure 2A , Figure 5A as well as Figures 8 to 9 According to embodiments of this disclosure, the output bias voltages (V_NEG1, V_NEG2) can be used as the body bias voltage (VB), while the negative voltage (VSS) can be used as the previous bias voltage of this application. Figure 2A , Figure 5A , Figure 5G , Figure 5H and Figure 6 The gate bias voltage (VG) of any circuitry shown in the diagram. Below, some exemplary graphs will be shown to further highlight the benefits of the methods disclosed above, which implement the previously... Figure 2A , Figure 5A , Figure 5G , Figure 5H and Figure 6 The volume current management technology shown in the figure also sets the volume bias voltage to a relatively negative voltage value.

[0104] Also refer to Figure 2A , Figure 5A as well as Figures 8 to 9 , Figure 10 A graph (1000) is shown, comprising two sets of curves (1001, 1002) representing the performance results obtained with and without body current management. Curve (1001) shows the dependence of the power processing FET switch on the body bias voltage (VB) without body current management. An example of this is... Figure 1AThe FET switch stack (100). As can be seen, performance degrades as the body current bias voltage is increased to a less negative value during the off-state of the FET switches, and the FET switches exhibit lower power handling capability. Throughout the document, the term "power handling capability" refers to the maximum power applied to the switch stack in the off-state without causing any switch breakdown, given a configuration (e.g., series or shunt) and RF port impedance termination (e.g., open or 50 ohms). On the other hand, curve (1002) represents the case of implementing body current management according to the teachings of this disclosure. Exemplary FET switch stacks for this case are respectively Figure 2A and Figure 5A The FET switch stacks (200A, 500A) are shown. As can be observed, the power handling capability has been improved after implementing body current management, and more specifically, the dependence of the power handling capability of the RF switch stack in this case on the applied bias voltage (VB) is eliminated (i.e., curve 1002 is relatively flat), thus confirming the fact that the FET switch stack in this case can benefit from the counterintuitive teachings of this disclosure without sacrificing power handling requirements. Each of the curves (1001, 1002) comprises two separate plots, each corresponding to a different switch stack, showing the component-to-component variation.

[0105] Figure 11 A graph (1100) is shown comprising four sets of curves (1101, 1102, 1103, 1104) representing performance results obtained with and without body current management, and with VB being less negative than VSS. Curve (1101) represents an exemplary variation of the body current (Iss) FET switching relative to the RF peak voltage without any body current management, and with the bias voltage VB connected to a voltage, VNEG1, that is less negative than VSS in the bias generator rail. Curve (1102) represents an exemplary variation of the body current (Iss) FET switching relative to the RF peak voltage without any body current management and with the bias voltage VB connected to VSS. Curve (1103) represents the case where body current management is implemented according to the teachings of this disclosure, and the bias voltage VB is connected to a voltage, VNEG1, that is less negative than VSS in the bias generator rail. Curve (1104) represents the case where body current management is implemented according to the teachings of this disclosure, and the bias voltage VB is connected to VSS. As can be observed, for curve (1103), the maximum Iss that the bias generator needs to handle is reduced compared to curves (1101, 1102, 1104), thus reducing the complexity and power consumption requirements of the bias generator.

[0106] Figure 12An exemplary RF circuit (1200) according to an embodiment of this disclosure is shown. The operation of the RF circuit (1200) is similar to that of the one described above, except that a control circuit (1303) is added. Figure 8 The principle of operation described by the RF circuit (800) is as follows. Under operating conditions, when the RF switch (1202) is in the off state, depending on the desired linear performance of the RF switch (1202), the control circuit (1203) can issue a control signal (CTRL) to indicate what level of body bias voltage (VB) needs to be provided to the RF switch (1202) by the bias voltage generator circuit (1201).

[0107] As previously noted, the bias voltage (VB) can be adjusted during the off-state of the RF switch. In particular, as the RF power decreases, it can be useful to adjust the bias voltage (VB) further negatively toward the optimal body voltage target voltage when the diode is not conducting, in order to maintain linearity and good small-signal isolation in the off-state mode. Under such backoff conditions, the body current to be managed is typically small. In such cases, the adjustment (VB) can be achieved through variable or discrete steps. For example, adjustability can be controlled via analog control, a digital control register, or the decoded output of an RF detector that adjusts the voltage in the off-state mode based on the RF power applied to the switch.

[0108] As used in this disclosure, the term "MOSFET" includes any field-effect transistor (FET) having an insulated gate with conductivity of its voltage-determining transistor and includes an insulated gate having a metallic or metalloid, insulator, and / or semiconductor structure. The terms "metal" or "metalloid" include at least one conductive material (e.g., aluminum, copper, or other metals, or heavily doped polycrystalline silicon, graphene, or other conductors), "insulator" includes at least one insulating material (e.g., silicon oxide or other dielectric material), and "semiconductor" includes at least one semiconductor material.

[0109] As used in this disclosure, the term "radio frequency" (RF) refers to an oscillation rate in the range of about 3 kHz to about 300 GHz. The term also includes frequencies used in wireless communication systems. RF frequencies can be the frequencies of electromagnetic waves or the frequencies of alternating voltage or current in a circuit.

[0110] Regarding the accompanying drawings referenced in this disclosure, the dimensions of the various elements are not drawn to scale; for clarity or emphasis, some dimensions have been significantly enlarged vertically and / or horizontally. Furthermore, references to orientation and direction (e.g., “top,” “bottom,” “above,” “below,” “lateral,” “vertical,” “horizontal,” etc.) are relative to the example drawings and are not necessarily absolute orientations or directions.

[0111] Various embodiments of the present invention can be implemented to meet various specifications. Unless otherwise stated above, the selection of suitable component values ​​is a matter of design choice. Various embodiments of the present invention can be implemented using any suitable integrated circuit (IC) technology (including, but not limited to, MOSFET structures) or in hybrid or discrete circuit form. Integrated circuit embodiments can be fabricated using any suitable substrate and process (including, but not limited to, standard bulk silicon, high-resistivity bulk CMOS, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS)). Unless otherwise stated above, embodiments of the present invention can be implemented using other transistor technologies (e.g., bipolar, BiCMOS, LDMOS, BCD, GaAs HBT, GaN HEMT, GaAspHEMT, and MESFET technologies). However, embodiments of the present invention are particularly useful when fabricated using SOI or SOS-based processes, or when fabricated using processes with similar characteristics. Fabrication in CMOS using SOI or SOS processes enables circuits to have low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high-frequency operation (i.e., radio frequency up to and exceeding 300 GHz). Because parasitic capacitance can usually be kept low (or minimal, and kept uniform across all cells, thus allowing for compensation of parasitic capacitance) through careful design, monolithic IC implementations are particularly useful.

[0112] Depending on the specific specifications and / or implementation technology (e.g., NMOS, PMOS, or CMOS, and enhancement-mode or depletion-mode transistor devices), voltage levels and / or voltage and / or logic signal polarity can be adjusted. The voltage, current, and power handling capabilities of components can be adjusted as needed, for example, by adjusting device size, "stacking" components (especially FETs) in series to withstand greater voltages, and / or using multiple components in parallel to handle greater currents. Additional circuit components can be added to enhance the capabilities of the disclosed circuit and / or to provide additional functionality without significantly altering the function of the disclosed circuit.

[0113] The circuits and devices according to the invention can be used alone or in combination with other components, circuits, and devices. Embodiments of the invention can be manufactured as integrated circuits (ICs), which can be packaged in IC packages and / or modules for ease of handling, manufacturing, and / or improved performance. In particular, IC embodiments of the invention are typically used in combination of one or more such ICs with other circuit blocks (e.g., filters, amplifiers, passive components, and possible additional ICs) into a single packaged module. The ICs and / or modules are then typically combined with other components, usually on a printed circuit board, to form part of an end product such as a cellular phone, laptop computer, or tablet computer, or to form a more advanced module that can be used in various products such as vehicles, testing equipment, medical devices, etc. Through various configurations of modules and components, such ICs typically enable communication, usually wireless communication.

[0114] Many embodiments of the invention have been described. It should be understood that various modifications can be made without departing from the spirit and scope of the invention. For example, some of the steps described above may be sequentially independent and can therefore be performed in a different order than that described. Furthermore, some of the steps described above may be optional. The various activities described with respect to the methods identified above can be performed in a repetitive, serial, or parallel manner.

[0115] It should be understood that the foregoing description is intended to illustrate, not limit, the scope of the invention, which is defined by the scope of the appended claims, and other embodiments are also within the scope of the claims. In particular, the scope of the invention includes any and all possible combinations of one or more of the processes, machines, manufactures, or compositions of matter set forth in the appended claims. (Note that the bracket markings used for claim elements are for ease of reference to such elements and do not in themselves indicate a particular desired order or enumeration of elements; furthermore, such markings may be repeated in dependent claims as references to additional elements and are not considered as an inconsistent sequence of markings.)

Claims

1. A field-effect transistor (FET) switch stack, comprising: A series-connected FET, wherein one end of the series-connected FET is coupled to a first terminal and the other end is coupled to a second terminal; The first terminal is configured to receive an input radio frequency (RF) signal; A body resistance ladder, the body resistance ladder being coupled to the first terminal, the body resistance ladder comprising a plurality of body resistors connected in series, each body resistor being coupled to both ends of the body terminal of a corresponding adjacent FET in the series-connected FETs; A first diode stack, comprising one or more diodes, the diode stack having a first cathode terminal connected to the first terminal and a first anode terminal connected to the body terminal of a first FET in the series connection. The FET switch stack is configured such that when the FET switch stack is in the off state, the first anode terminal of the first diode stack and the body terminal of the first FET are at different voltages.

2. The FET switch stack according to claim 1, wherein: In the off state of the FET switch stack, the first diode stack is configured as follows: During the negative RF swing of the RF signal, it is in the on state, generating a discharge path for the gate-induced drain leakage current to pass through the first terminal; and It is in a non-conducting state during the positive RF oscillation of the RF signal.

3. The FET switch stack according to claim 1, wherein, The series-connected FETs are four or more FETs connected in series.

4. The FET switch stack of claim 2, further comprising a second diode stack having a second cathode terminal connected to the second terminal and a second anode terminal connected to the body terminal of the second FET in the series connection.

5. The FET switch stack according to claim 4, wherein, The series-connected FETs are four or more FETs connected in series.

6. The FET switch stack of claim 4, wherein: In the off state of the FET switch stack, the second diode stack is configured as follows: It is in the on state during the positive RF swing of the input RF signal, thereby generating an additional discharge path for the gate-induced drain leakage current through the second terminal; as well as It is in a non-conducting state during the negative RF swing of the input RF signal.

7. The FET switch stack of claim 6, configured to receive a first bias voltage at a gate bias terminal of the FET switch stack and a second bias voltage at a body bias terminal of the FET switch stack, the gate bias terminal being coupled via a resistor to the gate of a bottom FET near the second terminal, and the body bias terminal being coupled to the body of the bottom FET.

8. The FET switch stack according to claim 7, wherein, In the off state of the FET switch stack, the first bias voltage and the second bias voltage are negative bias voltages.

9. The FET switch stack of claim 1, wherein, The volume resistance ladder includes a first capacitor near the first terminal and a second capacitor near the second terminal.

10. The FET switch stack of claim 1, wherein, The second terminal is connected to a reference voltage or ground.

11. The FET switch stack of claim 6, wherein, The second terminal is configured as an output RF port.

12. The FET switch stack of claim 11, configured to receive a first bias voltage at a gate bias terminal and a second bias voltage at a body bias terminal, the gate bias terminal being coupled to the gate of an intermediate FET in the series-connected FETs via a resistor, and the body bias terminal being coupled to the body of the intermediate FET.

13. The FET switch stack of claim 12, wherein, In the off state of the FET switch stack, the first bias voltage and the second bias voltage are negative bias voltages.

14. A field-effect transistor (FET) switch stack, comprising: A series-connected FET, wherein one end of the series-connected FET is coupled to a first terminal and the other end is coupled to a second terminal; The first terminal is configured to receive an input radio frequency (RF) signal; A drain-source resistance ladder, the drain-source resistance ladder being coupled to the first terminal, the drain-source resistance ladder comprising a plurality of drain-source resistors connected in series, each drain-source resistor being coupled to the drain-source terminals of a corresponding adjacent FET in the series-connected FETs; A first diode stack, comprising one or more diodes, the diode stack having a first anode terminal connected to the first terminal and a first cathode terminal connected to the source terminal of the first FET in the series connection.

15. The FET switch stack of claim 14, wherein: In the off state of the FET switch stack, the first diode stack is configured as follows: During the positive RF swing of the input RF signal, it is in the ON state, generating a source path for gate-induced drain leakage current through the first terminal; and It is in a non-conducting state during the negative RF swing of the input RF signal.

16. The FET switch stack of claim 14, wherein, The series-connected FETs are four or more FETs connected in series.

17. The FET switch stack of claim 15, further comprising a second diode stack having a second anode terminal connected to the second terminal and a second cathode terminal connected to the drain terminal of the second FET in the series connection.

18. The FET switch stack of claim 17, wherein, The series-connected FETs are four or more FETs connected in series.

19. The FET switch stack of claim 17, wherein: In the off state of the FET switch stack, the second diode stack is configured as follows: It is in the on state during the negative RF swing of the input RF signal, thereby generating an additional source path for the gate-induced drain leakage current through the second terminal; as well as It is in a non-conducting state during the positive RF swing of the input RF signal.

20. The FET switch stack of claim 19, configured to receive a first bias voltage at a gate bias terminal and a second bias voltage at a drain bias terminal, the gate bias terminal being coupled via a resistor to the gate of a bottom FET near the second terminal, and the drain bias terminal being coupled to the drain terminal of the bottom FET.

21. The FET switch stack of claim 20, wherein, In the off state of the FET switch stack, the first bias voltage is at zero volts, and the second bias voltage is a positive bias voltage.

22. The FET switch stack of claim 14, wherein, The drain-source resistance ladder includes a first capacitor near the first terminal and a second capacitor near the second terminal.

23. The FET switch stack of claim 21, wherein, The second terminal is connected to a reference voltage or ground.

24. The FET switch stack of claim 19, wherein, The second terminal is configured as an output RF port.

25. The FET switch stack of claim 24, configured to receive a first bias voltage at a gate bias terminal and a second bias voltage at a drain bias terminal, the gate bias terminal being coupled to the gate of an intermediate FET in the series-connected FETs via a resistor, and the drain bias terminal being coupled to the drain terminal of the intermediate FET.

26. The FET switch stack of claim 25, wherein, In the off state of the FET switch stack, the first bias voltage is zero volts, and the second bias voltage is a positive bias voltage.

27. An RF module comprising the FET switch stack of claim 1.

28. A communication device comprising a FET switch stack according to claim 1.

29. A field-effect transistor (FET) switch stack, comprising: A series-connected FET, wherein one end of the series-connected FET is coupled to a first terminal and the other end is coupled to a second terminal, the first terminal being configured to receive an input radio frequency (RF) signal; A body resistor step, the body resistor step being coupled to the first terminal, the body resistor step comprising a plurality of body resistor elements connected in series, each body resistor element being coupled to both ends of the body terminal of a corresponding adjacent FET in the series-connected FETs; as well as A body current management circuit, wherein the body current management circuit is coupled to the body resistor step. in, The FET switch stack is configured to receive a first bias voltage at the gate bias terminal of the FET switch stack and a second bias voltage at the body bias terminal of the FET switch stack. In the off state of the FET switch stack, the first bias voltage and the second bias voltage are negative bias voltages; In the off state, the second bias voltage is less negative than the first bias voltage, and The body current management circuit is configured to provide one or more current discharge paths for gate-sensing drain leakage current.

30. The FET switch stack of claim 29, wherein, The body current management circuit includes a first diode arrangement, the first diode arrangement comprising: A diode stack comprising two or more diodes coupled between the body resistor step and the first terminal, the diode stack being configured to provide a first current discharge path among the one or more current discharge paths during the off-state of the FET switch stack.

31. The FET switch stack of claim 30, wherein, The diode stack is configured to be in the on state and to provide a first current discharge path during a first time portion of the positive or negative oscillation of the RF signal when the FET switch stack is in the off state.

32. The FET switch stack of claim 31, wherein, The first diode arrangement further includes: One or more additional diodes coupled to the body resistor ladder, the one or more additional diodes being configured to provide at least a second current discharge path among the one or more current discharge paths during the off state of the FET switch stack.

33. The FET switch stack of claim 32, wherein, The one or more additional diodes are configured to be in the on state and to provide the at least second current discharge path during at least a second time portion of the positive or negative oscillation of the RF signal in the off state of the FET switch stack.

34. The FET switch stack of claim 33, wherein, The at least second time portion is within the first time portion.

35. The FET switch stack of claim 32, wherein, The diode stack and at least one of the one or more additional diodes are coupled to the body resistor ladder via at least one coupling resistor, which acts as a current-limiting resistor during the positive or negative oscillation portion of the RF signal when the first current discharge path and the at least second current discharge path are provided in combination.

36. The FET switch stack of claim 35, wherein, Both the diode stack and the one or more additional diodes are coupled to the bulk resistor ladder via corresponding coupling resistors.

37. The FET switch stack of claim 32, wherein, The diode stack and the one or more additional diodes are coupled to the body resistor step at different taps of the body resistor step.

38. The FET switch stack of claim 32, wherein, The diode stack and the one or more additional diodes are configured to, during the positive or negative oscillation of the RF signal in the off state of the FET switch stack, i) begin providing the first current discharge path before providing the at least second current discharge path, and ii) stop providing the first current discharge path after stopping providing the at least second current discharge path.

39. The FET switch stack of claim 32, wherein, The one or more additional diodes are configured to combine with a subset of the diodes in the diode stack to provide the at least second current discharge path, whereby the at least second current discharge path partially overlaps with the first current discharge path.

40. The FET switch stack of claim 32, wherein, The one or more additional diodes are configured to provide the at least second current discharge path without being combined with a subset of diodes in a diode stack, thereby separating the at least second current discharge path from the first current discharge path.

41. The FET switch stack of claim 30, further comprising a second diode arrangement having a corresponding diode stack, wherein, The first diode stack is configured to be in a conducting state and, in the off state of the FET switch stack, provides the first current discharge path during the first time portion of the positive swing of the RF signal. The diode stack of the second diode arrangement is configured to be in the on state and to provide the first current discharge path during the first time portion of the negative swing of the RF signal in the off state of the FET switch stack.

42. The FET switch stack of claim 41, wherein: The first diode arrangement further includes: One or more additional diodes coupled to the body resistor step, the additional diodes being configured to provide at least a second current discharge path during a second time portion of the positive oscillation of the RF signal in the off state of the FET switch stack; and The second diode arrangement also includes: One or more additional diodes coupled to the body resistor ladder, the one or more additional diodes being configured to provide at least a second current discharge path during a second time portion of the negative swing of the RF signal in the off state of the FET switch stack.

43. The FET switch stack of claim 29, wherein, In the off state, the second bias voltage is less negative than the set body bias voltage corresponding to the set nonlinear performance and power handling capability of the FET switch stack.

44. The FET switch stack of claim 43, wherein, The bias voltage of the body terminal of each FET is pulled toward the set body bias voltage.

45. The FET switch stack of claim 43, wherein, The second bias voltage is at least 1V less negative than the set body bias voltage.

46. ​​The FET switch stack of claim 43, wherein, The first bias voltage is the same as the set body bias voltage.

47. The FET switch stack of claim 43, wherein, The second bias voltage is adjustable in the off state of the FET switch stack.

48. The FET switch stack of claim 47, wherein, The second bias voltage is adjustable if the body current management circuit does not provide one or more current discharge paths.

49. The FET switch stack of claim 35, wherein, When the first current discharge path and the at least second current discharge path are provided through the same diode, the coupling resistor is used as a current-limiting resistor during the positive or negative swing portion of the RF signal.

50. A circuit arrangement, comprising: The FET switch stack according to claim 29; and A bias voltage generator circuit is configured to generate the first bias voltage and the second bias voltage at least during the off-state of the FET switch stack.

51. The circuit arrangement according to claim 50, wherein, The bias voltage generator circuit includes a multi-stage charge pump switch block configured to generate two or more different negative voltage levels.

52. The circuit arrangement according to claim 51, wherein, The first negative voltage level among the two or more different negative voltage levels is the first bias voltage, and the second negative voltage level among the two or more different negative voltage levels is the second bias voltage.

53. A method for biasing a stack of radio frequency (RF) field-effect transistor (FET) switches in an off-state, the RF FET switch stack comprising FETs connected in series and coupled at one end to a first terminal and at the other end to a second terminal, the first terminal being configured to receive an input radio frequency (RF) signal, the method comprising: A negative gate bias voltage is applied to the gate terminal of the series-connected FET; A negative body bias voltage is applied to the body terminal of the series-connected FET, the body bias voltage being less negative than the gate bias voltage; An RF signal is applied across the RF FET switch stack in the off state. as well as When the RF signal is applied, the gate-induced drain leakage current is discharged through one or more current discharge paths, and the discharge pulls down the voltage at the body terminal of the series-connected FET to a voltage much more negative than the body bias.

54. The method according to claim 53, wherein, The one or more current discharge paths are multiple current discharge paths.

55. The method according to claim 54, wherein, The first current discharge path of the plurality of current discharge paths is generated by a diode stack coupled to the RF FET switch stack, and the second current discharge path of the plurality of current discharge paths is generated by one or more additional diodes.

56. The method of claim 53, further comprising adjusting the negative body bias voltage to provide a different negative bias to the body terminal.

57. A field-effect transistor (FET) switch stack, comprising: A series-connected FET, wherein one end of the series-connected FET is coupled to a first terminal and the other end is coupled to a second terminal, the first terminal being configured to receive radio frequency (RF) signals; A body resistor step, the body resistor step being coupled to the first terminal, the body resistor step comprising a plurality of body resistor elements connected in series, each body resistor element being coupled to both ends of the body terminal of a corresponding adjacent FET in the series-connected FETs; as well as The first diode element arrangement includes: i) A diode element stack comprising two or more diode elements, the diode element stack being coupled between the bulk resistor step and the first terminal, and ii) One or more additional diode elements coupled to the body resistor step.

58. The FET switch stack of claim 57, wherein, The diode element stack is configured to provide a first gate-induced drain leakage current discharge path during the off-state of the FET switch stack.

59. The FET switch stack of claim 58, wherein, The one or more additional diode elements are configured to provide at least a second gate-induced drain leakage current discharge path during the off-state of the FET switch stack.

60. The FET switch stack of claim 59, wherein, The diode element stack and the one or more additional diode elements are configured to be in an on state, and in the off state of the FET switch stack, the first gate-induced drain leakage current discharge path and the at least second gate-induced drain leakage current discharge path are provided in combination during the positive or negative swing portion of the RF signal.

61. The FET switch stack of claim 59, wherein, At least one of the two or more diode elements in the diode element stack is coupled to the bulk resistor ladder via at least one coupling resistor.

62. The FET switch stack of claim 61, wherein, When the first gate-induced drain leakage current discharge path and the at least second gate-induced drain leakage current discharge path are provided in combination, the coupling resistor functions as a current-limiting resistor during the positive or negative swing portion of the RF signal.

63. The FET switch stack of claim 62, wherein, Both the stack of diode elements and the one or more additional diode elements are coupled to the bulk resistor ladder via corresponding coupling resistors.

64. The FET switch stack of claim 57, wherein, The diode element stack and the one or more additional diode elements are coupled to the body resistor step at different taps of the body resistor step.

65. The FET switch stack of claim 62, wherein, The diode element stack, the one or more additional diode elements, and the at least one coupling resistor are configured to, during the positive or negative oscillation of the RF signal in the off state of the FET switch stack, i) begin providing the first gate-induced drain leakage current discharge path before providing the at least second gate-induced drain leakage current discharge path, and ii) stop providing the first gate-induced drain leakage current discharge path after stopping providing the at least second gate-induced drain leakage current discharge path.

66. The FET switch stack of claim 62, wherein, The one or more additional diode elements are configured to combine with a subset of the diode elements stacked with the diode elements to provide the at least second gate-induced drain leakage current discharge path, whereby the second gate-induced drain leakage current discharge path partially overlaps with the first gate-induced drain leakage current discharge path.

67. The FET switch stack of claim 62, wherein, The one or more additional diode elements are configured to provide the at least second gate-induced drain leakage current discharge path without being combined with a subset of diode elements stacked with the diode elements, whereby the second gate-induced drain leakage current discharge path is separate from the first gate-induced drain leakage current discharge path.

68. The FET switch stack of claim 62, further comprising a second diode element arrangement having a corresponding diode element stack and one or more additional diode elements, wherein, The diode element stack of the first diode element arrangement and one or more additional diode elements are configured to combine the first gate-induced drain leakage current discharge path and the at least second gate-induced drain leakage current discharge path during the positive swing portion of the RF signal in the off state of the FET switch stack, and The diode element stack of the second diode element arrangement and one or more additional diode elements are configured to be in the on state, and in the off state of the FET switch stack, the first gate-induced drain leakage current discharge path and the at least second gate-induced drain leakage current discharge path are combined during the negative swing portion of the RF signal.

69. The FET switch stack of claim 57, configured to receive a first bias voltage at a gate bias terminal of the FET switch stack and a second bias voltage at a body bias terminal of the FET switch stack.

70. The FET switch stack of claim 69, wherein, In the off state of the FET switch stack, the first bias voltage and the second bias voltage are negative bias voltages.

71. The FET switch stack of claim 57, wherein, The second terminal is configured to be coupled to a reference voltage or ground.

72. The FET switch stack of claim 57, wherein, The second terminal is configured to be coupled to an RF signal.

73. The FET switch stack of claim 57, wherein, The diode element stack and at least one of the one or more diode elements include a diode-connected transistor or diode.

74. The FET switch stack of claim 57, further comprising a first capacitor coupling the series-connected FETs to the first terminal and a second capacitor coupling the series-connected FETs to the second terminal.

75. A method for controlling gate-induced drain leakage current in the off state of an RF switch stack, the RF switch stack including i) a series-connected FET configured to receive an RF signal and ii) a body resistor ladder coupled to the body terminal of the series-connected FET, the method comprising: The RF signal is applied to the RF switch stack; In the off state of the RF switch stack, a first current discharge path is generated during the first time interval for the gate-sensed drain leakage current to pass through the body resistor step. as well as In the off state of the RF switch stack, a second current discharge path is generated during the second time interval for the gate-sensed drain leakage current to pass through the body resistor step. During the first overlapping time interval when the RF switch that generates both the first current discharge path and the second current discharge path is in the off state, the second time interval partially overlaps with the first time interval in time.

76. The method according to claim 75, wherein, The first current discharge path is generated by a diode stack coupled to the RF switch stack and the body resistor ladder, and the second current discharge path is generated by coupling one or more diodes attached to the diode stack to the RF switch stack and the body resistor ladder.

77. The method according to claim 76, wherein, The diode stack and the one or more diodes are coupled to the bulk resistor step at different taps of the bulk resistor step.

78. The method of claim 75, further comprising: In the off state of the RF switch stack, a third current discharge path is generated during the third time interval for the gate-sensed drain leakage current to pass through the body resistor step. During the second overlapping time interval of the RF switch in the off state that generates the first current discharge path, the second current discharge path and the third current discharge path, the third time interval partially overlaps with the first time interval and the second time interval in time.

79. A field-effect transistor (FET) switch stack, comprising: A series-connected FET, wherein one end of the series-connected FET is coupled to a first terminal and the other end is coupled to a second terminal, the first terminal being configured to receive radio frequency (RF) signals; A body resistor step, the body resistor step being coupled to the first terminal, the body resistor step comprising a plurality of body resistor elements connected in series, each body resistor element being coupled to both ends of the body terminal of a corresponding adjacent FET in the series-connected FETs; as well as The first diode element arrangement includes: i) A diode element stack coupled between a first tap of the bulk resistor step and the first terminal, the diode element stack comprising a first diode element and a second diode element connected in series, wherein the cathode of the first diode element is connected to the anode of the second diode element, and ii) A third diode element coupled between the second tap of the body resistor step and the anode of the second diode element, the third diode element having a cathode coupled to the cathode of the first diode element and the anode of the second diode element.

80. The FET switch stack of claim 79, wherein, The diode element stack is configured to provide a first gate-induced drain leakage current discharge path during the off-state of the FET switch stack.

81. The FET switch stack of claim 80, wherein, The third diode element is configured to provide at least a second gate-induced drain leakage current discharge path during the off-state of the FET switch stack.

82. The FET switch stack of claim 81, wherein, The diode element stack and the third diode element are configured to be in an on state, and in the off state of the FET switch stack, the first gate-induced drain leakage current discharge path and the at least second gate-induced drain leakage current discharge path are combined during the positive or negative swing portion of the RF signal.

83. The FET switch stack of claim 81, wherein, At least one of the first diode element or the second diode element in the diode element stack is coupled to the bulk resistor ladder via at least one coupling resistor.

84. The FET switch stack of claim 83, wherein, When the first gate-induced drain leakage current discharge path and the at least second gate-induced drain leakage current discharge path are provided in combination, the coupling resistor functions as a current-limiting resistor during the positive or negative swing portion of the RF signal.

85. The FET switch stack of claim 84, wherein, The diode element stack and the third diode element are coupled to the bulk resistor ladder via corresponding coupling resistors.

86. The FET switch stack of claim 79, wherein, The stack of diode elements, as well as the first and second diode elements, are coupled to the bulk resistor step at different tap points of the bulk resistor step.

87. The FET switch stack of claim 84, wherein, The diode element stack, the third diode element, and the at least one coupling resistor are configured to, during the positive or negative oscillation of the RF signal in the off state of the FET switch stack, i) begin providing the first gate-induced drain leakage current discharge path before providing the at least second gate-induced drain leakage current discharge path, and ii) stop providing the first gate-induced drain leakage current discharge path after stopping providing the at least second gate-induced drain leakage current discharge path.

88. The FET switch stack of claim 84, wherein, The third diode element is configured to provide the at least second gate-induced drain leakage current discharge path in combination with a subset of diode elements stacked with the diode element, whereby the second gate-induced drain leakage current discharge path partially overlaps with the first gate-induced drain leakage current discharge path.

89. The FET switch stack of claim 84, wherein, The third diode element is configured to provide the at least second gate-induced drain leakage current discharge path without being combined with a subset of diode elements stacked with the diode element, thereby separating the second gate-induced drain leakage current discharge path from the first gate-induced drain leakage current discharge path.

90. The FET switch stack of claim 84, further comprising a second diode element arrangement having a corresponding diode element stack and a fourth diode element, wherein, The first diode element stack and the third diode element are configured to combine the first gate-induced drain leakage current discharge path and the at least second gate-induced drain leakage current discharge path during the positive swing portion of the RF signal in the off state of the FET switch stack. The fourth diode element is configured to be in the on state and, in the off state of the FET switch stack, to provide the first gate-induced drain leakage current discharge path and the at least second gate-induced drain leakage current discharge path in combination during the negative swing portion of the RF signal.

91. The FET switch stack of claim 79, configured to receive a first bias voltage at a gate bias terminal of the FET switch stack and a second bias voltage at a body bias terminal of the FET switch stack.

92. The FET switch stack of claim 91, wherein, In the off state of the FET switch stack, the first bias voltage and the second bias voltage are negative bias voltages.

93. The FET switch stack of claim 79, wherein, The second terminal is configured to be coupled to a reference voltage or ground.

94. The FET switch stack of claim 79, wherein, The second terminal is configured to be coupled to an RF signal.

95. The FET switch stack of claim 79, wherein, At least one of the diode element stack and the third diode element includes a diode-connected transistor or diode.

96. The FET switch stack of claim 79, further comprising a first capacitor that steps the body resistor to the first terminal and a second capacitor that steps the body resistor to the second terminal.

97. The FET switch stack of claim 79, wherein, One or more individual resistor elements of the volume resistor ladder are connected in series between the first tap and the second tap.

98. A method for controlling gate-induced drain leakage current in the off state of an RF switch stack, the RF switch stack comprising: i) A series-connected FET configured to receive RF signals; ii) A body resistor step coupled to the body terminal of the series-connected FET; iii) a stack of diode elements coupled between a first tap and a first terminal of the body resistor step, the stack comprising a first diode element and a second diode element connected in series, wherein the cathode of the first diode element is connected to the anode of the second diode element; and iv) a third diode element coupled between a second tap and the anode of the second diode element of the body resistor step, the third diode element having a cathode coupled to the cathode of the first diode element and the anode of the second diode element; the method comprising: The RF signal is applied to the RF switch stack; In the off state of the RF switch stack, a first current discharge path is generated during a first time interval for the gate-sensed drain leakage current to pass through the body resistor step; and In the off state of the RF switch stack, a second current discharge path is generated during the second time interval for the gate-sensed drain leakage current to pass through the body resistor step. in, During the first overlapping time interval of the RF switch in the off state that generates both the first and second current discharge paths, the second time interval partially overlaps with the first time interval in time; and The first current discharge path is generated through the stack of diode elements, and the second current discharge path is generated through the third diode element.

99. The method according to claim 98, wherein, The diode element stack and the third diode element are coupled to the body resistor step at different tap points of the body resistor step.

100. The method of claim 98, further comprising: In the off state of the RF switch stack, a third current discharge path is generated during the third time interval for the gate-sensed drain leakage current to pass through the body resistor step. During the second overlapping time interval of the RF switch in the off state that generates the first current discharge path, the second current discharge path and the third current discharge path, the third time interval partially overlaps with the first time interval and the second time interval in time.

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