A chip testing system

Abstract

The application provides a chip test system, comprising: a programmable logic device; the programmable logic device comprises: a universal bus conversion module, a universal bus interconnection module and a universal bus decoding module, the universal bus conversion module is used for realizing bus conversion of a chip test program loading interface and a universal bus master interface, and the chip test program loading interface is used for loading a chip test program. The universal bus interconnection module is used for realizing interconnection of the universal bus master interface and a plurality of universal bus slave interfaces. The universal bus first slave interface is connected with the universal bus decoding module, and the universal bus decoding module is used for connecting a plurality of interface bus modules. At least one universal bus second slave interface is connected with each logic module of a chip under test respectively, and is used for testing each logic module of the chip under test. Therefore, the interaction between the plurality of interface bus modules and each logic module of the chip under test can be realized, the switching between different modes can be realized, and the universality is improved, so that the demand of different scenes can be adapted.

Description

Technical Field

[0001] This application relates to the field of chip testing, and in particular to a chip testing system. Background Technology

[0002] Logic engineers often need to perform feasibility verification work in the early stages of a project, such as verifying whether a certain analog-to-digital converter (ADC) chip meets the requirements of the project application. During verification, it is necessary to conduct communication between the internal modules of the chip and the external environment, as well as communication between the various modules within the chip. However, at present, different test platforms need to be built for different bus interfaces, which is not universal, has low testing efficiency, and high cost. Summary of the Invention

[0003] In view of this, the purpose of this application is to provide a chip testing system that is universal and can adapt to the needs of different scenarios.

[0004] To achieve the above objectives, this application provides the following technical solution:

[0005] In a first aspect, embodiments of this application provide a chip testing system, including a programmable logic device; the programmable logic device includes: a general-purpose bus conversion module, a general-purpose bus interconnect module, and a general-purpose bus decoding module;

[0006] One end of the universal bus conversion module is connected to the chip test program loading interface, and the other end is connected to the universal bus main interface, which is used to realize the bus conversion between the chip test program loading interface and the universal bus main interface; the chip test program loading interface is used to load the chip test program;

[0007] One end of the universal bus interconnect module is connected to the universal bus master interface, and the other end is connected to the universal bus first slave interface and at least one universal bus second slave interface, respectively, to realize the interconnection between the universal bus master interface and multiple universal bus slave interfaces;

[0008] The first slave interface of the general-purpose bus is connected to the general-purpose bus decoding module; the general-purpose bus decoding module is used to connect to multiple interface bus modules;

[0009] The at least one general-purpose bus second slave interface is connected to each logic module of the chip under test, and is used to test each logic module of the chip under test.

[0010] In one possible implementation, the system further includes: input / output buffers with multiple level formats;

[0011] One end of the multi-level format input / output buffer is connected to the programmable logic device; the other end of the multi-level format input / output buffer is connected to the electrical interface of an external device, for converting the multi-level format into the level format of the programmable logic device.

[0012] In one possible implementation, the chip test program includes: a tool command language TCL script program.

[0013] In one possible implementation, the universal bus conversion module includes:

[0014] Joint test workgroup interface to advanced extensible interface JTAG to AXI module, or MicroBlaze soft core.

[0015] In one possible implementation, when the general-purpose bus conversion module is the MicroBlaze soft core, the chip test program is a C program.

[0016] In one possible implementation, the programmable logic device includes a field-programmable gate array (FPGA).

[0017] In one possible implementation, the general-purpose bus interconnect module includes an advanced scalable interface interconnect (AXIInterconnect) module.

[0018] In one possible implementation, the general-purpose bus decoding module includes: an advanced extensible interface decoding AXIdecoder module.

[0019] In one possible implementation, the multiple interface bus modules include: a Serial Peripheral Interface (SPI) module, and an internal integrated circuit (I). 2 At least two of the following: C module, general purpose input / output (GPIO) module, general purpose asynchronous transceiver (UART) module, and pulse (PULSE) module.

[0020] In one possible implementation, the multiple level formats include at least two of the following: 5V transistor logic level TTL, 3.3V low-voltage transistor logic level LVTTL, 2.5V low-voltage transistor logic level LVTTL, 1.8V low-voltage transistor logic level LVTTL, low-voltage differential signal LVDS, and asynchronous transmission standard interface RS232 standard level.

[0021] This application provides a chip testing system, including a programmable logic device (PLD). The PLD includes a universal bus conversion module, a universal bus interconnect module, and a universal bus decoding module. The universal bus conversion module converts the chip test program loading interface to a universal bus master interface, and the chip test program loading interface loads the chip test program. The universal bus interconnect module interconnects the universal bus master interface with multiple universal bus slave interfaces. A first universal bus slave interface connects to the universal bus decoding module, which connects to various interface bus modules. At least one second universal bus slave interface connects to each logic module of the chip under test (DUT) for testing each logic module. This allows for interaction between various interface bus modules and the logic modules of the DUT, enabling switching between different modes, thus improving versatility and adapting to different scenarios. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 A schematic diagram of a chip testing system provided in an embodiment of this application is shown;

[0024] Figure 2 A schematic diagram of another chip testing system provided in an embodiment of this application is shown. Detailed Implementation

[0025] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0026] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0027] As described in the background section, logic engineers often need to perform feasibility verification work in the early stages of a project. For example, they may need to verify whether a certain analog-to-digital converter (ADC) chip meets the requirements of the project application. During verification, it is necessary to verify the communication between the internal modules of the chip and the external environment, as well as the communication between the various modules within the chip. However, at present, different test platforms need to be built for different bus interfaces, which is not universal, has low testing efficiency, and high cost.

[0028] Specifically, there are currently three main ways to build a testing platform:

[0029] (1) For general-purpose buses such as the asynchronous transmission standard interface RS232 or general-purpose input / output (GPIO), the corresponding functions can be implemented using a bus interface card. However, this method cannot communicate with the logic modules of the chip under test in the programmable logic device. At the same time, this method can only control the interface through the application programming interface (API) function provided by the bus interface card, which is less flexible.

[0030] (2) For applications requiring a serial peripheral interface (SPI) or internal integrated circuit (I) 2 In C++, for inter-integrated circuit (IUT) interface debugging and testing applications, specific logic function modules of the chip under test (DUT) can be written using hardware description languages ​​such as Verilog or Very-High-Speed ​​Integrated Circuit Hardware Description Language (VHDL) to achieve communication with external systems. This approach offers high flexibility, enabling data interaction between the DUT's logic function modules within a programmable logic device. However, these logic function modules are only applicable to specific scenarios, lacking versatility and code reusability. Furthermore, due to the low abstraction level of hardware description languages ​​like Verilog / VHDL, development efficiency is low, making them unsuitable for applications with complex testing functions. Developing these debugging modules also consumes excessive time and effort from developers, extending the project development cycle.

[0031] (3) For test stimuli such as external pulses, square waves, or high and low level signals, standard signal sources can be used. Standard signal source devices generally provide external interfaces such as USB or RS232, which can be used to program and control the output of the signal source to achieve test automation. However, this method also cannot communicate with the function under test module inside the programmable logic device; it also has drawbacks such as poor flexibility and high cost.

[0032] To address the aforementioned technical issues, this application provides a chip testing system, comprising: a programmable logic device; the programmable logic device includes: a general-purpose bus conversion module, a general-purpose bus interconnect module, and a general-purpose bus decoding module. The general-purpose bus conversion module is used to convert the chip test program loading interface to a general-purpose bus master interface, and the chip test program loading interface is used to load the chip test program. The general-purpose bus interconnect module is used to interconnect the general-purpose bus master interface with multiple general-purpose bus slave interfaces. A first general-purpose bus slave interface is connected to the general-purpose bus decoding module, which is used to connect multiple interface bus modules. At least one second general-purpose bus slave interface is connected to each logic module of the chip under test, for testing each logic module of the chip under test. This enables interaction between multiple interface bus modules and the logic modules of the chip under test, allowing switching between different modes, thereby improving versatility and adapting to the needs of different scenarios.

[0033] To better understand the technical solution and effects of this application, the specific embodiments will be described in detail below with reference to the accompanying drawings.

[0034] See Figure 1 As shown in the figure, this figure is a schematic diagram of a chip testing system provided in an embodiment of this application.

[0035] In this embodiment of the application, a test program needs to be loaded to test each logic module 17 of the chip under test. The chip test program can be loaded into the programmable logic device 1 through the chip test program loading interface 10 of the programmable logic device 1 for subsequent use.

[0036] Specifically, the chip test program loading interface 10 can be connected to a computer. The chip test program loading interface 10 can be a Joint Test Action Group (JTAG) interface. JTAG is an international standard test protocol primarily used for internal chip testing. The JTAG interface connects to the computer via an emulator, allowing chip test programs to be loaded from the computer.

[0037] Chip test programs can be tool command language (TCL) script programs. Using TCL script programs, more complex and higher-level test processes can be completed, including completing test stimuli, reading the current state of the logic module of the chip under test, and recording test results. This can improve testing and development efficiency. At the same time, TCL script programs can also easily call mature library functions of other languages. As a glue language, it can also easily glue different functional modules together to complete automated testing and improve testing efficiency.

[0038] The programmable logic device 1 provided in this application includes: a general-purpose bus conversion module 11, a general-purpose bus interconnect module 13, and a general-purpose bus decoding module 15.

[0039] Since the bus formats of the chip test program loading interface 10 and the general bus master interface 12 are inconsistent, a general bus conversion module 11 is needed. One end of the module is connected to the chip test program loading interface 10, and the other end is connected to the general bus master interface 12, which can realize the bus conversion between the chip test program loading interface 10 and the general bus master interface 12.

[0040] Specifically, the general-purpose bus main interface 12 can be an advanced extensible interface (AXI) main interface. Since the AXI bus is a highly versatile interface bus, it is an on-chip bus designed for high performance, high bandwidth, and low latency. It can interact with various interface bus modules and various logic modules of the chip under test. Therefore, the general-purpose bus conversion module 11 can be a Joint Test Action Group to advanced extensible interface (JTAG to AXI) module. The JTAG to AXI module is a user-customizable intellectual property (IP) core, which is a pre-designed circuit function module that can perform AXI transmission within the programmable device, drive AXI signals, and realize bus conversion from JTAG interface to AXI interface.

[0041] In an alternative implementation, the general-purpose bus conversion module 11 can also be Xilinx's soft core MicroBlaze. In this case, the chip test program is a C program. Running the C program in the soft core can also perform the same functions as the TCL script program. However, the disadvantage of doing so is that the software program can only use the C standard library supported by MicroBlaze to complete the corresponding test functions. TCL, as a scripting language, can easily call mature library functions of multiple languages, which is significantly better than C language in terms of development efficiency.

[0042] After the bus conversion is completed, in order to enable more modules to be connected to the universal bus, the universal bus interconnect module 13 can be used to interconnect the universal bus master interface 12 with multiple universal bus slave interfaces. Specifically, one end of the universal bus interconnect module 13 can be connected to the universal bus master interface 12, and the other end can be connected to the universal bus first slave interface 14 and at least one universal bus second slave interface 16 respectively. In one possible implementation, the universal bus second slave interface 16 can include two: universal bus second slave interface 161 and universal bus second slave interface 162, to connect different chip under test logic modules 17. Depending on the function, the chip under test logic modules can include chip under test logic module 171, chip under test logic module 172, etc.

[0043] In one possible implementation, the general-purpose bus slave interface can be an Advanced Extensible Interface (AXI) slave interface, and the general-purpose bus interconnect module 13 can be an AXI Interconnect module, which is a Xilinx built-in IP core that can realize the interconnection of one AXI master interface with multiple AXI slave interfaces.

[0044] The first slave interface 14 of the general bus can be connected to the general bus decoding module 15. The general bus decoding module 15 is used to connect to various interface bus modules 18. Depending on the type of interface, the interface bus module 18 may include interface bus module 181, interface bus module 182, etc.

[0045] Optionally, the general-purpose bus decoding module 15 can be an advanced extensible interface decoding AXI decoder module, which is a Xilinx built-in IP core, thereby transforming AXI read and write operations into operations of various interface modules. This module can be implemented using Xilinx's high-level synthesis (HLS) tool to further improve development efficiency.

[0046] Optionally, the various interface bus modules include at least two of the following: a serial peripheral interface (SPI) module, an internal integrated circuit (I2C) module, a general purpose input / output (GPIO) module, a universal asynchronous receiver / transmitter (UART) module, and a pulse module. The SPI module enables read / write operations on the SPI interface, the I2C module enables read / write operations on the I2C interface, the GPIO module enables input / output operations on the general purpose I / O interface, the UART module enables read / write operations on the universal serial bus, and the PULSE module enables the output of various pulses. This allows for interaction between the various interface bus modules and the logic modules of the chip under test, enabling switching between different modes, thus improving versatility and adapting to the needs of different scenarios.

[0047] In one possible implementation, see Figure 2 As shown, the system also includes: input / output buffers 19 with various level formats; depending on the level format, the input / output buffers 19 may include input / output buffers 191, input / output buffers 192, etc.

[0048] One end of the multi-level format input / output buffer 19 is connected to the programmable logic device 1; the other end of the multi-level format input / output buffer 19 is connected to the electrical interface of an external device, for converting the multi-level format into the level format of the programmable logic device.

[0049] Optionally, multiple level formats are available, including at least two of the following: 5V transistor logic level (TTL), 3.3V low-voltage transistor logic level (LVTTL), 2.5V low-voltage transistor logic level (LVTTL), 1.8V low-voltage transistor logic level (LVTTL), low-voltage differential signaling (LVDS), and the RS232 standard asynchronous transmission interface level. This allows for connection to external devices via various level interfaces through connectors, enhancing hardware versatility.

[0050] Optionally, the programmable logic device 1 provided in this application embodiment can be a field programmable gate array (FPGA), or other programmable logic devices, such as programmable array logic (PAL), generic array logic (GAL), etc. In this application embodiment, the programmable logic device 1 is an FPGA, specifically Xilinx's XC7K325T.

[0051] This application provides a chip testing system, including a programmable logic device (PLD). The PLD includes a universal bus conversion module, a universal bus interconnect module, and a universal bus decoding module. The universal bus conversion module converts the chip test program loading interface to a universal bus master interface, and the chip test program loading interface loads the chip test program. The universal bus interconnect module interconnects the universal bus master interface with multiple universal bus slave interfaces. A first universal bus slave interface connects to the universal bus decoding module, which connects to various interface bus modules. At least one second universal bus slave interface connects to each logic module of the chip under test (DUT) for testing each logic module. This allows for interaction between various interface bus modules and the logic modules of the DUT, enabling switching between different modes, thus improving versatility and adapting to different scenarios.

[0052] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on its differences from other embodiments. In particular, the device embodiments are basically similar to the method embodiments, so they are described more simply; relevant parts can be referred to the descriptions in the method embodiments.

[0053] The above description is merely a preferred embodiment of this application. Although this application has disclosed preferred embodiments above, it is not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application using the methods and techniques disclosed above, or modify them into equivalent embodiments with equivalent changes, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall still fall within the protection scope of the technical solutions of this application.

Claims

1. A chip testing system, characterized in that, The system includes programmable logic devices; the programmable logic devices include: a general-purpose bus conversion module, a general-purpose bus interconnect module, and a general-purpose bus decoding module; the general-purpose bus interconnect module includes an Advanced Scalable Interface Interconnect (AXI Interconnect) module, the general-purpose bus decoding module includes an AXI decoder module, and the various interface bus modules include at least two of the following: a Serial Peripheral Interface (SPI) module, an Internal Integrated Circuit (I2C) module, a General Purpose Input / Output (GPIO) module, a Universal Asynchronous Receiver / Transmitter (UART) module, and a Pulse module; One end of the universal bus conversion module is connected to the chip test program loading interface, and the other end is connected to the universal bus main interface, which is used to realize the bus conversion between the chip test program loading interface and the universal bus main interface; the chip test program loading interface is used to load the chip test program; One end of the universal bus interconnect module is connected to the universal bus master interface, and the other end is connected to the universal bus first slave interface and at least one universal bus second slave interface, respectively, to realize the interconnection between the universal bus master interface and multiple universal bus slave interfaces; The first slave interface of the general-purpose bus is connected to the general-purpose bus decoding module; the general-purpose bus decoding module is used to connect to multiple interface bus modules; The at least one general-purpose bus second slave interface is respectively connected to each logic module of the chip under test, and is used to test each logic module of the chip under test; The system also includes: input / output buffers with multiple level formats; the multiple level formats include at least two of the following: 5V transistor logic level TTL, 3.3V low-voltage transistor logic level LVTTL, 2.5V low-voltage transistor logic level LVTTL, 1.8V low-voltage transistor logic level LVTTL, low-voltage differential signal LVDS, and asynchronous transmission standard interface RS232 standard level; One end of the multi-level format input / output buffer is connected to the programmable logic device; the other end of the multi-level format input / output buffer is connected to the electrical interface of an external device, for converting the multi-level format into the level format of the programmable logic device.

2. The system according to claim 1, characterized in that, The chip testing program includes: the TCL script program, a tool command language.

3. The system according to claim 1, characterized in that, The universal bus conversion module includes: Joint test workgroup interface to advanced extensible interface JTAG to AXI module, or MicroBlaze soft core.

4. The system according to claim 3, characterized in that, include: When the general-purpose bus conversion module is the MicroBlaze soft core, the chip test program is a C program.

5. The system according to any one of claims 1-4, characterized in that, The programmable logic device includes: Field Programmable Gate Array (FPGA).

Images