Method and circuit simulation system for establishing a process drift model regarding circuit characteristics for performing circuit simulation

Abstract

The present invention provides a method for establishing a process drift model of circuit characteristics for circuit simulation, comprising: performing first, second, third, and fourth Monte Carlo simulation operations based on a first netlist file and predetermined process model data to generate first, second, third, and fourth performance simulation results, wherein the first netlist file is used to indicate the basic circuits in the circuit system; and executing a performance simulation result extension procedure based on the first, second, third, and fourth performance simulation results to generate a plurality of performance simulation results to establish the process drift model for circuit simulation to generate circuit simulation results of the circuit system based on one or more of the plurality of performance simulation results, wherein the number of the plurality of performance simulation results is greater than four.

Description

Technical Field

[0001] This invention relates to circuit design, and more particularly to a method and a related circuit simulation system for establishing a process drift model (variation model) of circuit characteristics for circuit simulation. Background Technology

[0002] Traditional integrated circuit (IC) design flows typically require a long time to complete the entire IC design without errors for mass production. In particular, the delay of basic circuits in an IC, such as standard cells, can vary under different conditions, and the databases used in traditional IC design flows may only record the delay value information for each standard cell under specific application conditions, resulting in limited delay information. This limited delay information is insufficient to calculate the parameter variations required during IC design. Consequently, IC designers may be forced to wait until the IC is fully fabricated before testing it to determine whether the delay values ​​of the standard cells within the IC meet the requirements within a predetermined voltage range. If any standard cell in the IC fails to meet the requirements, the IC must be redesigned, meaning the entire design flow must be re-executed, which is a significant burden for those involved. Some suggestions have been proposed in related technologies to attempt to solve this problem, but these may introduce additional problems such as side effects. Therefore, a novel method and related system are needed to shorten the time to complete the entire IC design without errors for mass production with few or no side effects. Summary of the Invention

[0003] One object of the present invention is to provide a method and a related circuit simulation system for establishing a process drift model of circuit characteristics for circuit simulation, in order to solve the above-mentioned problems.

[0004] Another object of the present invention is to provide a method and a related circuit simulation system for establishing a process drift model of circuit characteristics for circuit simulation, so as to shorten the time to complete the entire IC design without any errors for mass production with no or fewer side effects.

[0005] At least one embodiment of the present invention provides a method for establishing a process drift model of circuit characteristics for circuit simulation. The method may include: performing multiple first Monte Carlo simulations in parallel based on a first netlist file and predetermined process model data. The circuit simulation process includes: performing Monte Carlo simulations to generate a first performance simulation result, wherein the first netlist file indicates the basic circuitry in the circuit system; performing multiple second Monte Carlo simulations in parallel with the first netlist file and the predetermined process model data to generate a second performance simulation result; performing multiple third Monte Carlo simulations in parallel with the first netlist file and the predetermined process model data to generate a third performance simulation result; performing multiple fourth Monte Carlo simulations in parallel with the first netlist file and the predetermined process model data to generate a fourth performance simulation result; and performing a performance simulation result extension procedure based on the first, second, third, and fourth performance simulation results to generate multiple performance simulation results to build the process drift model for circuit simulation to generate at least one circuit simulation result of the circuit system based on one or more of the multiple performance simulation results, wherein the number of the multiple performance simulation results in the process drift model is greater than four.

[0006] At least one embodiment of the present invention provides a circuit simulation system, which may include: at least one memory circuit for storing a plurality of source codes; and at least one processor circuit for executing the plurality of source codes in the at least one memory circuit to build a process drift model of circuit characteristics for circuit simulation. For example, the at least one processor circuit performs a plurality of first Monte Carlo simulation operations in parallel according to a first netlist file and predetermined process model data to generate a first performance simulation result, wherein the first netlist file is used to indicate the basic circuits in the circuit system; the at least one processor circuit performs a plurality of second Monte Carlo simulation operations in parallel according to the first netlist file and the predetermined process model data to generate a second performance simulation result; the at least one processor circuit performs a plurality of third Monte Carlo simulation operations in parallel according to the first netlist file and the predetermined process model data to generate a third ... The first netlist file and the predetermined process model data are subjected to multiple fourth Monte Carlo simulation operations in parallel to generate a fourth performance simulation result; and the at least one processor circuit executes a performance simulation result extension procedure based on the first performance simulation result, the second performance simulation result, the third performance simulation result and the fourth performance simulation result to generate multiple performance simulation results to establish the process drift model for performing the circuit simulation to generate at least one circuit simulation result of the circuit system based on one or more of the multiple performance simulation results, wherein the number of the multiple performance simulation results in the process drift model is greater than four.

[0007] One advantage of this invention is that, through a carefully designed process drift modeling mechanism, the method and circuit simulation system of this invention can simultaneously improve circuit simulation speed and maintain circuit simulation accuracy without being hindered by the trade-off between circuit simulation speed and accuracy. Compared to related technologies, the method and circuit simulation system of this invention can shorten the time to complete the entire IC design for mass production without any errors, with few or no side effects. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of a circuit simulation system according to an embodiment of the present invention.

[0009] Figure 2 This is a flowchart of a method for establishing a process drift model of circuit characteristics for circuit simulation according to an embodiment of the present invention.

[0010] Figure 3 The first process drift model establishment control scheme of the method according to an embodiment of the present invention is shown.

[0011] Figure 4An embodiment of the invention is shown as follows. Figure 3 The first process drift model shown illustrates some implementation details of the control scheme.

[0012] Figure 5 Another process drift model is shown to establish a control scheme.

[0013] Figure 6 A second process drift model establishment control scheme of the method according to an embodiment of the present invention is shown.

[0014] Figure 7 An embodiment of the invention is shown as follows. Figure 6 The second process drift model shown contains some implementation details of the control scheme.

[0015] Figure 8 An embodiment of the invention is shown as follows. Figure 6 The accuracy of the control scheme established by the second process drift model shown.

[0016] Figure 9 Another embodiment of the invention is shown as follows. Figure 6 The accuracy of the control scheme established by the second process drift model is shown.

[0017] Figure 10 The workflow of the method according to an embodiment of the present invention is shown. Detailed Implementation

[0018] Figure 1 This is a schematic diagram of a circuit simulation system 100 according to an embodiment of the present invention. The circuit simulation system 100 may include at least one processor circuit (e.g., one or more processor circuits), collectively referred to as processor circuit 110; at least one memory circuit (e.g., one or more memory circuits), collectively referred to as memory circuit 120; a bus 130; and at least one storage device (e.g., one or more storage devices), collectively referred to as storage device 140. Multiple components in the circuit simulation system 100, such as processor circuit 110, memory circuit 120, and storage device 140, can be coupled to each other via the bus 130, but the invention is not limited thereto. In some embodiments, Figure 1 The architecture shown can be modified. In addition, the processor circuit 110 can be used to control the operation of the circuit simulation system 100, the memory circuit 120 can be used to temporarily store information for the circuit simulation system 100, the bus 130 can be used to perform internal signal transmission for the circuit simulation system 100, and the storage device 140 can be used to store information for the circuit simulation system 100.

[0019] For ease of understanding, the circuit simulation system 100 can be implemented using servers, personal computers such as desktop computers and laptops, etc. In particular, the processor circuit 110 can be implemented using processors / processor cores, the memory circuit 120 can be implemented using random access memory (RAM) such as dynamic random access memory (DRAM), and the storage device 140 can be implemented using hard disks, solid-state drives, etc.

[0020] Memory circuit 120 can store multiple source codes 120C. Circuit simulation system 100 (e.g., processor circuit 110) can load source codes 140C stored in storage device 140 into memory circuit 120 to become source code 120C. Source code 140C may include operating system, drivers, application programs, etc., for execution by processor circuit 110 to control the operation of circuit simulation system 100 when loaded into memory circuit 120. In particular, processor circuit 110 can be used to execute source code 120C to build a process drift model of circuit characteristics for circuit simulation. For example, source code 120C may include a process drift model creation program 122, a performance simulation result extension program 124, and a circuit simulation program 126. Processor circuit 110 may execute the process drift model creation program 122, the performance simulation result extension program 124, and the circuit simulation program 126 respectively to configure one or more sub-circuits of processor circuit 110 (e.g., one or more processors / processor cores) into a plurality of functional modules 110M, namely process drift model creation module 112, performance simulation result extension module 114, and circuit simulation module 116, for respectively performing process drift model creation, performance simulation result extension, and circuit simulation. Storage device 140 may store at least one netlist file (e.g., one or more netlist files), collectively referred to as netlist file 142, predetermined process model data 144, and at least one process drift model (e.g., one or more process drift models), collectively referred to as process drift model VM. The circuit simulation system 100 (e.g., processor circuit 110) can perform the process drift model establishment, in particular, establish a process drift model VM containing multiple performance simulation results {PSR} based on the netlist file 142 and predetermined process model data 144, for performing the circuit simulation to generate at least one circuit simulation result such as circuit simulation result CSR.

[0021] Figure 2 This is a flowchart illustrating a method for establishing a process drift model of circuit characteristics for circuit simulation, according to an embodiment of the present invention, wherein the method can be applied to... Figure 1 The circuit simulation system 100 shown is shown.

[0022] In step S210, the processor circuit 110 can perform parallel processing, in particular, the respective operations of sub-steps S211 to S214 of step S210 are performed in parallel.

[0023] In step S211, the processor circuit 110 may perform multiple first Monte Carlo simulation operations in parallel with the netlist file 142 and the predetermined process model data 144 to generate a first performance simulation result such as a performance simulation result PSR(1,1). The netlist file 142 can be used to indicate the basic circuits in the circuit system, but the invention is not limited thereto. For example, the basic circuit can represent any one of multiple basic circuits (such as multiple standard cells) in the circuit system, and the netlist file 142 can be used to indicate the multiple basic circuits.

[0024] In step S212, the processor circuit 110 may perform multiple second Monte Carlo simulation operations in parallel according to the netlist file 142 and the predetermined process model data 144 to generate a second performance simulation result such as the performance simulation result PSR(M1,1), where the symbol “M1” may represent a positive integer greater than one.

[0025] In step S213, the processor circuit 110 may perform multiple third Monte Carlo simulation operations in parallel with the netlist file 142 and the predetermined process model data 144 to generate a third performance simulation result such as the performance simulation result PSR(1,M2), where the symbol “M2” may represent a positive integer greater than one.

[0026] In step S214, the processor circuit 110 may perform multiple fourth Monte Carlo simulation operations in parallel according to the netlist file 142 and the predetermined process model data 144 to generate fourth performance simulation results such as performance simulation results PSR(M1,M2).

[0027] In step S220, the processor circuit 110 may execute a performance simulation result extension program 124 based on the first performance simulation result, the second performance simulation result, the third performance simulation result and the fourth performance simulation result to generate multiple performance simulation results {PSR} to establish a process drift model VM, wherein the number of multiple performance simulation results {PSR} in the process drift model VM is greater than four.

[0028] For ease of understanding, when the first performance simulation result, the second performance simulation result, the third performance simulation result, and the fourth performance simulation result represent performance simulation results PSR(1,1), PSR(M1,1), PSR(1,M2), and PSR(M1,M2) respectively, multiple performance simulation results {PSR} can contain (M1*M2) performance simulation results {{PSR(1,1),…,PSR(M1,1)},…,{PSR(1,M2),…,PSR(M1,M2)}}. For example, the performance simulation results PSR(1,1), PSR(M1,1), PSR(1,M2), and PSR(M1,M2) can represent boundary values ​​corresponding to boundary conditions. The processor circuit 110 can perform interpolation operations based on the performance simulation results PSR(1,1), PSR(M1,1), PSR(1,M2), and PSR(M1,M2) to generate corresponding interpolation results as the remaining performance simulation results (other than the performance simulation results PSR(1,1), PSR(M1,1)}, ..., {PSR(1,M2), ..., PSR(M1,M2)}} in the (M1*M2) performance simulation results {{PSR(1,1),...,PSR(M1,1)},...,{PSR(1,M2),...,PSR(M1,M2)}}, but the present invention is not limited thereto. In some embodiments, the processor circuit 110 may perform interpolation and / or extrapolation operations based on the performance simulation results PSR(1,1), PSR(M1,1), PSR(1,M2) and PSR(M1,M2) to generate corresponding interpolation and / or extrapolation results as the remaining performance simulation results (parts other than the performance simulation results PSR(1,1), PSR(M1,1), PSR(1,M2) and PSR(M1,M2)) among the plurality of performance simulation results {PSR}.

[0029] Furthermore, the plurality of basic circuits and the plurality of standard circuit units can be referred to as basic circuits #1, #2, ... and #K and standard circuit units #1, #2, ... and #K, respectively, and any basic circuit can be referred to as any basic circuit #k. The index k of the basic circuit can be a positive integer in the interval [1, K], and the total number K of basic circuits #1, #2, ... and #K can be a positive integer greater than or equal to one thousand, but this invention is not limited thereto. Multiple performance simulation results {PSR} can represent K sets of performance simulation results {{PSR1}, {PSR2}, ..., {PSR...} corresponding to the basic circuits #1, #2, ..., #K, respectively. K The set of performance simulation results {PSR} corresponding to any basic circuit #k in}} K}, and the K sets of performance simulation results {{PSR1},{PSR2},…,{PSR} in the process drift model VM KEach set of performance simulation results in the}} (such as this set of performance simulation results {PSR) K The number of performance simulation results in}) is greater than four. For example, basic circuits #1, #2, ... and #K (such as standard circuit units #1, #2, ... and #K) may contain inverters, AND gates, OR gates, etc.

[0030] For any basic circuit #k among basic circuits #1, #2, ... and #K, processor circuit 110 can perform a plurality of first Monte Carlo simulation operations, a plurality of second Monte Carlo simulation operations, a plurality of third Monte Carlo simulation operations, and a plurality of fourth Monte Carlo simulation operations in steps S211 to S214 to generate the first performance simulation result, the second performance simulation result, the third performance simulation result, and the fourth performance simulation result corresponding to any basic circuit #k, respectively. In particular, in step S220, a performance simulation result extension program 124 can be executed based on the first performance simulation result, the second performance simulation result, the third performance simulation result, and the fourth performance simulation result corresponding to any basic circuit #k to generate this set of performance simulation results {PSR} corresponding to any basic circuit #k. K To establish a process drift model (VM).

[0031] In step S230, the processor circuit 110 may perform the circuit simulation to generate at least one circuit simulation result for the circuit system based on one or more of the plurality of performance simulation results. For example, for the basic circuits #1, #2, ... and #K in the circuit system, the circuit simulation may include:

[0032] (1) Based on multiple component parameters, from the K groups of performance simulation results {{PSR1},{PSR2},…,{PSR K Select the K sets of performance simulation results {{PSR1},{PSR2},…,{PSR} K Each subset of the respective components, in particular, selects the performance simulation results that conform to the current values ​​of the multiple component parameters as the K sets of performance simulation results {{PSR1},{PSR2},…,{PSR}. K The aforementioned subsets of}}; and

[0033] (2) Based on the K sets of performance simulation results {{PSR1},{PSR2},…,{PSR K The aforementioned subsets of each of the above-mentioned components produce at least one circuit simulation result for the circuit system.

[0034] Among them, the K groups of performance simulation results are {{PSR1},{PSR2},…,{PSR}K Each of the aforementioned subsets may contain one or more performance simulation results, but the invention is not limited thereto. For example, the loop including steps S230 and S240 allows the processor circuit 110 to re-perform the circuit simulation, and the processor circuit 110 can select the performance simulation result that conforms to the latest values ​​of the plurality of component parameters as the K sets of performance simulation results {{PSR1},{PSR2},…,{PSR}. K The latest versions of each of the above-mentioned subsets are used to generate the latest version of the at least one circuit simulation result.

[0035] In step S240, the processor circuit 110 can determine whether the at least one circuit simulation result (generated in step S230) conforms to a predetermined circuit design specification. If yes (i.e., conforms to the predetermined circuit design specification), the process ends. Figure 2 The workflow is as shown; if not (i.e., does not meet the predetermined circuit design specifications), proceed to step S230 to re-perform the circuit simulation. For example, the processor circuit 110 may selectively re-perform the circuit simulation based on the result of the at least one circuit simulation, wherein whether to re-perform the circuit simulation is determined based on whether the result of the at least one circuit simulation meets the predetermined circuit design specifications.

[0036] Assuming the decision result of step S240 is negative, and therefore proceeding to step S230 to re-perform the circuit simulation. In this case, for the basic circuits #1, #2, ..., #K in the circuit system, the circuit simulation may further include:

[0037] (1) Update (e.g., modify) the parameters of these multiple components; and

[0038] (2) Based on the updated component parameters, from the K sets of performance simulation results {{PSR1},{PSR2},…,{PSR K Select the K sets of performance simulation results {{PSR1},{PSR2},…,{PSR} K Each of the K sets of performance simulation results (which can be considered as the latest versions of the aforementioned subsets) is a new subset of the K sets of performance simulation results {{PSR1},{PSR2},…,{PSR}. K Each of the above-mentioned new subsets is used to generate at least one new circuit simulation result for the circuit system (which can be regarded as the latest version of the above-mentioned at least one circuit simulation result);

[0039] The processor circuit 110 may determine in step S240 whether the at least one circuit simulation result, such as its latest version, conforms to the predetermined circuit design specifications, so as to determine (again) whether to re-perform the circuit simulation.

[0040] To better understand, this method is available Figure 2 The present invention is illustrated by the workflow shown, but is not limited thereto. According to some embodiments, one or more steps may be performed... Figure 2 Add, delete, or modify within the workflow shown.

[0041] According to some embodiments, the processor circuit 110 executing the performance simulation result extension program 124 can perform machine learning-based performance simulation result extension based on the first performance simulation result, the second performance simulation result, the third performance simulation result, and the fourth performance simulation result to generate multiple performance simulation results {PSR} to establish a process drift model VM. For example, the processor circuit 110 can perform machine learning-based interpolation based on the performance simulation results PSR(1,1), PSR(M1,1), PSR(1,M2) and PSR(M1,M2) to generate corresponding interpolation results as the remaining performance simulation results in the (M1*M2) performance simulation results {{PSR(1,1),…,PSR(M1,1)},…,{PSR(1,M2),…,PSR(M1,M2)}}, where the distribution of the (M1*M2) performance simulation results {{PSR(1,1),…,PSR(M1,1)},…,{PSR(1,M2),…,PSR(M1,M2)}} can be linear or nonlinear. As another example, the processor circuit 110 can perform machine learning-based interpolation and / or extrapolation operations based on the performance simulation results PSR(1,1), PSR(M1,1), PSR(1,M2) and PSR(M1,M2) to generate corresponding interpolation and / or extrapolation results as the remaining performance simulation results among multiple performance simulation results {PSR}, wherein the distribution of the (M1*M2) performance simulation results {{PSR(1,1),…,PSR(M1,1)},…,{PSR(1,M2),…,PSR(M1,M2)}} can be linear or nonlinear.

[0042] According to some embodiments, M1 = M2 = M, where the symbol "M" may represent a positive integer greater than one, but the present invention is not limited thereto.

[0043] Figure 3A first process drift model establishment control scheme according to an embodiment of the present invention is illustrated. During the process drift model establishment, the processor circuit 110 executing the process drift model establishment program 122 can perform a set of operations 310 for generating random samples and a set of operations 320 for estimating the standard deviation (which can be represented by the symbol "σ") from the sample data (labeled as "generating random samples" and "estimating σ from sample data" for brevity, respectively). In particular, a Monte Carlo simulation operation is performed based on a set of corresponding parameter values ​​of any random sample (e.g., each random sample) to generate a performance simulation result corresponding to any basic circuit #k, thereby establishing a process drift model VM. The process drift model VM may include at least one process drift format library (Liberty Variation Format library, hereinafter referred to as "LVF library") 330, such as a Monte Carlo (MC) LVF library, and the parameters Vth and Tox may be examples of the plurality of component parameters, but the present invention is not limited thereto. For example, one of these performance simulation results may include a simulation result of the distribution of the delay DELAY of the output signal of any basic circuit #k relative to the input signal, such as the delay value DELAY. NOMINAL DELAY EARLY and DELAY LATE and standard deviation σ EARLY and σ LATE , relative to a nominal point.

[0044] For ease of understanding, it is assumed that the user of the circuit simulation system 100 has ample time (e.g., more than three months) and that spending considerable time performing numerous Monte Carlo simulations is permissible. The processor circuit 110 executing the process drift model building program 122 can generate a set of performance simulation results {PSR} corresponding to any basic circuit #k based on the first process drift model-based control scheme. K To build a process drift model VM, and in particular, to generate this set of performance simulation results {PSR}. K The effective performance simulation results {PSR} K}, such as the simulation results under all possible combinations of the predetermined candidate values ​​Index1_1~Index1_M1 and Index2_1~Index2_M2 of the circuit characteristic indices Index1 and Index2 of any basic circuit #k, namely, the M1 predetermined candidate values ​​{Index1_1,Index1_2,…,Index1_M1} and the M2 predetermined candidate values ​​{Index2_1,Index2_2,…,Index2_M2}, namely {{(Index1_1,Index2_1),…,(Index1_M1,Index2_1)},…,{(Index1_1,Index2_M2),…,(Index1_M1,Index2_M2)}}, and these simulation results may include:

[0045] (1) A set of delay values ​​331, such as delay value {DELAY} NOMINAL (Index1, Index2)} contains:

[0046] DELAY NOMINAL (Index1_1,Index2_1),…,DELAY NOMINAL (Index1_M1,Index2_1)},

[0047] …,

[0048] DELAY NOMINAL (Index1_1,Index2_M2),…,DELAY NOMINAL (Index1_M1,Index2_M2)}};

[0049] (2) The first group of standard deviations is 332, such as the standard deviation {σ} EARLY (Index1, Index2)} contains:

[0050] {{σ EARLY (Index1_1,Index2_1),…,σ EARLY (Index1_M1,Index2_1)},

[0051] …,

[0052] {σ EARLY (Index1_1,Index2_M2),…,σ EARLY (Index1_M1,Index2_M2)}};and

[0053] (3) The second group of standard deviations 333, such as the standard deviation {σ LATE(Index1,Index2)}, containing: {{σ LATE (Index1_1,Index2_1),…,σ LATE (Index1_M1,Index2_1)},

[0054] …,

[0055] {σ LATE (Index1_1,Index2_M2),…,σ LATE (Index1_M1,Index2_M2)}};

[0056] The delay value DELAY corresponding to the same combination (Index1_i, Index2_j) NOMINAL (Index1_i, Index2_j) and standard deviation σ EARLY (Index1_i,Index2_j) and σ LATE (Index1_i, Index2_j) can be considered as this set of performance simulation results {PSR} K One of the performance simulation results PSR K .

[0057] For example, this set of performance simulation results {PSR} corresponding to any basic circuit #k K} can contain (M1*M2) performance simulation results {{PSR K (1,1),…,PSR K (M1,1)},…,{PSR K (1,M2),…,PSR K (M1,M2)}}, which can be collectively referred to as the performance simulation results {PSR} K (i,j)|i=1,2,…,M1;j=1,2,…,M2}, and these performance simulation results {PSR K Any performance simulation result PSR in (i,j)} K (i,j) may contain a delay value DELAY NOMINAL (Index1_i, Index2_j) and standard deviation σ EARLY (Index1_i,Index2_j) and σ LATE (Index1_i,Index2_j). Therefore, this set of performance simulation results {PSR} corresponds to any basic circuit #k. K} can be represented as follows:

[0058] {PSR K (i,j)=(DELAY NOMINAL(Index1_i,Index2_j),σ EARLY (Index1_i,Index2_j),σ LATE (Index1_i,Index2_j))|i=1,2,…,M1;j=1,2,…,M2};

[0059] It can be equivalent to:

[0060] {(DELAY NOMINAL (Index1,Index2),σ EARLY (Index1,Index2),σ LATE (Index1, Index2))|Index1=Index1_1, Index1_2,…, Index1_M1; Index2=Index2_1, Index2_2,…, Index2_M2};

[0061] However, the present invention is not limited thereto.

[0062] Due to the generation of this set of performance simulation results {PSR K The effective performance simulation results {PSR} K This is very time-consuming, therefore, in the processor circuit 110, the process drift model building module 112 (e.g., the processor circuit 110 executing the process drift model building program 122) can only generate this set of performance simulation results {PSR} in steps S211 to S214. K Performance simulation results PSR K (1,1), PSR K (M1,1), PSR K (1,M2) and PSR K (M1, M2), and call the performance simulation result extension module 114 (e.g., the processor circuit 110 that executes the performance simulation result extension program 124) to perform the performance simulation result PSR in step S220. K (1,1), PSR K (M1,1), PSR K (1,M2) and PSR K (M1, M2) are extended with the performance simulation results (e.g., machine learning-based extension of the performance simulation results) to produce this set of performance simulation results {PSR}. K The effective performance simulation results {PSR} KThe process drift model VM is established to allow the circuit simulation module 116 (e.g., the processor circuit 110 executing the circuit simulation program 126) to refer to the process drift model VM in step S230 for circuit simulation. Therefore, the circuit simulation system 100 operating according to this method can simultaneously improve circuit simulation speed and maintain circuit simulation accuracy without being hindered by the trade-off between circuit simulation speed and circuit simulation accuracy.

[0063] Figure 4 An embodiment of the invention is shown as follows. Figure 3 The diagram illustrates some implementation details of the control scheme for the first process drift model. The horizontal axis represents voltage (VOLTAGE), measurable in volts (V), while the vertical axis represents delay (DELAY). Figure 4 The values ​​can be normalized. The process drift model VM can contain a set of performance simulation results {PSR} corresponding to any basic circuit #k. K}, such as {PSR K (i,j)=(DELAY NOMINAL (Index1_i,Index2_j),σ EARLY (Index1_i,Index2_j),σ LATE The expression (Index1_i, Index2_j))|i=1,2,…,M1;j=1,2,…,M2} indicates the distribution of the delay DELAY of any basic circuit #k (e.g., the inverter) relative to the voltage VOLTAGE applied to that basic circuit #k, but the invention is not limited thereto. For the sake of simplicity, similar content in this embodiment will not be repeated here.

[0064] Figure 5 Another process drift model establishment control scheme is shown. It is assumed that the processor circuit 110 executing the process drift model establishment program 122 can generate this set of performance simulation results {PSR} corresponding to any basic circuit #k according to this other process drift model establishment control scheme. K To build a process drift model VM, and in particular, to generate this set of performance simulation results {PSR}. K The effective performance simulation results {PSR} KIn this case, the processor circuit 110 can perform machine learning (ML)-based extrapolation / interpolation 520 based on a reference process parameter condition LVF library 511 and a target process parameter condition list 512, specifically to generate an ML LVF library 530. Typically, the term "process parameter condition" can represent a combination of process, voltage, and temperature, such as a set of process-voltage-temperature (PVT) conditions. The reference process parameter condition LVF library 511 may contain performance requirement information for a set of predetermined process parameter conditions (e.g., a set of predetermined PVT conditions), while the target process parameter condition list 512 may contain a set of target process parameter conditions (e.g., a set of target PVTs). A control scheme is established based on this alternative process drift model, and since Monte Carlo simulation is not required, the generation of the ML LVF library 530 can be very fast. However, the accuracy of the ML LVF library 530 can be very low.

[0065] Figure 6 A second process drift model establishment control scheme according to an embodiment of the present invention is illustrated. For ease of understanding, the reference process parameter condition LVF library 611 and the target process parameter condition list 612 can be equivalent to the reference process parameter condition LVF library 511 and the target process parameter condition list 512, respectively, and the ML-based extrapolation / interpolation 620 can be the same as or similar to the ML-based extrapolation / interpolation 520. The shrinkage index table LVF library 613 can represent at least a portion (e.g., a portion or all) of the LVF library 330, in particular, a compact version of the LVF library 330, rather than the full version of the LVF library 330, wherein the full version may contain this set of performance simulation results {PSR} corresponding to any basic circuit #k. K The effective performance simulation results {PSR} K This sophisticated version can include this set of performance simulation results {PSR}. K Performance simulation results PSR K (1,1), PSR K (M1,1), PSR K (1,M2) and PSR K (M1,M2).

[0066] For example, the process drift model building module 112 can generate only this set of performance simulation results {PSR} in steps S211 to S214. K Performance simulation results PSR K (1,1), PSR K(M1,1), PSR K (1,M2) and PSR K (M1, M2) to establish the shrink index table LVF library 613, and call the performance simulation result extension module 114 to perform the performance simulation result PSR in step S220 based on the shrink index table LVF library 613. K (1,1), PSR K (M1,1), PSR K (1,M2) and PSR K (M1,M2) are subjected to ML-based extrapolation / interpolation 620 to produce this set of performance simulation results {PSR} K The effective performance simulation results {PSR} K The process drift model VM is established, specifically, a high-precision LVF library 630 is established to allow the circuit simulation module 116 to refer to the process drift model VM, such as the high-precision LVF library 630, in step S230 to perform the circuit simulation. For the sake of simplicity, similar content will not be repeated here in this embodiment.

[0067] Figure 7 An embodiment of the invention is shown as follows. Figure 6 The second process drift model shown contains some implementation details of the control scheme. Figure 7 The upper part indicates the complete version of LVF library 330, which may contain this set of performance simulation results {PSR} corresponding to any basic circuit #k. K The effective performance simulation results {PSR} K For example, the above set of delay values ​​331 includes delay values ​​such as {DELAY}. NOMINAL (Index1,Index2)}, the first group's standard deviation is 332, such as the standard deviation {σ} EARLY (Index1,Index2)}, and the second set of standard deviations 333, such as the standard deviation {σ} LATE (Index1, Index2)}. Additionally... Figure 7 The lower part indicates that the shrink index table LVF library 613 can be implemented as a more concise version of LVF library 330, which can include this set of performance simulation results {PSR}. K Performance simulation results PSR K (1,1), PSR K (M1,1), PSR K (1,M2) and PSR K(M1, M2), for example, the respective subsets of the aforementioned set of delay values ​​331, the first set of standard deviations 332, and the second set of standard deviations 333 in the complete version, such as delay values ​​331S, standard deviations 332S, and 333S. For the sake of simplicity, similar content will not be repeated here in this embodiment.

[0068] Figure 8 An embodiment of the invention is shown as follows. Figure 6 The second process drift model shown establishes the accuracy of the control scheme. The horizontal axis represents voltage (VOLTAGE), which can be measured in volts (V), while the vertical axis represents delay (DELAY), which can be measured in nanoseconds (ns). Figure 8 As shown in the lower right corner, multiple sets of curves corresponding to various voltage ranges indicate the performance requirements of the reference process parameters. The complete version of LVF library 330 can be generated based on the control scheme established by this first process drift model, and it can be very accurate. For example, data points belonging to the complete version of LVF library 330 (labeled "belonging to 330" for simplicity) can be very accurate and suitable as a reference for circuit simulation, making the simulation results very close to the test results of the circuit system during mass production. In addition, the ML LVF library 530 can be generated based on the control scheme established by this other process drift model, and its accuracy can be very low. For example, data points belonging to ML LVF library 530 (labeled "belonging to 530" for simplicity) may have low accuracy and are not suitable as a reference for circuit simulation because ML LVF library 530 can cause the circuit system to fail during mass production testing. Furthermore, the high-accuracy LVF library 630 can be generated based on the control scheme established by this second process drift model, and it is more accurate. For example, data points belonging to one of the high-precision LVF libraries 630 (labeled "belonging to 630" for brevity) can also be very accurate and suitable as a reference for the circuit simulation, making the simulation results very close to the test results of the circuit system during mass production. For the sake of simplicity, similar content will not be repeated here in this embodiment.

[0069] Figure 9 Another embodiment of the invention is shown as follows. Figure 6The second process drift model shown establishes the accuracy of the control scheme. The horizontal and vertical axes represent the slew rate (SLEW) and standard deviation σ, respectively, which can be measured in nanoseconds (ns). Since the SLEW of a signal can be expressed as the change of voltage per unit of time to indicate the slope of a local waveform, for a predetermined voltage change, the SLEW can also be expressed in time to indicate the same slope. This predetermined voltage change represents the minimum voltage value V of the signal. MIN and the maximum value V MAX Defined voltage range (e.g., interval [V]) MIN V MAX One of the main ranges in ]) is the interval [V] MIN +((V MAX -V MIN )*P SLEW ),V MAX -((V MAX -V MIN )*P SLEW For ease of understanding, the range parameter P SLEW It can be equal to 30%, but the present invention is not limited thereto. The range parameter P can be adjusted as long as it does not impede the implementation of the present invention. SLEW It can be equal to any value in the interval (0,1), such as 5%, 10%, 15%, 20%, etc.

[0070] For example, a set of curves belonging to the complete version of LVF library 330 (labeled "belongs to 330" for simplicity) can be very accurate and suitable as a reference for circuit simulation, making the simulation results very close to the test results of the circuit system during mass production. Conversely, a set of curves belonging to ML LVF library 530 (labeled "belongs to 530" for simplicity) may have lower accuracy and is unsuitable as a reference for circuit simulation because ML LVF library 530 can cause the circuit system to fail during mass production testing. Furthermore, a set of curves belonging to the high-accuracy LVF library 630 (labeled "belongs to 630" for simplicity) is also relatively accurate and suitable as a reference for circuit simulation, making the simulation results very close to the test results of the circuit system during mass production. Figure 9It is clearly stated that the set of curves belonging to the ML LVF library 530 is not equal to (or cannot be considered equal to) the set of curves belonging to the complete version of the LVF library 330 (marked with "≠" for simplicity), while the set of curves belonging to the high-precision LVF library 630 is approximately equal to (or can be considered equal to) the set of curves belonging to the complete version of the LVF library 330 (marked with "≠" for simplicity). (For the sake of simplicity). For the sake of simplicity, similar content in this embodiment will not be repeated here.

[0071] Figure 10 The workflow of the method according to an embodiment of the present invention is illustrated. The circuit simulation module 116 (e.g., processor circuit 110 executing circuit simulation program 126) can perform steps S1011 to S1014. In particular, steps S1011 and S1013 can be performed with reference to the design margin provided by the LVF library 1030, wherein the circuit simulation described in step S230 may include the operations of steps S1011 to S1013. For example, the LVF library 1030 may include at least one LVF library such as the high-precision LVF library 630.

[0072] In step S1011, the circuit simulation module 116 may perform a synthesis operation according to the LVF library 1030 to convert the information used to describe the operation of the circuit system into at least a portion of the basic circuits #1, #2, ... and #K (such as standard circuit units #1, #2, ... and #K), for example, basic circuits #1, #2, ... and #K0, where the symbol "K0" may represent a positive integer less than or equal to K.

[0073] In step S1012, the circuit simulation module 116 can perform placement and routing operations to establish a circuit system model of the circuit system.

[0074] In step S1013, the circuit simulation module 116 may perform static timing analysis (STA) to generate at least one STA result as at least one circuit simulation result in step S230.

[0075] In step S1014, the circuit simulation module 116 determines whether the at least one circuit simulation result, such as the at least one STA result (just generated in step S1013), conforms to the predetermined circuit design specifications. If yes, the process ends. Figure 10 The workflow shown is as follows; if not, proceed to step S1011 to re-simulate the circuit.

[0076] Assuming the determination result of step S1014 is negative, the process proceeds to step S1011 to re-perform the circuit simulation. In this case, for at least a portion of the basic circuits #1, #2, ..., and #K in the circuit system, such as basic circuits #1, #2, ..., and #K0, the circuit simulation module 116 can update (e.g., modify) the multiple component parameters (labeled "modified" for brevity), and in step S1013, based on the updated multiple component parameters, from the performance simulation results {{PSR1}, {PSR2}, ..., {PSR...} of group K0. K0 Select the performance simulation results of group K0: {{PSR1}, {PSR2}, ..., {PSR} K0 Each of the new subsets, in particular, selects the performance simulation results that conform to the latest values ​​of the multiple component parameters as the performance simulation results of the K0 group {{PSR1},{PSR2},…,{PSR}. K0 The aforementioned new subsets are used to generate the latest version of the at least one circuit simulation result (e.g., the at least one STA result) of the circuit system, wherein the circuit simulation module 116 can determine in step S1014 (the one or more circuit simulation results just generated in step S1013), such as its latest version, whether it conforms to the predetermined circuit design specifications, so as to (again) determine whether to re-perform the circuit simulation. For the sake of simplicity, similar content will not be repeated here in this embodiment.

[0077] To better understand, this method is available Figure 10 The present invention is illustrated by the workflow shown, but is not limited thereto. According to some embodiments, one or more steps may be performed... Figure 10 Add, delete, or modify within the workflow shown.

[0078] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be covered by the present invention.

[0079] [Symbol Explanation]

[0080] 100: Circuit Simulation System

[0081] 110: Processor circuit

[0082] 110M: Functional Module

[0083] 112: Process Drift Model Establishment Module

[0084] 114: Performance Simulation Results Extension Module

[0085] 116: Circuit Simulation Module

[0086] 120: Memory circuit

[0087] 120C, 140C: Source Code

[0088] 122: Process Drift Model Establishment Procedure

[0089] 124: Performance Simulation Results Extension Program

[0090] 126: Circuit Simulation Program

[0091] 130: Bus

[0092] 140: Storage device

[0093] 142: Netlist file

[0094] 144: Pre-defined process model data

[0095] VM: Process Drift Model

[0096] PSR: Performance Simulation Results

[0097] CSR: Circuit Simulation Results

[0098] S210~S214, S220, S230, S240: Steps

[0099] 310: Operations for generating random samples

[0100] 320: Estimating the standard deviation (σ) from sample data

[0101] 330: Process Drift Format (LVF) Library

[0102] 331,331S,DELAYNOMINAL,DELAYEARLY,DELAYLATE: Delay values

[0103] 332,332S,333,333S,σEARLY,σLATE: Standard deviation

[0104] Vth, Tox: Parameters

[0105] Index1, Index2: Circuit characteristic index

[0106] DELAY: Delay

[0107] VOLTAGE: Voltage

[0108] 511, 611: Reference process parameter conditions process drift format (LVF) library

[0109] 512, 612: List of target process parameter conditions

[0110] 520, 620: Extrapolation / Interpolation based on Machine Learning (ML)

[0111] 530: Machine Learning (ML) Process Drift Format (LVF) Library

[0112] 613: Shrink the index table process drift format (LVF) library

[0113] 630: High-Precision Process Drift Format (LVF) Library

[0114] Index1_1~Index1_M, Index2_1~Index2_M: Pre-defined candidate values

[0115] σ: Standard deviation

[0116] SLEW: Voltage Slew Rate

[0117] ≠: Not equal to

[0118] Approximately equal to

[0119] S1011~S1014: Steps

[0120] 1030: Process Drift Format (LVF) Library

Claims

1. A method for establishing a process drift model for a circuit characteristic for performing a circuit simulation, the method comprising: performing a plurality of first Monte Carlo simulation operations in parallel according to a first netlist file and predetermined process model data to generate first performance simulation results, wherein the first netlist file is used to indicate a base circuit in a circuit system; performing a plurality of second Monte Carlo simulation operations in parallel according to the first netlist file and the predetermined process model data to generate second performance simulation results; performing a plurality of third Monte Carlo simulation operations in parallel according to the first netlist file and the predetermined process model data to generate third performance simulation results; performing a plurality of fourth Monte Carlo simulation operations in parallel according to the first netlist file and the predetermined process model data to generate fourth performance simulation results; and executing a performance simulation result expansion procedure according to the first performance simulation results, the second performance simulation results, the third performance simulation results, and the fourth performance simulation results to generate a plurality of performance simulation results to establish the process drift model for performing the circuit simulation to generate at least one circuit simulation result of the circuit system according to one or more of the plurality of performance simulation results, wherein a number of the plurality of performance simulation results in the process drift model is greater than four.

2. The method of claim 1, wherein the base circuit represents any one of a plurality of base circuits in the circuit system, and the plurality of performance simulation results represents a corresponding one of a plurality of sets of performance simulation results respectively corresponding to the plurality of base circuits.

3. The method of claim 2, wherein a number of performance simulation results in each of the plurality of sets of performance simulation results in the process drift model is greater than four.

4. The method of claim 2, wherein for the any one of the plurality of base circuits, the plurality of first Monte Carlo simulation operations, the plurality of second Monte Carlo simulation operations, the plurality of third Monte Carlo simulation operations, and the plurality of fourth Monte Carlo simulation operations are performed to respectively generate the first performance simulation results, the second performance simulation results, the third performance simulation results, and the fourth performance simulation results corresponding to the any one of the plurality of base circuits.

5. The method of claim 4, wherein for the any one of the plurality of base circuits, the performance simulation result expansion procedure is executed according to the first performance simulation results, the second performance simulation results, the third performance simulation results, and the fourth performance simulation results corresponding to the any one of the plurality of base circuits to generate the set of performance simulation results corresponding to the any one of the plurality of base circuits to establish the process drift model.

6. The method of claim 2, wherein for the plurality of base circuits in the circuit system, the circuit simulation comprises: ​ generating the at least one circuit simulation result of the circuit system according to respective sub-sets of the plurality of sets of performance simulation results, wherein each of the respective sub-sets of the plurality of sets of performance simulation results comprises one or more performance simulation results.

7. The method of claim 6, wherein the circuit simulation further comprises, for the plurality of basic circuits in the circuit system: selecting the respective sub-sets of the plurality of sets of performance simulation results from the plurality of sets of performance simulation results according to a plurality of element parameters for generating the at least one circuit simulation result of the circuit system.

8. The method of claim 7, wherein the circuit simulation further comprises, for the plurality of basic circuits in the circuit system: updating the plurality of element parameters, and selecting respective new sub-sets of the plurality of sets of performance simulation results from the plurality of sets of performance simulation results according to the updated plurality of element parameters for generating at least one new circuit simulation result of the circuit system.

9. The method of claim 1, wherein the first circuit property index and the second circuit property index of the basic circuit are respectively configurable as one of a plurality of first predetermined candidate values of the first circuit property index and one of a plurality of second predetermined candidate values of the second circuit property index; and the plurality of first Monte Carlo simulation operations, the plurality of second Monte Carlo simulation operations, the plurality of third Monte Carlo simulation operations, and the plurality of fourth Monte Carlo simulation operations are respectively performed with the first circuit property index and the second circuit property index being set as a first combination, a second combination, a third combination, and a fourth combination of the plurality of first predetermined candidate values and the plurality of second predetermined candidate values.

10. A circuit simulation system, comprising: at least one memory circuit to store a plurality of source codes; and at least one processor circuit to execute the plurality of source codes in the at least one memory circuit to establish a process variation model with respect to a circuit property for performing circuit simulation; wherein: the at least one processor circuit performs a plurality of first Monte Carlo simulation operations in parallel according to a first netlist file and predetermined process model data to generate first performance simulation results, wherein the first netlist file is used to indicate a basic circuit in a circuit system; the at least one processor circuit performs a plurality of second Monte Carlo simulation operations in parallel according to the first netlist file and the predetermined process model data to generate second performance simulation results; the at least one processor circuit performs a plurality of third Monte Carlo simulation operations in parallel according to the first netlist file and the predetermined process model data to generate third performance simulation results; the at least one processor circuit performs a plurality of fourth Monte Carlo simulation operations in parallel according to the first netlist file and the predetermined process model data to generate fourth performance simulation results; and the at least one processor circuit selects respective sub-sets of the plurality of sets of performance simulation results from the plurality of sets of performance simulation results according to a plurality of element parameters for generating the at least one circuit simulation result of the circuit system. The at least one processor circuit performs performance simulation result extension procedures according to the first performance simulation result, the second performance simulation result, the third performance simulation result, and the fourth performance simulation result to generate a plurality of performance simulation results to establish the process drift model for performing the circuit simulation to generate at least one circuit simulation result of the circuitry according to one or more performance simulation results of the plurality of performance simulation results, wherein a number of the plurality of performance simulation results in the process drift model is greater than four.

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