integrated circuit

Abstract

The present disclosure relates to an integrated circuit comprising at least one first memory block, at least one second memory block, and a pad configuration area. The first memory block and the second memory block are disposed on opposite sides of the integrated circuit, each including a memory cell array having a three-dimensional architecture. The first memory block and the second memory block are disposed symmetrically with respect to the pad configuration area. The pad configuration area includes a plurality of pads, each electrically coupled to the first memory block and the second memory block.

Description

Technical Field

[0001] The present disclosure relates to an integrated circuit, and more particularly to an integrated circuit capable of reducing layout area. Background Art

[0002] In the prior art, the bonding pad area of ​​memory chips is typically located at the edge of the integrated circuit. This arrangement often requires the use of transmission wires, with complex routing methods and relatively long routing paths, to electrically couple the bonding pads to distant memory blocks within an integrated circuit (IC). This often requires additional area to accommodate these transmission wires, increasing the IC's layout area. Furthermore, excessively long transmission wires often create excess parasitic resistance and parasitic capacitance between them. These parasitic effects can also degrade the quality of signals and power transmitted by the transmission wires, impacting the IC's performance. Summary of the Invention

[0003] At least one embodiment of the present disclosure provides a variety of integrated circuits that can shorten the length of transmission wires between bonding pads and memory blocks, reduce the layout area of ​​the integrated circuit, and improve signal transmission efficiency.

[0004] In one embodiment of the present disclosure, an integrated circuit includes at least one first memory block, at least one second memory block, and a pad configuration area. The first memory block and the second memory block are disposed on opposite sides of the integrated circuit, respectively, wherein each of the at least one first memory block and the at least one second memory block includes a memory cell array having a three-dimensional architecture. The at least one first memory block and the at least one second memory block are disposed symmetrically with respect to the pad configuration area. A plurality of pads are disposed in the pad configuration area, each of the pads being electrically coupled to the first memory block and the second memory block.

[0005] In another embodiment of the present disclosure, an integrated circuit includes two adjacent first memory blocks and two adjacent second memory blocks, and a pad configuration area. The first memory block and the second memory block are respectively disposed on opposite sides of the integrated circuit. Each of the first memory block and the second memory block includes a memory cell array having a three-dimensional architecture and a minimum spacing between the memory cell array and the first memory block. The pad configuration area is disposed between the first memory block and the second memory block, wherein a plurality of pads are disposed in the pad configuration area and are electrically coupled to the first memory block and the second memory block, respectively.

[0006] Based on the above, in many embodiments of the present disclosure, the integrated circuit is configured so that the first memory block and the second memory block are symmetrically arranged with respect to the pad arrangement area, thereby enabling the first memory block and the second memory block to be electrically coupled to adjacent pads in the pad arrangement area. This effectively reduces the length of the transmission wires connecting the pads to the first memory block and the second memory block. Furthermore, no additional layout area is required for the transmission wires, effectively reducing the required layout area. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 FIG. 1 is a schematic diagram of an integrated circuit according to an embodiment of the present disclosure.

[0008] Figure 2 FIG. 1 is a schematic diagram of an integrated circuit according to another embodiment of the present disclosure.

[0009] Figure 3 for Figure 2 A partially enlarged view of the memory blocks 210 and 230 of the embodiment.

[0010] Figure 4 FIG. 4 is a cross-sectional view of a memory block in an integrated circuit according to an embodiment of the present disclosure.

[0011] Figure 5 FIG. 1 is a schematic diagram illustrating the positional relationship between a memory block and a bonding pad configuration area in an integrated circuit according to an embodiment of the present disclosure.

[0012] Figure 6A as well as Figure 6B Schematic diagrams of different implementations of the coupling relationship between the control circuit and the bonding pad of the integrated circuit according to the embodiment of the present disclosure.

[0013] Figure 7A as well as Figure 7B They are schematic diagrams of different implementations of integrated circuits according to the embodiments of the present disclosure.

[0014] Description of Reference Numerals

[0015] 100, 200, 500, 701, 702: integrated circuits

[0016] 110, 120, 210, 220, 230, 240, 400, 510~540, 710~780: Memory blocks

[0017] 130, 250, 550, 790: pad configuration area

[0018] 211, 221, 231, 241, 411: Address decoding circuits

[0019] 212, 222, 232, 242: Memory cell array

[0020] 213, 223, 233, 243, 413, 521~541: Sensing circuit

[0021] 214, 224, 234, 244, 514~544, 610: Control circuit

[0022] 401: Conductive layer

[0023] 402: Laminated structure

[0024] 404: First Material

[0025] 412: Charge Storage Structure

[0026] 420: Vertical channel structure

[0027] 426, 426t, 426b: Conductor layer

[0028] D1: Length

[0029] D2: Distance

[0030] EXT: Extension

[0031] MA: Memory Cell Array

[0032] MC1: Storage cell group

[0033] MT1~MTN: Metal layer

[0034] PD: solder pad

[0035] SC: ladder structure

[0036] VIA1~VIAN, CNT: connection structure DETAILED DESCRIPTION

[0037] Please refer to Figure 1 , Figure 1 This is a schematic diagram of an integrated circuit according to an embodiment of the present disclosure. Integrated circuit 100 includes memory blocks 110 and 120 and a pad configuration area 130. Memory blocks 110 and 120 are disposed on opposite sides of integrated circuit 100 and are symmetrically arranged with respect to pad configuration area 130. Specifically, pad configuration area 130 may be located in the center of integrated circuit 100.

[0038] The pad configuration area 130 includes a plurality of pads PD. The pads PD are electrically coupled to the memory blocks 110 and 120 via a plurality of transmission lines. In this embodiment, the pads PD may be input / output pads (I / O pads). Each pad PD may function as a transmission medium for transmitting signals or power voltages.

[0039] Furthermore, in this embodiment, memory blocks 110 and 120 may have the same circuit architecture and be symmetrically arranged on either side of pad configuration area 130. With this layout, both memory blocks 110 and 120 are adjacent to pad configuration area 130. Multiple transmission wires can be utilized between memory blocks 110 and 120 and their corresponding pads PD, achieving electrical coupling between memory blocks 110 and 120 and their corresponding pads PD without requiring wire routing. This effectively reduces the length of the transmission wires between memory blocks 110 and 120 and their corresponding pads PD, thereby reducing the layout area required for the transmission wires and lowering the equivalent resistance of the transmission wires, thereby improving the transmission efficiency of signals and power supply voltages.

[0040] Please refer to the following Figure 2 , Figure 2 This is a schematic diagram of an integrated circuit according to another embodiment of the present disclosure. Integrated circuit 200 includes memory blocks 210, 220, 230, 240, and a pad configuration area 250. Memory blocks 210 and 220 are disposed on the same first side of integrated circuit 200, while memory blocks 230 and 240 are disposed on the same second side of integrated circuit 200. Pad configuration area 250 is disposed between the first and second sides. In other words, memory blocks 210 and 230 are symmetrical with respect to pad configuration area 250, and memory blocks 220 and 240 are also symmetrical with respect to pad configuration area 250.

[0041] Furthermore, memory block 210 includes an address decoding circuit 211, a memory cell array 212, a sensing circuit 213, and a control circuit 214. Memory block 220 includes an address decoding circuit 221, a memory cell array 222, a sensing circuit 223, and a control circuit 224. Memory block 230 includes an address decoding circuit 231, a memory cell array 232, a sensing circuit 233, and a control circuit 234. Memory block 240 includes an address decoding circuit 241, a memory cell array 242, a sensing circuit 243, and a control circuit 244. In this embodiment, memory blocks 210, 220, 230, and 240 have the same circuit architecture.

[0042] In this embodiment, taking the memory block 210 as an example, the memory cell array 212 is a three-dimensional memory cell array. In other words, the memory cell array 212 can be a three-dimensional NOR, AND, or NAND flash memory cell array.

[0043] The memory cell array 212 can be stacked above the sensing circuit 213. The sensing circuit 213 is used to sense the read data provided by the memory cell array 212. The address decoding circuit 211 is used to provide an address signal and enable the memory cell array 212 to perform access operations based on the address signal. The control circuit 214 is used to generate control signals to control the access operations of the memory cell array 212.

[0044] In this embodiment, the control circuits 214-244 of the memory blocks 210-240 are all disposed adjacent to the bonding pad area 250. Each of the control circuits 214-244 has multiple terminals, which are electrically coupled to corresponding pads in the bonding pad area 250. The control circuits 214 and 234 can be disposed symmetrically with respect to the bonding pad area 250, and the control circuits 224 and 244 can also be disposed symmetrically with respect to the bonding pad area 250. In this way, the terminals on the control circuits 214, 224, 234, and 244 can be electrically coupled to the bonding pads on the bonding pad area 250 via transmission lines with a short line distance.

[0045] Incidentally, the number of memory blocks in the integrated circuit 200 in this embodiment is 4, that is, 2 2 indivual.

[0046] Please refer to the following Figure 3 , Figure 3 for Figure 2 A partially enlarged view of the memory blocks 210 and 220 of the embodiment. On the coordinate plane formed by the X and Y axes, in memory block 210, multiple memory cell groups MC1 form a memory cell array 212. Some of the memory cell groups MC1 are stacked and arranged on a sensing circuit 213. An address decoding circuit 211 is disposed adjacent to the sensing circuit 213 and the memory cell groups MC1. The address decoding circuit 211 is used to provide address signals to the memory cell array 212. Similarly, in memory block 220, multiple memory cell groups MC2 form a memory cell array 222. Some of the memory cell groups MC2 are stacked and arranged on a sensing circuit 223. The address decoding circuit 221 is disposed adjacent to the sensing circuit 223 and the memory cell groups MC2. The address decoding circuit 221 is used to provide address signals to the memory cell array 222.

[0047] It is worth noting that in this embodiment, the transmission lines between the memory blocks 210, 220 and the bonding pads do not need to pass through the area between the memory blocks 210, 220 for layout. The area between the memory blocks 210, 220 can be used for the layout of the peripheral circuits of the memory blocks 210, 220, without requiring an excessively large area. Therefore, in this embodiment, the shortest separation distance D2 between the memory cell array of memory block 210 and the memory cell array of memory block 220 can be less than 1 / 200 of the length D1 of the memory cell array of memory block 210. It can be seen that the distance between the memory blocks 210, 220 can be effectively reduced.

[0048] Please refer to the following Figure 4 , Figure 4 The integrated circuit of the embodiment of the present disclosure is Figure 3 4 is a cross-sectional view of the memory block along the X-axis. The memory block 400 includes an address decoding circuit 411, a memory cell array MA, and a sensing circuit 413. The address decoding circuit 411 is arranged adjacent to the sensing circuit 413. The address decoding circuit 411 is coupled to the memory cell array MA through a plurality of conductive lines of a ladder structure SC, wherein the ladder structure SC is a word line wiring area arranged in a ladder shape. The memory cell array MA is constructed by a plurality of stacked structures (such as the stacked structure 402), and the stacked structure 402 can be formed on the conductive layer 401. The stacked structure 402 includes a plurality of first materials (such as dielectric layers) 404 and a plurality of conductor layers (word lines) 426 alternately stacked. The vertical channel structure 420 penetrates the stacked structure 402. The charge storage structure 412 surrounds the sidewalls of the vertical channel structure 420. As shown in FIG. Figure 4 As shown, the sensing circuit 413 is arranged under the memory cell array MA. The address decoding circuit 411 is arranged under the ladder structure SC. The control circuit (not shown) is also arranged under the memory cell array MA. Figure 4 In the embodiment, the topmost conductor layer 426t may be used as a string selection line (SSL), and the bottommost conductor layer 426b may be used as a ground selection line (GSL).

[0049] Please refer to the following Figure 5 , Figure 5This diagram illustrates the relationship between memory blocks and pad configuration areas in an integrated circuit according to an embodiment of the present disclosure. Integrated circuit 500 includes memory blocks 510-540 and pad configuration area 550. Memory block 510 includes sensing circuit 511 and control circuit 514; memory block 520 includes sensing circuit 521 and control circuit 524; memory block 530 includes sensing circuit 531 and control circuit 534; and memory block 540 includes sensing circuit 541 and control circuit 544.

[0050] Memory blocks 510 and 530 are arranged symmetrically with respect to pad configuration area 550, and memory blocks 520 and 540 are similarly arranged symmetrically with respect to pad configuration area 550. This allows control circuit 514 in memory block 510, control circuit 524 in memory block 520, control circuit 534 in memory block 530, and control circuit 544 in memory block 540 to be electrically coupled to adjacent pads in pad configuration area 550 via transmission conductors. This effectively reduces the length of the transmission conductors between control circuits 514-544 and their corresponding pads PD. Furthermore, these transmission conductors eliminate the need for wiring, effectively reducing layout area.

[0051] In this embodiment, each of the bonding pads PD can be used to transmit a power supply voltage or a ground voltage. Alternatively, each of the bonding pads PD can also be used to transmit and receive signals without any particular limitation.

[0052] Incidentally, the control circuits 514 - 544 are coupled to the sensing circuits 511 - 541 , respectively. The control circuits 514 - 544 transmit signals to control the sensing operations of the sensing circuits 511 - 541 to read out data.

[0053] For details on the electrical coupling between the control circuits 514-544 and the pads, please refer to Figure 6A as well as Figure 6B Schematic diagrams of different implementations of the coupling relationship between the control circuit and the bonding pad of the integrated circuit of the embodiment of the present disclosure. Figure 6A In the embodiment, the bonding pad PD is located in the bonding pad area of ​​the integrated circuit and can be used as a medium for transmitting and receiving power voltage or ground voltage. In this embodiment, the bonding pad PD is directly connected to the first metal layer MT1. Metal layer MT1 is connected to metal layer MT2 via connection structure VIA1, and metal layer MT2 is connected to the metal layer below via connection structure VIA2. Similarly, the bottom metal layer MTN can be directly connected to the power receiving terminal of the control circuit 610 via connection structure CNT.

[0054] exist Figure 6AIn the embodiment, the vertical projection of the first metal layer MT1 can cover the power receiving terminal of the control circuit 610. In other words, the bonding pad PD and the power receiving terminal of the control circuit 610 can be electrically coupled to each other while minimizing the layout area.

[0055] exist Figure 6B In another embodiment, a bonding pad PD is disposed in the bonding pad area of ​​the integrated circuit and can also serve as a medium for transmitting and receiving power or ground voltages. Bonding pad PD can be directly connected to metal layer MT2 via connection structure VIA1. Metal layer MT2 can also be connected to the underlying metal layer via connection structure VIA2. Similarly, through the staggered arrangement of multiple connection structures VIA1-VIAN and metal layers MT2-MTN, bonding pad PD can be electrically coupled to metal layer MTN.

[0056] It is worth noting that in this embodiment, the metal layer MTN may have an extension portion EXT, wherein the vertical projection of the extension portion EXT may cover the power receiving terminal of the control circuit 610. Furthermore, the extension portion EXT of the metal layer MTN may be directly connected to the power receiving terminal of the control circuit 610 via the connection structure CNT.

[0057] Similarly, through Figure 6B In the embodiment, the bonding pad PD and the power receiving end of the control circuit 610 can also be electrically coupled to each other under the condition of saving the layout area.

[0058] Incidentally, in other embodiments of the present disclosure, the extension portion EXT may also be formed on any one of the metal layers MT2 to MTN, and is not necessarily formed on the metal layer MTN.

[0059] Please refer to the following Figure 7A as well as Figure 7B , Figure 7A as well as Figure 7B They are schematic diagrams of different implementations of the integrated circuit of the embodiment of the present disclosure. Figure 7A In the embodiment, integrated circuit 701 includes memory blocks 710-780 and a pad area 790. In terms of positional arrangement, memory blocks 710 and 750 are symmetrical with respect to pad area 790; memory blocks 720 and 760 are symmetrical with respect to pad area 790; memory blocks 730 and 770 are symmetrical with respect to pad area 790; and memory blocks 740 and 780 are symmetrical with respect to pad area 790. Memory blocks 710-780 may have the same circuit architecture.

[0060] In this embodiment, the number of memory blocks 710 - 780 in the integrated circuit 701 may be 8. In fact, in the embodiment of the present disclosure, the number of memory blocks may be 2 to the power of N, where N may be an integer greater than or equal to 0.

[0061] In this embodiment, the memory blocks 710 - 740 are arranged in the same first row, and the memory blocks 750 - 780 are arranged in the same second row. The pad configuration area 790 is arranged in the row direction and is disposed between the first row and the second row.

[0062] exist Figure 7B , integrated circuit 702 includes memory blocks 710-740 and a pad configuration area 790. Memory blocks 710 and 720 are symmetrical with respect to pad configuration area 790; memory blocks 730 and 740 are symmetrical with respect to pad configuration area 790. Memory blocks 710-740 may have the same circuit architecture.

[0063] Unlike the previous embodiment, the pad arrangement area 790 of this embodiment is arranged in rows. Memory blocks 710 and 730 are arranged in the same first row, while memory blocks 720 and 740 are arranged in the same second row. The pad arrangement area 790 can be arranged between the first and second rows.

[0064] Whether Figure 7A or Figure 7B In this embodiment, the electrical coupling path between the memory block and the pads in the pad configuration area can be effectively shortened, reducing the equivalent resistance of the transmission wires therebetween. Furthermore, the memory block and the pads in the pad configuration area do not need to be connected via transmission wires that require routing, effectively reducing the required circuit layout area.

[0065] In summary, the integrated circuit disclosed herein, by providing a pad configuration area between multiple memory blocks, effectively reduces the length of the transmission conductors connecting these memory blocks to the corresponding pads within the pad configuration area. This effectively reduces the layout area of ​​the integrated circuit and also effectively reduces the resistance of the transmission conductors between the memory blocks and the pads, thereby improving the quality of the transmitted signals (power).

Claims

1. An integrated circuit comprising: At least one first memory block and at least one second memory block are respectively disposed on two sides of the integrated circuit, wherein each of the at least one first memory block and the at least one second memory block includes a memory cell array having a three-dimensional structure; as well as a pad configuration area, wherein the at least one first memory block and the at least one second memory block are arranged symmetrically to the pad configuration area, and a plurality of pads are arranged in the pad configuration area, and the pads are electrically coupled to the at least one first memory block and the at least one second memory block respectively; Each of the at least one first memory block and the at least one second memory block includes a control circuit that generates a control signal to control access actions of the memory cell array; The control circuit of the at least one first memory block and the control circuit of the at least one second memory block are symmetrically arranged with respect to the pad configuration area.

2. The integrated circuit of claim 1 , wherein each of the at least one first memory block and the at least one second memory block comprises: an address decoding circuit for providing an address signal; The memory cell array performs an access operation according to the address signal; A sensing circuit senses read data provided by the memory cell array, wherein the memory cell array is stacked on the sensing circuit. 3 . The integrated circuit according to claim 2 , wherein the control circuit is disposed adjacent to the pad configuration area and electrically coupled to the corresponding pads. 4 . The integrated circuit according to claim 2 , wherein the power receiving end of the control circuit is electrically coupled to a power pad through a plurality of metal layers and a plurality of connection structures, wherein the metal layers and the connection structures are respectively arranged in a staggered manner. 5 . The integrated circuit according to claim 4 , wherein the power pad is directly connected to a first metal layer, and a vertical projection surface of the first metal layer covers the power receiving end of the control circuit. 6 . The integrated circuit according to claim 4 , wherein one of the metal layers has an extension portion, wherein a vertical projection of the extension portion covers the power receiving terminal of the control circuit.

7. An integrated circuit comprising: Two adjacent first memory blocks and two adjacent second memory blocks, the two adjacent first memory blocks and the two adjacent second memory blocks being respectively disposed on opposite sides of the integrated circuit, each of the two adjacent first memory blocks and the two adjacent second memory blocks comprising a memory cell array having a three-dimensional structure and a shortest distance between the memory cell array and the two adjacent first memory blocks; as well as a pad configuration area disposed between the two adjacent first memory blocks and the two adjacent second memory blocks, wherein a plurality of pads are disposed in the pad configuration area and are electrically coupled to the two adjacent first memory blocks and the two adjacent second memory blocks respectively; Each of at least one of the first memory blocks and at least one of the second memory blocks includes a control circuit that generates a control signal to control access actions of the memory cell array; The control circuit of at least one of the first memory blocks and the control circuit of at least one of the second memory blocks are symmetrically arranged with respect to the pad configuration area. 8 . The integrated circuit of claim 7 , wherein the shortest pitch is less than 1 / 200 of the length of the memory cell array of the first memory block.

9. The integrated circuit according to claim 7, further comprising a sensing circuit disposed under the memory cell array.

10. The integrated circuit of claim 7, wherein each of the two adjacent first memory blocks and the two adjacent second memory blocks comprises a decoding circuit arranged in a staircase structure and adjacent to the memory cell array.

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