Method for reducing on-state loss and switching loss in driving circuit and driving circuit

Abstract

A method and a driving circuit for reducing conduction loss and switching loss in a driving circuit, for a driving circuit and a switching circuit, the driving circuit comprising an analog-to-digital converter, the switching circuit comprising an inductor and coupled to a load, the method comprising: performing an analog-to-digital conversion on a load voltage of the load at a first rate; and generating at least one current pulse flowing through the inductor at a second rate; wherein each current pulse in the at least one current pulse is completed within a second period corresponding to the second rate; all of the at least one current pulse is completed within a first period corresponding to the first rate; a first length of the first period is longer than twice a second length of the second period. The method can well arrange the pulse width modulation signal of the direct current to direct current converter to achieve the balance of conduction loss and switching loss, thereby minimizing the power loss of the acoustic system.

Description

Technical Field

[0001] This application relates to a method for driving circuits, and more particularly to a method for reducing conduction and switching losses in driving circuits, especially for audio systems. Background Technology

[0002] Piezoelectric-actuated speakers (piezo-speakers) have recently emerged as promising technologies. Due to the capacitive characteristics of thin-film piezoelectric actuators, these speakers introduce high capacitive loads into amplifiers. However, conventional driver circuits (such as Class AB, Class D, Class G, and Class H amplifiers) are developed under the assumption that the load (a coil made of very fine wire) is primarily resistive and slightly inductive. Therefore, conventional amplifiers are unsuitable for driving high capacitive loads such as piezoelectric-actuated speakers.

[0003] To minimize power loss, the applicant developed a two-way DC-DC converter capable of powering a piezoelectric actuated speaker and recovering power from it; therefore, minimizing power loss is crucial. DC-DC converters experience two main types of power loss: conduction loss and switching loss. Conduction loss occurs when current flows through the on-resistance of the transistor (acting as a switching element) in the DC-DC converter; therefore, the higher the current, the greater the conduction loss. Switching loss occurs when the switching element in the DC-DC converter is switched (e.g., driving the gate of a metal-oxide-semiconductor field-effect transistor to V). ON or V OFF This is generated by the switching element. Regardless of the magnitude of the current passing through the switching element, each switching operation will generate a certain amount of power loss.

[0004] In the switching operation of a DC-DC converter, both conduction losses and switching losses are unavoidable. Therefore, it is necessary to minimize the overall power consumption by achieving a balance between conduction losses and switching losses. Summary of the Invention

[0005] In view of this, the main objective of this application is to provide a method for driving a DC-DC converter in a drive circuit, which can well arrange the pulse width modulation signal controlling the DC-DC converter to achieve a balance between conduction loss and switching loss, thereby minimizing the power loss of the acoustic system.

[0006] This application discloses a method for a driving circuit and a switching circuit. The driving circuit includes an analog-to-digital converter (ADC), and the switching circuit includes an inductor coupled to a load. The method includes the following steps: performing an analog-to-digital conversion on a load voltage of the load at a first rate; and generating at least one current pulse flowing through the inductor at a second rate; wherein each of the at least one current pulses is completed within a second cycle corresponding to the second rate; all of the at least one current pulses are completed within a first cycle corresponding to the first rate; and a first length of the first cycle is longer than twice the second length of the second cycle.

[0007] This application discloses a driving circuit for driving a load. The driving circuit includes: an analog-to-digital converter for performing an analog-to-digital conversion on a load voltage of the load at a first rate; and a switching circuit including an inductor and coupled to the load for generating at least one current pulse flowing through the inductor at a second rate; wherein each of the at least one current pulse is completed within a second cycle corresponding to the second rate; all of the at least one current pulse is completed within a first cycle corresponding to the first rate; and a first length of the first cycle is longer than twice the second length of the second cycle.

[0008] Using this application, the pulse width modulation signal controlling the DC-DC converter can be well arranged to achieve a balance between conduction loss and switching loss, thereby minimizing the power loss of the acoustic system. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of a driving circuit according to an embodiment of this application.

[0010] Figure 2 This section describes the specific operation of the drive circuit at both the analog-to-digital converter frequency and the DC-to-DC operating frequency.

[0011] Figure 3 This section describes the specific operation of the drive circuit at both the analog-to-digital converter frequency and the DC-to-DC operating frequency.

[0012] Figure 4 This is a schematic diagram of pulse control in the cycle of an analog-to-digital converter according to an embodiment of this application.

[0013] Figure 5 This is a flowchart of an embodiment of this application.

[0014] Figure 6 This is a flowchart of an embodiment of this application.

[0015] Figure 7 This is a schematic diagram of an exemplary data field of an effective pulse width control code according to an embodiment of this application.

[0016] Figure 8 This is an effective pulse width control code control scheme according to an embodiment of this application.

[0017] Figure 9 This is a schematic diagram of another exemplary data field of the effective pulse width control code according to another embodiment of this application.

[0018] Figure 10 This is a schematic diagram of a pulse width modulation controller according to an embodiment of this application.

[0019] Symbol explanation:

[0020] 10: Drive circuit

[0021] 11: Voltage source

[0022] 110: Pulse Width Modulation Controller

[0023] 120: Switching circuit

[0024] 130: Analog-to-Digital Converter

[0025] CL: Load

[0026] IN: Input signal

[0027] FB: Feedback Signal

[0028] SP1, SP2, SP3, SP4, SP InFlux SP DeFlux Pulse width modulation signal

[0029] T1, T2, T3, T4: Switches

[0030] L1: Inductor

[0031] ADC slot: Analog-to-digital converter time slot

[0032] T ADC Analog-to-digital converter cycle

[0033] T DC-DC Time slot

[0034] I L Current

[0035] I peak ,I peak Peak current

[0036] CP, CP': Current pulse

[0037] T R ,T F ,T R ',T F ':interval

[0038] ΔQ F ,ΔQ F ',ΔQ R ,ΔQ R ': Charge quantity

[0039] EPWCC: Effective Pulse Width Control Code

[0040] PWCC: Pulse Width Control Code

[0041] NCC: Quantity Control Code

[0042] A02: Control Circuit

[0043] A04: Memory

[0044] A06: Digital-to-Analog Converter

[0045] A08: Waveform Generator

[0046] A10: Quite angry

[0047] LUT: Lookup Table

[0048] S saw : Sawtooth-like signal

[0049] V A Analog voltage Detailed Implementation

[0050] U.S. Patent Publications 11,290,015 and 11,336,182 disclose drive circuits that include a DC-to-DC converter as a switching circuit for driving capacitive loads, particularly suitable for driving capacitive speaker loads within piezoelectrically actuated speakers. DC-to-DC converters consume conduction and switching losses. The drive circuit of this application attempts to minimize both conduction and switching losses.

[0051] Figure 1This is a schematic diagram of a drive circuit 10 according to an embodiment of this application. The drive circuit 10 drives a load according to an input signal IN, and includes a pulse width modulation (PWM) controller 110, a switching circuit 120, and an analog-to-digital converter (ADC) 130. The switching circuit 120 is coupled between a voltage source (or power supply, which may be a battery) 11 and the load CL, and includes an inductor L1 and switches T1-T4. The switching circuit 120 is controlled by pulse width modulation signals SP1-SP4 generated by the PWM controller 110 to perform a DC-DC operation between the voltage source 11 and the load CL, thereby controlling the voltage across the load CL. Here, the DC-DC operation can be referred to as a charging operation that forms a current flowing to the load CL, or a discharging operation that forms another current flowing out of the load CL. The load CL here can primarily be a capacitive load. Generally speaking, charging a load will increase its load voltage, while discharging a load will decrease its load voltage.

[0052] Analog-to-digital converter 130 is used to convert 1 / T ADC The rate at which the load voltage is converted from analog to digital is denoted by T. ADC This represents the interval / period between two consecutive analog-to-digital conversions (sampling instants). The load voltage of the load can be expressed as follows: Figure 1 V in Load Rate 1 / T ADC It can be called the sampling frequency of an analog-to-digital converter (ADC) or the ADC frequency / rate, and its unit is (samples per second) or Hz.

[0053] The switching circuit 120 is controlled by pulse width modulation signals SP1-SP4 generated by the pulse width modulation controller 110, and is used to switch at 1 / T DC-DC The rate generates current pulses flowing through inductor L1 to perform DC-DC operation. Rate 1 / T DC-DC This can be referred to as DC-to-DC operating frequency / rate, and T. DC-DC This represents the length of a DC-to-DC cycle or a DC-to-DC cycle. In this application, performing a DC-to-DC operation means generating a current pulse flowing through inductor L1, and at a DC-to-DC operation rate of 1 / T. DC-DC Generating current pulses means that each current pulse occurs within one DC-DC cycle T. DC-DC Completed within the specified time.

[0054] In this application, due to the compactness of the inductor and the power consumption of the analog-to-digital converter, the DC-DC operation rate of the switching circuit (e.g., 120) is higher than that of the analog-to-digital converter, as detailed below.

[0055] Regarding the reasons for inductor compactness, in order to reduce the size of inductor L1 to achieve circuit compactness and reduce peak current to reduce conduction losses, it is generally desirable to increase the DC-DC operating rate. For example, for the switching circuit 120 based on mainstream semiconductor processes, it is feasible to design and operate at a DC-DC operating rate of around 3MHz. Therefore, from the perspective of power efficiency and compactness of the drive circuit 10, it is feasible and ideal to configure the switching circuit 120 to operate at a high DC-DC operating rate (e.g., 3.072MHz), but it is not limited to this.

[0056] On the other hand, regarding the reasons for the power consumption of analog-to-digital converters (ADCs), the power consumed by an ADC is related to its resolution and conversion rate: the higher the resolution, the higher the power consumption; the higher the conversion rate, the higher the power consumption. In sound generation applications, the bandwidth of a raw audio input signal is typically limited to the human audible frequencies between 16.5 Hz and 22 kHz. For such a bandwidth-limited input, increasing the sampling / conversion rate (i.e., the ADC speed) of the ADC to the range of 3 MHz or as high as the DC-DC operation speed offers little benefit. That is, from the perspective of reducing ADC power consumption, the ADC speed can be reduced to (e.g., several times) below the DC-DC operation speed.

[0057] In one embodiment, the switching circuit 120 may operate at a DC-DC operating rate of 3.072 MHz or 1.536 MHz, while the analog-to-digital converter 130 may operate at a lower analog-to-digital converter frequency such as 384 kHz or 768 kHz. In this case, one analog-to-digital converter cycle may comprise multiple DC-DC cycles (e.g., 4 or 8) of the switching circuit 120. In this application, the analog-to-digital converter cycle T... AD (The first length) should be at least longer than the DC-DC cycle T. DC-DC (The second length) is twice the length of (the second length).

[0058] Illustratively, Figure 2 This demonstrates the driving circuit 10 at an analog-to-digital converter frequency of 1 / T. ADC DC-to-DC operation frequency is 1 / T DC-DC The specific operation. With the analog-to-digital converter frequency at 384kHz and the DC-to-DC operating frequency at 1.536MHz, the analog-to-digital converter period T... ADC For T ADC =4TDC-DC In other words, the analog-to-digital converter period T ADC It can be divided into four time slots. Three of the four time slots can be used for DC-DC operation, and one or the last time slot can be used to perform analog-to-digital conversion. Figure 2 The middle label is "ADC slot".

[0059] exist Figure 2 The diagram shows the inductor / conduction current I used to perform a single DC-to-DC operation. L Pulse Width Modulation Signal SP InFlux and SP DeFlux The waveform of the current I. L This represents the magnitude of the current flowing through inductor L1, which is independent of the current direction. In other words, I... L This can represent the inductor / conduction current flowing from the first terminal of inductor L1 (connected to switches T1-T2) to the second terminal of inductor L1 (connected to switches T3-T4) for charging operations, or the current flowing from the second terminal to the first terminal for discharging operations.

[0060] like Figure 2 As shown, the current pulse CP originates from I. L Starting from the moment when I = 0, the current I flows through... L Increased ascending segment / interval T R , to reach I L =I peak A peak current, experiencing current I L The decreasing descending segment / interval, and in I L The period ends when the value equals 0. The rising segment / interval T... R This corresponds to the flux increase (InFlux) stage of DC-to-DC operation, while T F This corresponds to a flux reduction (DeFlux) stage in DC-to-DC operation. Please note that... Figure 2 As shown, the current pulse CP is completed within one of the DC-DC cycles, spanning T. DC-DC A time window, also referred to as: the switching circuit 120 operates at a DC-to-DC rate of 1 / T. DC-DC A current pulse CP is generated.

[0061] For ease of explanation, Figure 2 The current pulse CP in the diagram is represented as a triangle. In reality, I... L =0 and I L =I peak Current I between L The waveform may deviate slightly from a straight line, but can be approximated as linear or straight, especially when the interval T... R / T F(or pulse width modulation signal SP) InFlux / SP DeFlux The pulse width is small enough.

[0062] Pulse Width Modulation Signal SP InFlux Two of the pulse width modulation signals SP1-SP4 can be used in the flux increase phase, and the pulse width modulation signal SP... DeFlux Two of the pulse width modulation signals SP1-SP4 can be used for the flux reduction phase. For example, the DC-to-DC operation of the switching circuit 10 taught in U.S. Patent Publication No. 11,336,182 can be briefly described as follows. During one analog-to-digital converter cycle T of the charging operation... ADC Internal, pulse width modulation signal SP InFlux It can be applied to switches, such as T1 and T4 (i.e., SP1 = SP4 = SP). InFlux This is to convert the electrical energy stored in the voltage source 11 into the magnetic flux energy of the inductor L1 during the magnetic flux increase phase, and the pulse width modulation signal SP DeFlux It can be applied to switches, such as T2 and T3 (i.e., SP2 = SP3 = SP). DeFlux This allows the magnetic flux energy stored in inductor L1 to be converted into electrical energy in the load CL during the flux reduction phase. During one analog-to-digital converter cycle of the discharge operation, the pulse width modulation signal SP... InFlux It can be applied to switches, such as T2 and T3 (i.e., SP2 = SP3 = SP). InFlux This is to convert the electrical energy stored in the load CL into magnetic flux energy stored in the inductor L1 during the flux increase phase, and the pulse width modulation signal SP... DeFlux It can be applied to switches, such as T1 and T4 (i.e., SP1 = SP4 = SP). DeFlux This allows the magnetic flux energy stored in inductor L1 to be converted into electrical energy in voltage source 11 during the flux reduction phase. Further details of DC-DC operation can be found in U.S. Patent Publication No. 11,336,182.

[0063] When the switching circuit 10 performs a charging operation Figure 2 The area of ​​the shaded region below the falling segment of the current pulse CP (i.e., the area of ​​the right half-triangle of the shaded region within the waveform of the current pulse CP) is represented by ΔQ. F This represents the amount of charge injected / transferred to the capacitive load CL during the charging operation. When the switching circuit 10 performs a discharging operation... Figure 2 The area of ​​the blank region below the rising segment of the current pulse CP (i.e., the area of ​​the blank left half-triangle within the waveform of the current pulse CP) is represented by ΔQ. RThis indicates the amount of charge recovered / transferred from the capacitive load CL during the discharge operation.

[0064] The amount of charge transferred to / from the capacitive load CL (usually denoted as ΔQ) will result in a voltage change / voltage difference (denoted as ΔV). Load The larger the charge quantity ΔQ, the greater the voltage change / voltage difference ΔV. Load The larger the value, the greater the relationship can be expressed as ΔQ / CL=ΔV. Load The charge quantity ΔQ can be modulated by the pulse width modulation signal SP. InFlux / SP DeFlux The pulse width is determined by the interval T R / T F Controlled. If during the analog-to-digital converter cycle T ADC If there is only a single current pulse CP and a large amount of charge is required, a high peak current I will be generated. peak .

[0065] However, since P∝I 2 R, a higher peak current leads to a rapidly rising conduction loss due to the power consumed by the current flowing through the switch, which can be achieved by having a conduction current group R ON It is implemented using a metal-oxide-semiconductor field-effect transistor (MOSFET).

[0066] Alternatively, to minimize high conduction losses, a method can be used within one analog-to-digital converter cycle T. ADC Multiple pulses (CP) are generated internally to transfer the required amount of charge. For example, in... Figure 3 In one analog-to-digital converter cycle T ADC Three (alternative) current pulses CP' are generated internally, each of which also occurs within a DC-to-DC cycle T. DC-DC Complete within [time period]. If Figure 3 The current generation scheme is designed to achieve (basically) the same as Figure 2 The same ΔV in Load Or the same ΔQ (e.g., ΔQ) R =3ΔQ R 'and / or ΔQ F =3ΔQ F '), Figure 3 Peak current I in peak The proposed solution may be smaller than ' Figure 2 Therefore, the solution in the middle, and Figure 2 Compared to the previous solution, conduction losses are reduced. Specifically, Figure 3 The peak current Ipeak' in the scheme is Figure 2 This reduces the conduction loss to one-third of the original solution, thereby lowering it to [a certain value]. Figure 2 Scheme 3 (1 / 3) 2 =1 / 3 times.

[0067] Besides conduction losses, switching losses are another type of energy consumed (or dissipated) in a DC-to-DC switching circuit, such as switching circuit 120. This is related to the on-resistance R of the metal-oxide-semiconductor field-effect transistor acting as the switch. ON The related conduction losses are different, while the switching losses are related to the gate capacitance C of the metal-oxide-semiconductor field-effect transistor. G (C G =C GS +C GD This is charge / discharge related and remains essentially constant with each switch-on / off cycle. Note that this is due to the gate capacitance C. G It is proportional to the size / area of ​​a metal-oxide-semiconductor field-effect transistor, and therefore has a larger Ro and a lower Ro. ON Metal-oxide-semiconductor field-effect transistors may produce lower conduction losses, but have higher switching losses.

[0068] Specifically, for half of the DC-DC operation (corresponding to the flux increase or flux decrease phase), the conduction loss of half of the DC-DC operation can be expressed as: Where t PWM It can represent T R (used during the flux increase phase) or T F (For the flux reduction phase). For a predetermined embodiment of the DC-DC / switching circuit 120, the conduction loss W... CND It can be represented as W CND ∝t PWM 3 Therefore, the conduction loss W for each DC-to-DC cycle operation... CND With t PWM 3 Related, while switching loss W SW With t PWM Irrelevant.

[0069] By controlling the conduction loss W CND and switching loss W SWBy balancing these factors, the pulse width modulation controller 110 can control the switching circuit to generate an appropriate number of current pulses within the analog-to-digital converter cycle to minimize conduction and switching losses. Generally, more current pulses are needed when injecting or recovering high charge from a capacitive load CL, while fewer current pulses are preferable when injecting or recovering low charge from the capacitive load CL. Therefore, the pulse width modulation controller 110 can determine the number of current pulses in the analog-to-digital converter cycle based on the amount of charge that needs to be transferred to or from the capacitive load CL via the switching circuit 120.

[0070] Simply put, in T ADC = (N+1)·T DC-DC Or, in a scheme where the DC-to-DC operation rate is (N+1) times the analog-to-digital converter rate, for a given analog-to-digital converter cycle T... ADC A certain amount of charge ΔQ transferred internally can determine / optimize the number of current pulses K, such that within one analog-to-digital converter cycle T... ADC The goal is to minimize the conduction and switching losses of generating K current pulses within the system, where K ≤ N and K and N are integers.

[0071] Figure 4 The analog-to-digital converter period T of this application ADC A pulse control scheme within the system. For example... Figure 4 As shown, the number of current pulses can be adjusted according to the amount of charge corresponding to the current flowing in the switching circuit 120. In one embodiment, the analog-to-digital converter can operate at 768 kHz, therefore the analog-to-digital converter period T ADC The length is 1 / 768 kHz ≈ 1.302 μs. The switching circuit 120 can operate in DC-DC cycles T. DC-DC Its length is 1 / (4.768kHz) = 1 / 3.072kHz ≈ 325.52ns. In this case, the analog-to-digital converter period T ADC Includes four DC-DC cycles T DC-DC .

[0072] Figure 4 This describes three possible implementations or embodiments under different operating frequency configurations. In the first implementation (shown...), Figure 4 (Leftmost), in an analog-to-digital converter cycle T ADC Only one current pulse is generated internally. As the required charge increases, the width of the pulse width modulation pulse generated by the pulse width modulation controller 110 increases, resulting in a higher conduction power loss W. CND With T PWM 3The rate of increase is rapid. Therefore, in order to reduce conduction losses, when the required charge exceeds a first quantity threshold, it may be necessary to increase the conduction rate during the analog-to-digital converter cycle T. ADC The transfer of charge ΔQ is accomplished through one or more current pulses. For example, in the second embodiment (shown in...) Figure 4 (in the middle), during the analog-to-digital converter cycle T ADC Two current pulses with relatively low peak currents are generated internally. Note that in the second embodiment, the total conduction loss W consumed by the two current pulses is... CND It may be due to switching losses W SW The reduction comes at a cost. The conduction loss W is reduced by generating two current pulses. CND Greater than the incremental switching loss W caused by the additional current pulse. SW In this case, the second implementation method is preferable to the first implementation method.

[0073] Similarly, when the required charge increases further to a value greater than a second quantity threshold, it is best to adjust the charge during the analog-to-digital converter cycle T. ADC Three current pulses are generated internally, such as Figure 4 The third implementation shown on the far right further reduces conduction losses, at the cost of switching losses W. SW Increased to three times.

[0074] Conversely, when the required charge ΔQ is lower than the aforementioned second or first quantity threshold, the number of current pulses can be reduced to decrease switching losses W. SW This reduces the total energy loss W of the DC-to-DC switching circuit 120. CND +W SW .

[0075] Therefore, based on the total charge ΔQ (which can be determined from the expected / determined voltage difference of the capacitive load CL), the drive circuit 10 can determine the analog-to-digital converter period T. ADC The number of current pulses included is determined to minimize the total power consumption caused by switching losses and conduction losses.

[0076] Furthermore, the total charge can be determined by the expected voltage difference over one analog-to-digital converter cycle. According to the well-known formula Q = CV (Formula 1), the required charge ΔQ (r) That is, in one analog-to-digital converter cycle T ADC The amount of charge that needs to be transferred to the capacitive load CL / the amount of charge transferred from the capacitive load CL depends on an expected voltage difference ΔV. (int) Expected voltage difference ΔV (int) It can be obtained from an input signal IN and a feedback signal FB received by the pulse width modulation controller 110. Specifically, the expected voltage difference ΔV(int) Based on period T ADC The difference between the corresponding input signal IN and the feedback signal FB determines the value. Specifically, ΔQ (r) =C CL ·ΔV (int) C CL express Figure 1 The capacitance value of the load CL is shown.

[0077] In other words, in one analog-to-digital converter cycle T ADC Internally, when the difference between the input signal IN and the feedback signal FB is greater than a threshold value TH, the pulse width modulation controller 110 can control the switching circuit 120 to generate more than one current pulse. Furthermore, when the difference between the input signal IN and the feedback signal FB is greater than a first threshold value TH1, the pulse width modulation controller 110 can decide to increase the number of current pulses K and control the switching circuit 120 to operate at a DC-DC rate 1 / T. DC-DC A current pulse CP is generated flowing through inductor L1, and the number of current pulses after the increase is K. + (where K) + >K). On the other hand, when the difference between the input signal IN and the feedback signal FB is less than a second threshold value TH2, the pulse width modulation controller 110 can decide to reduce the number of current pulses K and control the switching circuit 120 to operate at a DC-DC rate 1 / T. DC-DC A current pulse CP is generated flowing through inductor L1, and the reduced number of current pulses is K. - (where K) - <K)。

[0078] In one embodiment, the load CL here can be a capacitive speaker load, such as a piezoelectrically driven speaker. The drive circuit 10 can receive an input signal IN generated according to an original audio signal in an audible frequency band (e.g., between 16.5 Hz and 22 kHz). The drive circuit drives the capacitive speaker load according to the input signal IN, such that the drive circuit 10 drives an output voltage V of the capacitive speaker load. Load It is substantially proportional to the input signal IN. The substantial proportionality of a signal a to a signal b may mean that ||a(t) - c·b(t)|| 2 ≤ε, where ||s(t)|| 2 It can be represented as an energy of any signal s(t), where a(t) and b(t) represent the time-varying functions of signals a and b, respectively, c represents a constant value that can be positive or negative, and ε represents some positive decimal, such as 10. -1 10 -2 10 -3 wait.

[0079] The threshold values ​​TH, TH1, and TH2 mentioned above are determined based on actual operating conditions. In some cases, the capacitance value C of the capacitive load CL... CL It can be relative to the load voltage V Load And it changes. For example, due to the properties of piezoelectric materials, the dielectric constant or capacitance value (C) of a piezoelectrically actuated loudspeaker changes. CL ) will change with the voltage (V) applied to it Load It decreases as the load voltage V increases. Generally, for a given load voltage V... Load Expected voltage difference ΔV (int) The larger the value, the larger the current pulse count K. Conversely, for a given load voltage V... Load Expected voltage difference ΔV (int) The smaller the value, the smaller the number of current pulses K.

[0080] In one embodiment, the input signal IN can be a digital signal, corresponding to a sampling rate and an analog-to-digital converter rate of 1 / T. ADC The same applies. For example, in one embodiment, for an analog-to-digital converter rate of 384 kHz or 768 kHz, an input signal IN can be generated from an input digital audio signal having a sampling rate of 48 kHz through an up-sampling process.

[0081] The operation of the drive circuit 10 can be summarized as follows: Figure 5 The process shown is 50. Figure 5 Includes the following steps:

[0082] Step 502: Measure the load voltage V at the analog-to-digital converter rate. Load Perform analog-to-digital conversion.

[0083] Step 504: Generate at least one current pulse CP flowing through inductor L1 at a DC-to-DC operating rate.

[0084] In process 50, the DC-DC operating rate is typically greater than the analog-to-digital converter (ADC) rate. The ratio of the DC-DC operating rate to the ADC rate is not limited. To reduce conduction losses, it is recommended to retain more than one DC-DC cycle within an ADC cycle to unload the required charge. That is, in this application, the ADC cycle T... ADC It is recommended to be at least longer than the DC-DC cycle T. DC-DC Twice as much.

[0085] The applicant's U.S. Patent Publication No. 11,271,480 and Application No. 18 / 048,852 teach a pulse width modulation controller that receives an input signal IN and a feedback signal FB, obtains an address based on the input signal IN and the feedback signal FB, retrieves a pulse width control code (PWCC) from a lookup table (LUT) stored in a memory based on the address, and generates a pulse width modulation signal (e.g., PWCC) with a pulse width corresponding to the PWCC. Figure 2 SP shown InFlux or SP DeFlux This allows the pulse width modulation signal corresponding to the pulse width control code to control the operation of the switching circuit (or the bidirectional circuit in both applications).

[0086] Generally, a pulse width modulation controller can obtain a first pulse width control code to generate a pulse width modulation signal SP for the flux increase phase. InFlux A second pulse width control code is used to generate a pulse width modulation signal SP for the flux reduction phase. DeFlux Because the current paths differ between the flux increase and flux decrease phases, the first pulse width control code for the flux increase phase is typically different from the second pulse width control code for the flux decrease phase.

[0087] In one embodiment, the pulse width modulation controller may access a first lookup table to obtain an in-flux-charging PWCC to generate a pulse width modulation signal SP for charging operation. InFlux And access a second lookup table to obtain an outflow discharge pulse width control code (DeFlux-discharging PWCC) to generate a pulse width modulation signal SP for discharge operation. InFlux In one embodiment, an inflow charging current and an outflow discharging current can travel through the same path (e.g., through...). Figure 1 Switches T1 and T4 in the circuit, but with opposite current directions; and a charging current (DeFlux-charging current) and a discharging current (InFlux-discharging current) have the same current path (e.g., flowing through...). Figure 1 Switches T2 and T3 in the circuit (but with opposite current directions). In this case, in one embodiment, the pulse width modulation controller can access a second lookup table to obtain an outgoing charging pulse width control code to generate a pulse width modulation signal SP for charging operation. DeFluxIt also accesses the first lookup table to obtain an outflow discharge pulse width control code to generate a pulse width modulation signal SP for discharge operation. DeFlux .

[0088] U.S. Patent Application No. 18 / 048,852 further teaches that pulse width control codes can be acquired and / or updated while the drive circuit is running. The concept of using control codes to specify the number of current pulses K can be incorporated into this application.

[0089] For example, Figure 6 This is a flowchart of a process 60 according to an embodiment of the present invention. Process 60 can be implemented by the driving circuit 10 of this application. Figure 6 As shown, process 60 includes the following steps:

[0090] Step 602: Receive the input signal and the feedback signal from the analog-to-digital converter.

[0091] Step 604: Obtain an Effective Pulse Width Control Code (EPWCC) based on the input signal and feedback signal, wherein the Effective Pulse Width Control Code includes a Pulse Width Control Code (PWCC) and a Number Control Code (NCC).

[0092] Step 606: Generate at least one current pulse according to the effective pulse width control code.

[0093] According to process 60, the pulse width modulation controller 110 can receive the input signal IN and the feedback signal FB from the analog-to-digital converter. Similar to U.S. Patent Publication No. 11,271,480 and U.S. Patent Application No. 18 / 048,852, the pulse width modulation controller 110 determines a table address based on the input signal IN and the feedback signal FB, and obtains the valid pulse width control code by referring to a lookup table (LUT) based on the table address. In addition to the pulse width control code, the valid pulse width control code in this application also includes a quantity control code, used to specify an analog-to-digital converter period T. ADC The number of current pulses K within the circuit. Therefore, the pulse width modulation controller 110 can generate a pulse width modulation signal (e.g., based on the effective pulse width control code) according to the effective pulse width control code. Figure 2 or Figure 3 SP shown InFlux or SP DeFluxThe pulse width modulation signal in one of the analog-to-digital converter cycles contains K pulses (where K is determined based on a quantity control code), and each pulse has a pulse width (where the pulse width is determined based on a pulse width control code).

[0094] Figure 7 This is an exemplary data field for the effective pulse width control code in an embodiment of the present invention. In one embodiment, the effective pulse width control code may be a nine-bit data field, where seven bits are used to store the value of the pulse width control code and two bits are used to store the value of the quantity control code. The two-bit quantity control code indicates the number of (current) pulses generated in one analog-to-digital converter cycle. Assume T... ADC =4T DC-DC An analog-to-digital converter (ADC) cycle can contain up to three DC-to-DC cycles for DC-to-DC operation and one ADC time slot. For example... Figure 7 As shown, a decimal value of 0 in the quantity control code indicates that there is only one pulse in the analog-to-digital converter cycle, a decimal value of 1 in the quantity control code indicates that there are two pulses in the analog-to-digital converter cycle, and a decimal value of 2 in the quantity control code indicates that there are three pulses in the analog-to-digital converter cycle.

[0095] To reduce conduction losses, the quantity control code can be increased when the pulse width control code is greater than or equal to a first value. Once the quantity control code is increased, the original pulse width control code can be reduced to a second (smaller) value. In one embodiment, when the pulse width control code is greater than or equal to the first value (e.g., decimal 107), to reduce conduction losses, the original current pulse (corresponding to a pulse width control code equal to decimal 107) can be replaced by two smaller current pulses corresponding to a pulse width control code equal to the second value (smaller, e.g., decimal 85). See the left side of Figure 8 and / or Figure 4 The transition from the far left to the middle.

[0096] On the other hand, when multiple current pulses are generated, to avoid switching losses, the quantity control code can be reduced when the pulse width control code of the multiple current pulses is less than or equal to a third value. Once the quantity control code is reduced, the original pulse width control code (belonging to or corresponding to multiple current pulses) can be enhanced to a fourth value for the less enhanced current pulse. In one embodiment, when the pulse width control code is less than or equal to a third value (e.g., decimal 81) and two current pulses are generated, to avoid switching losses, the original two weaker current pulses (corresponding to a pulse width control code equal to decimal 81) can be replaced by an enhanced / stronger current pulse corresponding to a pulse width control code equal to a fourth value (larger, e.g., decimal 103), such as... Figure 8 The right part and / or Figure 4 The transition from the middle to the far left.

[0097] In U.S. Patent Application No. 18 / 048,852, the pulse width control code can be updated during the operation of the drive circuit. In this application, the quantity control code can be updated along with the pulse width control code; that is, the valid pulse width control code can be updated during the operation of the drive circuit. In other words, the pulse width modulation controller 110 can receive a first feedback signal corresponding to the initial stage of an analog-to-digital converter cycle (or the current analog-to-digital converter cycle), obtain an address based on the input signal IN and the first feedback signal FB1, retrieve a valid pulse width control code from a lookup table (LUT) stored in memory based on the address, and generate a pulse width modulation signal (e.g., SP) corresponding to the valid pulse width control code. InFlux or SP DeFlux The switching circuit performs DC-DC operation, receives a second feedback signal FB2 at the end of a corresponding analog-to-digital converter cycle (or the current analog-to-digital converter cycle), updates the effective pulse width control code based on the first feedback signal FB1 and the second feedback signal FB2, and stores the updated effective pulse width control code back into a lookup table in memory. Here, the first feedback signal FB1 represents the load voltage V before the DC-DC operation is performed in the current analog-to-digital converter cycle. Load Furthermore, the second feedback signal FB2 represents the load voltage after the DC-to-DC operation is performed corresponding to the current analog-to-digital converter cycle.

[0098] During update operations where the (effective) pulse width control code shows an upward trend, such as Figure 8 As shown in the left part, when a raw pulse width control code (e.g., corresponding to a single current pulse, such as...) Figure 4 As shown in the leftmost diagram, when the quantity control code (e.g., 0) rises to a first value (e.g., decimal 107), the pulse width control code can decrease to a second value (e.g., decimal 85), and the quantity control code increases by 1 (e.g., the quantity control code equals 1). In this case, to reduce conduction losses, two AC current pulses with pulse widths corresponding to the pulse width control code 85 can be generated, as follows: Figure 8 As shown in the left part of the middle section, or as... Figure 4 The transition from leftmost to middle is shown in the diagram. The updated valid pulse width control code (including, for example, an increased quantity control code equal to 1 and a decreased pulse width control code equal to 85) will be stored back in the memory lookup table.

[0099] During update operations where the (effective) pulse width control code exhibits a decreasing trend, such as Figure 8 As shown in the right part, when a raw pulse width control code (e.g., corresponding to two current pulses, such as...) is used... Figure 4As shown in the middle, when the quantity control code (e.g., equal to 1) decreases to a third value (e.g., decimal 81), the pulse width control code can be increased to a fourth value (e.g., decimal 103), and the quantity control code decreases by 1 (e.g., the quantity control code equals 0). In this case, to avoid switching losses, a single AC current pulse with a pulse width corresponding to the pulse width control code 103 can be generated, such as... Figure 8 As shown in the right part, or as Figure 4 The transition from the middle to the leftmost part is shown. The updated valid pulse width control code (including, for example, a reduced quantity control code equal to 0 and an enhanced pulse width control code equal to 103) will be stored back in the memory lookup table.

[0100] Please note that the first, second, third, and fourth values ​​mentioned above can be determined based on the actual situation, but are not limited to certain values. For example, it may include hysteresis of the second and third values, or hysteresis of the first and fourth values, but is not limited to these.

[0101] Consider a single analog-to-digital converter cycle T ADC Multiple current pulses are generated internally. To achieve a balance between conduction and switching losses, the charge carried by these current pulses can be evenly distributed along their polarity. The updated pulse width control code can be applied to the analog-to-digital converter cycle T. ADC All multiple current pulses within, meaning multiple current pulses correspond to the same pulse width control code (e.g., for SP). InFlux ), but it is not limited to this.

[0102] In one embodiment, the pulse width modulation controller can control the switching circuit within one analog-to-digital converter cycle T. ADC At least one first current pulse CP1 and at least one second current pulse CP2 are generated internally, wherein the first current pulse CP1 corresponds to PWCC1 and the second current pulse CP2 corresponds to PWCC2, and PWCC2 ≠ PWCC1. To distribute the charge as uniformly as possible, in one embodiment, PWCC1 can satisfy PWCC1 = PWCC2 + 1. Here, PWCC1 / PWCC2 determines the pulse width modulation signal SP of the current pulses CP1 / CP2. InFlux The pulse width controls the rise interval of the control current pulses CP1 / CP2. In this example, the rise interval of the first current pulse CP1 differs from the rise interval of the second current pulse CP2 by one unit of pulse width control code resolution. Furthermore, a quantity of the first current pulse CP1 can be recorded as a dither control code (DCC) and recorded together with the effective pulse width control code.

[0103] Figure 9 This is an exemplary data field of the effective pulse width control code according to another embodiment of the present invention. In this embodiment, the effective pulse width control code further includes a jitter control code. The jitter control code indicates the number of first current pulses CP1.

[0104] For example, suppose the pulse width control code is equal to 87, the quantity control code indicates four pulses, and the jitter control code indicates the number of pulses with increasing widths. If the jitter control code is equal to 0, all pulses of the pulse width modulation signal can have the same width corresponding to the value 87. If the jitter control code is equal to 1, one of the four pulses can have a width corresponding to the value 88. That is, the pulse width control code values ​​for these four pulses become {87, 87, 87, 88}. If the jitter control code is equal to 2, the pulse width control code values ​​for these four pulses can become {87, 87, 88, 88}; if the jitter control code is equal to 3, the pulse width control code values ​​for these four pulses can become {87, 88, 88, 88}. The next level is {88, 88, 88, 88}, which can be achieved by modifying the pulse width control code to 88 and setting the jitter control code to 0. The above operation can be easily achieved by treating the jitter control code as the binary fractions of the pulse width control code, thereby achieving finer voltage difference resolution within a single analog-to-digital converter cycle.

[0105] Similar to the teachings of U.S. Patent Publication No. 11,271,480 and U.S. Patent Application No. 18 / 048,852, the pulse width modulation controller 110 may include a memory A04, a digital-to-analog converter (DAC) A06, a waveform generator A08, and a comparator A10, such as Figure 10 As shown. Waveform generator A08 is used to generate a type of sawtooth signal (with or without flat ends) S. saw The memory stores a first lookup table A04_1 and a second lookup table A04_2. The first lookup table A04_1 is used for charging operations, while the second lookup table A04_2 is used for discharging operations. (Valid) Pulse width control codes can be retrieved from memory A04 and output to a digital-to-analog converter A06. The digital-to-analog converter A06 converts the pulse width control codes into an analog voltage V. A Comparator A10 is used to compare the sawtooth-like signal S. saw With analog voltage V A And generate a comparison result as a pulse width modulation signal (which can be SP). InFlux or SP DeFluxIts pulse width corresponds to the pulse width control code.

[0106] Please note, refer back Figure 2 or Figure 3 During the charging operation / charging cycle, the voltage change across the load CL occurs in the second (DeFlux) phase or the falling interval T. F During the charging / discharging cycle, however, the voltage change across the load CL occurs during the first (InFlux) phase. In other words, the effect of the timing of the current pulses on the voltage across the load CL differs between the charging and discharging cycles. When the drive circuit 10 is applied to a density coding system (e.g., signal density modulation (SDM) or pulse density modulation (PDM) system), it is sensitive not only to the signal level but also to the timing of the level maintenance. This timing difference in the current pulse timing (between the charging current pulse and the discharging current pulse) can lead to errors in signal density modulation and degrade the signal-to-quantization-noise ratio (SQNR) performance.

[0107] To minimize such timing errors, in one embodiment, the timing of the discharge cycle can be delayed relative to the timing of the charging cycle, and vice versa. In other words, a timing difference can be applied between the current pulses used for the charging operation and the current pulses used for the discharging operation. In one embodiment, this delay (or timing difference) can be achieved by increasing the delay of the start-up time of the waveform generator A08, but is not limited thereto. In one embodiment, this delay can be achieved by applying a time offset (delay) (relative to the charging operation) to the start-up time of the current pulses for the discharging operation. The amount of delay can be fixed or can be related to / proportional to the pulse width control code, and the amount of delay can also include a random number to break timing error patterns.

[0108] In other words, to minimize timing errors, a pulse width modulation (PWM) controller can control the switching circuit to generate a current pulse CP with a delay relative to the envelope-non-changing analog-to-digital converter (ADC) cycle and corresponding to a discharge operation, where there is no such delay in the ADC cycle corresponding to a charging operation, and vice versa. In one embodiment, the delay can be 0.5n times a clock cycle, where a length of the clock cycle can be T. DC-DC / M. Here, n and M are both integers (e.g., n = 1, 2 or 3 and M = 12, 18 or 32, but not limited to these).

[0109] For details on signal density modulation, please refer to U.S. Patent Application No. 17 / 452,403. For details on pulse density modulation, please refer to U.S. Patent Application No. 17 / 452,403. For the sake of brevity, these details will not be repeated here.

[0110] In summary, this application utilizes the fact that the DC-DC operation rate is higher than that of the analog-to-digital converter (ADC) rate, reserves more time slots, makes the number of current pulses within an ADC cycle adjustable, and minimizes power consumption by considering conduction losses and switching losses.

[0111] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A method for reducing conduction losses and switching losses in a drive circuit, characterized in that, For a drive circuit and a switching circuit, the drive circuit including an analog-to-digital converter, the switching circuit including an inductor coupled to a load, the method includes: Perform an analog-to-digital conversion on a load voltage of the load at a first rate; and generate at least one current pulse flowing through the inductor at a second rate; Each of the at least one current pulse is completed within a second cycle corresponding to the second rate; All of the at least one current pulse is completed within a first cycle corresponding to the first rate; Wherein a first length of the first period is twice as long as a second length of the second period; The method further includes: It receives an input signal and a feedback signal from the analog-to-digital converter; When the difference between the input signal and the feedback signal is greater than a first threshold value, the current pulse count is increased; and During the first cycle, a plurality of current pulses are generated at the second rate, the plurality of current pulses having an increased number of current pulses.

2. A method for reducing conduction losses and switching losses in a drive circuit, characterized in that, For a drive circuit and a switching circuit, the drive circuit including an analog-to-digital converter, the switching circuit including an inductor coupled to a load, the method includes: Perform an analog-to-digital conversion on a load voltage of the load at a first rate; and generate at least one current pulse flowing through the inductor at a second rate; Each of the at least one current pulse is completed within a second cycle corresponding to the second rate; All of the at least one current pulse is completed within a first cycle corresponding to the first rate; Wherein a first length of the first period is twice as long as a second length of the second period; The method further includes: It receives an input signal and a feedback signal from the analog-to-digital converter; When the difference between the input signal and the feedback signal is less than a second threshold value, the number of current pulses is reduced; and The at least one current pulse is generated at the second rate during the first cycle, the at least one current pulse having a reduced number of current pulses.

3. A method for reducing conduction losses and switching losses in a drive circuit, characterized in that, For a drive circuit and a switching circuit, the drive circuit including an analog-to-digital converter, the switching circuit including an inductor coupled to a load, the method includes: Perform an analog-to-digital conversion on a load voltage of the load at a first rate; and generate at least one current pulse flowing through the inductor at a second rate; Each of the at least one current pulse is completed within a second cycle corresponding to the second rate; All of the at least one current pulse is completed within a first cycle corresponding to the first rate; Wherein a first length of the first period is twice as long as a second length of the second period; The method further includes: It receives an input signal and a feedback signal from the analog-to-digital converter; Based on the feedback signal and the input signal, a valid pulse width control code is obtained from a lookup table stored in a memory, wherein the valid pulse width control code includes a pulse width control code and a quantity control code; and The at least one current pulse is generated according to the effective pulse width control code; Receive a first feedback signal corresponding to the start of the first cycle and a second feedback signal corresponding to the end of the first cycle; Update the effective pulse width control code based on the first feedback signal and the second feedback signal; and The updated effective pulse width control code is stored back into the lookup table of the memory; The step of updating the effective pulse width control code includes: When the pulse width control code increases to a value greater than or equal to a first value, the quantity control code is increased; and When the quantity control code increases, the increased pulse width control code is replaced by a decreased pulse width control code, wherein the decreased pulse width control code has a second value that is less than the first value; The step of storing the updated effective pulse width control code back into the lookup table of the memory includes: The increased quantity control code and the decreased pulse width control code are stored back into the lookup table of the memory.

4. A method for reducing conduction losses and switching losses in a drive circuit, characterized in that, For a drive circuit and a switching circuit, the drive circuit including an analog-to-digital converter, the switching circuit including an inductor coupled to a load, the method includes: Perform an analog-to-digital conversion on a load voltage of the load at a first rate; and generate at least one current pulse flowing through the inductor at a second rate; Each of the at least one current pulse is completed within a second cycle corresponding to the second rate; All of the at least one current pulse is completed within a first cycle corresponding to the first rate; Wherein a first length of the first period is twice as long as a second length of the second period; The method further includes: It receives an input signal and a feedback signal from the analog-to-digital converter; Based on the feedback signal and the input signal, a valid pulse width control code is obtained from a lookup table stored in a memory, wherein the valid pulse width control code includes a pulse width control code and a quantity control code; and The at least one current pulse is generated according to the effective pulse width control code; Receive a first feedback signal corresponding to the start of the first cycle and a second feedback signal corresponding to the end of the first cycle; Update the effective pulse width control code based on the first feedback signal and the second feedback signal; and The updated effective pulse width control code is stored back into the lookup table of the memory; The step of updating the effective pulse width control code includes: When the pulse width control code decreases to less than or equal to a third value, the quantity control code is reduced; and When the quantity control code decreases, the decreased pulse width control code is replaced with an enhanced pulse width control code, wherein the enhanced pulse width control code has a fourth value greater than the third value; and The step of storing the updated effective pulse width control code back into the lookup table of the memory includes: The reduced quantity control code and the enhanced pulse width control code are stored back into the lookup table of the memory.

5. The method according to claim 3 or 4, characterized in that, The step of generating the at least one current pulse according to the effective pulse width control code includes: Generate a current pulse having a rising interval among the at least one current pulse, wherein the rising interval is determined according to the pulse width control code within the effective pulse width control code; as well as Generate the at least one current pulse having a number of current pulses, wherein the number of current pulses is determined according to the quantity control code within the effective pulse width control code.

6. The method according to claim 3 or 4, characterized in that, The step of generating the current pulse includes: generating a pulse width modulation signal having a pulse width to the switching circuit; The pulse width of the pulse width modulated signal is determined according to the pulse width control code.

7. The method according to any one of claims 1 to 4, characterized in that, Also includes: At least one first current pulse and at least one second current pulse are generated within the first cycle corresponding to the first rate; The first rising interval of the at least one first current pulse is greater than the second rising interval of the at least one second current pulse.

8. The method according to any one of claims 1 to 4, characterized in that, Also includes: The at least one current pulse with a delay is generated within the first cycle corresponding to a discharge operation.

9. A driving circuit for driving a load, characterized in that, The driving circuit includes: An analog-to-digital converter for performing an analog-to-digital conversion on a load voltage of the load at a first rate; A switching circuit, including an inductor coupled to the load, is configured to generate at least one current pulse flowing through the inductor at a second rate; and A pulse width modulation controller is used to receive an input signal and a feedback signal from the analog-to-digital converter; Each of the at least one current pulse is completed within a second cycle corresponding to the second rate; All of the at least one current pulse is completed within a first cycle corresponding to the first rate; Wherein a first length of the first period is twice as long as a second length of the second period; When the difference between the input signal and the feedback signal is greater than a first threshold value, the pulse width modulation controller increases the current pulse count; and The pulse width modulation controller controls the switching circuit to generate a plurality of current pulses at the second rate within the first cycle, the plurality of current pulses having an increased number of current pulses.

10. A driving circuit for driving a load, characterized in that, The driving circuit includes: An analog-to-digital converter for performing an analog-to-digital conversion on a load voltage of the load at a first rate; A switching circuit, including an inductor coupled to the load, is configured to generate at least one current pulse flowing through the inductor at a second rate; and A pulse width modulation controller is used to receive an input signal and a feedback signal from the analog-to-digital converter; Each of the at least one current pulse is completed within a second cycle corresponding to the second rate; All of the at least one current pulse is completed within a first cycle corresponding to the first rate; Wherein a first length of the first period is twice as long as a second length of the second period; When the difference between the input signal and the feedback signal is less than a second threshold value, the pulse width modulation controller reduces the number of current pulses; and The pulse width modulation controller controls the switching circuit to generate the at least one current pulse at the second rate within the first cycle, the at least one current pulse having a reduced number of current pulses.

11. A driving circuit for driving a load, characterized in that, The driving circuit includes: An analog-to-digital converter for performing an analog-to-digital conversion on a load voltage of the load at a first rate; A switching circuit, including an inductor coupled to the load, is used to generate a current flowing through the load at a second rate. At least one current pulse from the sensor; and A pulse width modulation controller is used to receive an input signal and a feedback signal from the analog-to-digital converter; Each of the at least one current pulse is completed within a second cycle corresponding to the second rate; All of the at least one current pulse is completed within a first cycle corresponding to the first rate; Wherein a first length of the first period is twice as long as a second length of the second period; The pulse width modulation controller includes a memory for storing a lookup table; The pulse width modulation controller obtains a valid pulse width control code from the lookup table stored in the memory based on the feedback signal and the input signal. The effective pulse width control code includes a pulse width control code and a quantity control code. The switching circuit generates the at least one current pulse according to the effective pulse width control code; The pulse width modulation controller receives a first feedback signal corresponding to the start of the first cycle and a second feedback signal corresponding to the end of the first cycle; The pulse width modulation controller updates the effective pulse width control code based on the first feedback signal and the second feedback signal. The pulse width modulation controller stores the updated effective pulse width control code back into the lookup table of the memory; During the process of the pulse width modulation controller updating the effective pulse width control code, when the pulse width control code increases to a value greater than or equal to a first value, the pulse width modulation controller increases the quantity control code, and when the quantity control code increases, the pulse width modulation controller replaces the increased pulse width control code with a decreased pulse width control code. The reduced pulse width control code has a second value that is less than the first value; and The pulse width modulation controller stores the increased quantity control code and the decreased pulse width control code back into the lookup table of the memory.

12. A driving circuit for driving a load, characterized in that, The driving circuit includes: An analog-to-digital converter for performing an analog-to-digital conversion on a load voltage of the load at a first rate; A switching circuit, including an inductor coupled to the load, is used to generate a current flowing through the load at a second rate. At least one current pulse from the sensor; and A pulse width modulation controller is used to receive an input signal and a feedback signal from the analog-to-digital converter; Each of the at least one current pulse is completed within a second cycle corresponding to the second rate; All of the at least one current pulse is completed within a first cycle corresponding to the first rate; Wherein a first length of the first period is twice as long as a second length of the second period; The pulse width modulation controller includes a memory for storing a lookup table; The pulse width modulation controller obtains a valid pulse width control code from the lookup table stored in the memory based on the feedback signal and the input signal. The effective pulse width control code includes a pulse width control code and a quantity control code. The switching circuit generates the at least one current pulse according to the effective pulse width control code; The pulse width modulation controller receives a first feedback signal corresponding to the start of the first cycle and a second feedback signal corresponding to the end of the first cycle; The pulse width modulation controller updates the effective pulse width control code based on the first feedback signal and the second feedback signal. The pulse width modulation controller stores the updated effective pulse width control code back into the lookup table of the memory; During the update of the effective pulse width control code by the pulse width modulation controller, when the pulse width control code decreases to less than or equal to a third value, the pulse width modulation controller decreases the quantity control code, and when the quantity control code decreases, the pulse width modulation controller replaces the decreased pulse width control code with an enhanced pulse width control code. The enhanced pulse width control code has a fourth value greater than the third value; and The pulse width modulation controller stores the reduced quantity control code and the enhanced pulse width control code back into the lookup table of the memory.

13. The driving circuit according to claim 11 or 12, characterized in that, The pulse width modulation controller determines a rising interval based on the pulse width control code, and determines the number of current pulses of the at least one current pulse based on the quantity control code; The switching circuit generates a current pulse having the rising interval among the at least one current pulse, and generates the at least one current pulse having the number of current pulses.

14. The driving circuit according to claim 11 or 12, characterized in that, The pulse width modulation controller generates a pulse width modulation signal with a pulse width corresponding to the pulse width control code and sends it to the switching circuit.

15. The driving circuit according to any one of claims 9 to 12, characterized in that, The switching circuit generates at least one first current pulse and at least one second current pulse within the first cycle corresponding to the first rate. The first rising interval of the at least one first current pulse is greater than the second rising interval of the at least one second current pulse.

16. The driving circuit according to claim 11 or 12, characterized in that, The pulse width modulation controller includes: A digital-to-analog converter for converting the pulse width control code into an analog voltage; a waveform generator for generating a sawtooth signal; and A comparator is used to compare the sawtooth-like signal with the analog voltage and generate a comparison result as a pulse width modulated signal having a pulse width corresponding to the pulse width control code.

17. The driving circuit according to any one of claims 9 to 12, characterized in that, The switching circuit includes: A first switch is coupled between a voltage source and a first terminal of the inductor; A second switch is coupled to the first terminal of the inductor; A third switch is coupled between the load and a second terminal of the inductor; and a fourth switch is coupled to the second terminal of the inductor.

18. The driving circuit according to any one of claims 9 to 12, characterized in that, The switching circuit is coupled between the load and a voltage source; During a discharge operation, the switching circuit generates a current flowing to the voltage source.

19. The driving circuit according to any one of claims 9 to 12, characterized in that, The second rate is a multiple of the first rate.

20. The driving circuit according to any one of claims 9 to 12, characterized in that, The load is a capacitive speaker load, the input signal is generated based on an original audio signal within an audible frequency band, and an output of the capacitive speaker load is substantially proportional to the input signal.

21. The driving circuit according to any one of claims 9 to 12, characterized in that, The pulse width modulation controller controls the switching circuit to generate the at least one current pulse with a delay within the first cycle corresponding to a discharge operation.

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