Current limiting indication circuit, chip and electronic equipment

Abstract

The embodiments of the present disclosure provide a current limiting indication circuit, chip, and electronic device, belonging to the field of integrated circuit technology. The current limiting indication circuit includes: a current sampling circuit that generates a first sampling current signal and a second sampling current signal that are multiples of the load current signal based on a load current signal, and provides the first sampling current signal and the second sampling current signal to a current comparison circuit via a first node and a second node, respectively; a reference current source that generates a reference current signal and provides the reference current signal to the current comparison circuit via a first node; the current comparison circuit compares the first sampling current signal with the reference current signal to obtain a first comparison signal, and outputs a current limiting indication signal based on a comparison result of the first comparison signal and a set current signal, and based on a comparison result of the sum of the first comparison signal and the second sampling current signal and the set current signal, wherein the second sampling current signal that is multiples of the load current signal is positively correlated with the current limiting hysteresis.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the technical field of integrated circuits, and in particular to a current limiting indication circuit, a chip, and an electronic device. Background Art

[0002] In current current-limiting indication circuits, when the load current output by the detection circuit exceeds the current-limiting threshold, the closed-loop structure within the circuit provides current-limiting protection. To achieve this early indication of current limiting, an overcurrent indication value smaller than the current-limiting threshold and an overcurrent release value smaller than the overcurrent indication value are required. When the load current reaches the overcurrent indication value, the output current-limiting indication signal is high. When the load current drops to the overcurrent release value, the output current-limiting indication signal is low. The difference between the overcurrent indication value and the overcurrent release value is the current-limiting hysteresis.

[0003] However, in actual applications, due to factors such as equipment accuracy, the load current is prone to fluctuations of ±2%. When the load current is low, its fluctuation range is still within the current limit hysteresis, and the current limit indication circuit can still filter out load current jitter. However, when the load current is too high, the current limit indication circuit with a fixed current limit hysteresis cannot filter out the load current jitter, and the current limit indication signal will still flip from a high level to a low level, resulting in frequent oscillation of the current limit indication signal. Since in actual applications, downstream chips need to collect the current limit indication signal to perform subsequent actions, a frequently oscillating current limit indication signal can cause the downstream chips to erroneously act. Summary of the Invention

[0004] The purpose of the embodiments of the present disclosure is to provide a current limiting indication circuit, chip and electronic device. Through the improved current limiting indication circuit, when the load current approaches the current limiting threshold, the fluctuations in the load current can be filtered, and the current limiting hysteresis amount can be changed with the change of the current limiting threshold, thereby ensuring that the current limiting indication signal will not frequently oscillate during the process of generating the current limiting indication signal.

[0005] According to a first aspect of the present disclosure, a current limiting indication circuit is provided. The current limiting indication circuit is connected to a charge pump that provides a driving current, and includes: a current sampling circuit, a reference current source, and a current comparison circuit. The current sampling circuit is configured to generate a first sampling current signal and a second sampling current signal that are multiples of the load current signal based on a received load current signal, and provide the first sampling current signal and the second sampling current signal to the current comparison circuit via a first node and a second node, respectively; the reference current source is configured to generate a reference current signal and provide the reference current signal to the current comparison circuit via the first node; the current comparison circuit is configured to compare the first sampling current signal with the reference current signal to obtain a first comparison signal, and output a current limiting indication signal based on a comparison result of the first comparison signal with a set current signal, and a comparison result of a sum of the first comparison signal and the second sampling current signal with the set current signal.

[0006] In some embodiments of the present disclosure, the current sampling circuit includes: a first resistor, a second resistor, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and an error amplifier, wherein the first end of the first resistor is coupled to the first voltage end, and the second end of the first resistor is coupled to the non-inverting input end of the error amplifier; the first end of the second resistor is coupled to the first voltage end, and the second end of the second resistor is coupled to the inverting input end of the error amplifier; the control electrode of the first transistor is coupled to the output end of the charge pump, the first electrode of the first transistor is coupled to the non-inverting input end of the error amplifier, and the second electrode of the first transistor is coupled to the load current input end and the second voltage end; the control electrode of the second transistor is coupled to the output end of the error amplifier, the first electrode of the second transistor is coupled to the inverting input end of the error amplifier, and the second electrode of the second transistor is coupled to the load current input end and the second voltage end. The first electrode of the fourth transistor is coupled; the control electrode of the third transistor is coupled to the output terminal of the error amplifier, the first electrode of the third transistor is coupled to the inverting input terminal of the error amplifier, and the second electrode of the third transistor is coupled to the second node; the control electrode of the fourth transistor is coupled to the first electrode of the fourth transistor, and the second electrode of the fourth transistor is coupled to the second voltage terminal; the control electrode of the fifth transistor is coupled to the control electrode of the fourth transistor, the first electrode of the fifth transistor is coupled to the first electrode of the sixth transistor, and the second electrode of the fifth transistor is coupled to the second voltage terminal; the control electrode of the sixth transistor is coupled to the first electrode of the sixth transistor, and the second electrode of the sixth transistor is coupled to the first voltage terminal; the control electrode of the seventh transistor is coupled to the control electrode of the sixth transistor, the first electrode of the seventh transistor is coupled to the first node, and the second electrode of the seventh transistor is coupled to the first voltage terminal.

[0007] In some embodiments of the present disclosure, a first terminal of the reference current source is coupled to the first node, and a second terminal of the reference current source is coupled to the second voltage terminal.

[0008] In some embodiments of the present disclosure, the current comparison circuit includes: an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a first current source and a first inverter, the control electrode of the eighth transistor is coupled to the first electrode of the eighth transistor and the first node, and the second electrode of the eighth transistor is coupled to the second voltage terminal; the control electrode of the ninth transistor is coupled to the control electrode of the eighth transistor, the first electrode of the ninth transistor is coupled to the output terminal of the charge pump, and the second electrode of the ninth transistor is coupled to the second voltage terminal; the control electrode of the tenth transistor is coupled to the control electrode of the eighth transistor, the first electrode of the tenth transistor is coupled to the first terminal of the first current source, and the second electrode of the tenth transistor is coupled to the a second voltage terminal; the control terminal of the eleventh transistor is coupled to the current limit indication signal output terminal, the first terminal of the eleventh transistor is coupled to the first terminal of the first current source, and the second terminal of the eleventh transistor is coupled to the first terminal of the twelfth transistor; the control terminal of the twelfth transistor is coupled to the control terminal of the thirteenth transistor, and the second terminal of the twelfth transistor is coupled to the second voltage terminal; the control terminal of the thirteenth transistor is coupled to the first terminal of the thirteenth transistor and the second node, and the second terminal of the thirteenth transistor is coupled to the second voltage terminal; the second terminal of the first current source is coupled to the first voltage terminal; the input terminal of the first inverter is coupled to the first terminal of the first current source, and the output terminal of the first inverter is coupled to the current limit indication signal output terminal.

[0009] In some embodiments of the present disclosure, when the first comparison signal is greater than the set current signal, the output current limiting indication signal is a high-level signal; when the sum of the first comparison signal and the second sampling current signal is less than the set current signal, the output current limiting indication signal is a low-level signal.

[0010] In some embodiments of the present disclosure, the first transistor, the fourth transistor, and the fifth transistor are all NMOS transistors, and the width-to-length ratio of the fourth transistor is greater than the width-to-length ratio of the fifth transistor; the second transistor, the third transistor, the sixth transistor, and the seventh transistor are all PMOS transistors, and the width-to-length ratio of the second transistor is greater than the width-to-length ratio of the third transistor, and the width-to-length ratio of the sixth transistor is greater than the width-to-length ratio of the seventh transistor.

[0011] In some embodiments of the present disclosure, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor and the thirteenth transistor are all NMOS transistors, and the width-to-length ratios of the eighth transistor, the ninth transistor and the tenth transistor are equal, and the width-to-length ratios of the twelfth transistor and the thirteenth transistor are equal.

[0012] In some embodiments of the present disclosure, the driving current provided by the charge pump is twice the setting current signal.

[0013] According to a second aspect of the present disclosure, a chip is provided, which includes the current limiting indication circuit according to the first aspect of the present disclosure.

[0014] According to a third aspect of the present disclosure, an electronic device is provided, comprising the chip according to the second aspect of the present disclosure.

[0015] Other features and advantages of the embodiments of the present disclosure will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings are used to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification. Together with the following detailed description, they are used to explain the embodiments of the present disclosure, but do not constitute a limitation of the embodiments of the present disclosure. In the accompanying drawings:

[0017] Figure 1 is an exemplary circuit diagram of a current limiting indication circuit;

[0018] Figure 2 is a schematic block diagram of a current limiting indication circuit according to an embodiment of the present disclosure;

[0019] Figure 3 is an exemplary circuit diagram of a current limiting indication circuit according to an embodiment of the present disclosure.

[0020] Elements in the drawings are schematic and not drawn to scale. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0022] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal manner unless otherwise explicitly defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together either directly or through one or more intermediate components.

[0023] In all embodiments of the present disclosure, since the source and drain of a metal oxide semiconductor (MOS) transistor are symmetrical, and the directions of the conduction current between the source and drain of an N-type transistor and a P-type transistor are opposite, in the embodiments of the present disclosure, the controlled middle terminal of the MOS transistor is referred to as the control terminal, and the remaining two terminals of the MOS transistor are referred to as the first terminal and the second terminal, respectively. In addition, terms such as "first" and "second" are only used to distinguish one component (or a portion of a component) from another component (or another portion of a component).

[0024] Figure 1 FIG. 1 shows an exemplary circuit diagram of a current limiting indication circuit 100. Figure 1 In the example, the charge pump provides a driving current of 2*Icp, thereby turning on the NMOS transistor in the same path as the resistor Ron. From the circuit structure and theoretical derivation, it can be seen that when the load current Iout rises to the current limit threshold Ilim expressed by the following formula (1), Figure 1 The current limiting indication signal CL outputted in the output indicates that the current limiting protection function is triggered:

[0025] Ilim=(2*Icp+Iset)*N*M*S=(2*Icp+Iset)*A Formula (1)

[0026] For simplicity of expression, parameter A is used to represent N*M*S in formula (1).

[0027] In addition, in order to achieve the function of indicating the occurrence of current limiting in advance, it is necessary to set an overcurrent indication value ICL_H that is smaller than the current limiting threshold Ilim, and an overcurrent state release value ICL_L that is smaller than the overcurrent indication value. When the load current Iout rises to the overcurrent indication value ICL_H shown in the following formula (2), the output of the inverter flips from a low level to a high level, and the output current limiting indication signal CL is a high level, notifying the outside world that it is in an overcurrent state:

[0028] ICL_H=(Icp+Iset)*A Formula (2)

[0029] When the load current Iout drops to the overcurrent state release value ICL_L shown in the following formula (3), the output of the inverter flips from high level to low level, and the output current limit indication signal CL is low level, notifying the outside world that it has exited the overcurrent state:

[0030]

[0031] In summary, the difference between the overcurrent indication value ICL_H and the overcurrent state release value ICL_L is the current limit hysteresis value ICL_hys, as shown in the following formula (4):

[0032]

[0033] In practical applications, Figure 1 The current source Iset in the circuit can be adjusted by an off-chip method, so the above formulas (1)-(3) can also change with the change of the current source Iset. However, as shown in formula (4), the current limit hysteresis cannot follow the change. Due to factors such as equipment accuracy, the load current is prone to ±2% fluctuations. When Iset = 20uA, Icp = 1uA, and A = 9200, the above formulas (2)-(4) can be used to obtain ICL_H = 193.2mA, ICL_L = 188.6mA, and ICL_hys = 4.6mA. If Iset = 300uA, the values ​​of Icp and A remain unchanged, then ICL_H = 2767mA, ICL_L = 2763.55mA, and ICL_hys remains 3.45mA. In actual applications, due to factors such as equipment accuracy, the load current is prone to ±2% fluctuations. When ICL_H=193.2mA, its current limit hysteresis ICL_hys is 4.6mA. If the load current fluctuates 2% downward from 194mA, the change is 3.88mA. Figure 1 The circuit shown can still filter the load current fluctuation. However, when ICL_H=2763.55mA, if the chip load current fluctuates 2% downward from 2764mA, that is, the change is 55mA, then Figure 1 The current-limit indicator circuit shown here cannot filter out fluctuations in the load current, causing the current-limit indicator signal to flip from a high level to a low level. If the load current fluctuates by ±2% around 2763.55mA, the indicator signal will frequently oscillate. In practical applications, downstream chips need to collect the current-limit indicator signal to take subsequent actions. Frequent oscillations can cause these chips to erroneously react.

[0034] The embodiments of the present disclosure provide a current limiting indication circuit that ensures that the current limiting indication signal does not frequently oscillate during the generation of the current limiting indication signal, thereby enabling the current limiting hysteresis to change with the current limiting threshold. Figure 2 FIG. 2 shows a schematic block diagram of a current limiting indication circuit 200 according to an embodiment of the present disclosure. Figure 2 As shown, the current limiting indication circuit 200 is connected to a charge pump 300 that provides a driving current. The current limiting indication circuit 200 may include: a current sampling circuit 210 , a reference current source 220 and a current comparison circuit 230 .

[0035] The current sampling circuit 210 can be coupled to a reference current source 220, a current comparison circuit 230, a charge pump 300, a first voltage terminal V1, a second voltage terminal V2, and a load current input terminal Iout. The current sampling circuit 210 is configured to generate a first sampling current signal I1 and a second sampling current signal I2 that are multiples of the load current signal Iout based on the received load current signal Iout, and provide the first sampling current signal I1 and the second sampling current signal I2 to the current comparison circuit 230 via a first node N1 and a second node N2, respectively.

[0036] The reference current source 220 can be coupled to the current sampling circuit 210, the current comparison circuit 230, and the second voltage terminal V2. The reference current source 220 is configured to generate a reference current signal Iset and provide the reference current signal Iset to the current comparison circuit 230 via the first node N1. The reference current signal Iset can be adjusted in value via an off-chip method.

[0037] The current comparison circuit 230 can be coupled to the current sampling circuit 210, the reference current source 220, the charge pump 300, the first voltage terminal V1, the second voltage terminal V2, and the current limit indication signal output terminal CL. The current comparison circuit 230 is configured to compare the first sampled current signal I1 with the reference current signal Iset to obtain a first comparison signal Is1, and output the current limit indication signal CL based on the comparison result of the first comparison signal Is1 with the set current signal Icp, and the comparison result of the sum of the first comparison signal Is1 and the second sampled current signal I2 with the set current signal Icp. The second sampled current signal I2, which has a multiple relationship with the load current signal Iout, and the current limit hysteresis ICL are proportional to each other. hys Positive correlation.

[0038] When the first comparison signal Is1 is greater than the set current signal Icp, the output current limit indication signal CL is a high-level signal, notifying the outside world that the device is in an overcurrent state. When the sum of the first comparison signal Is1 and the second sampling current signal I2 is less than the set current signal Icp, the output current limit indication signal CL is a low-level signal, notifying the outside world that the device has exited the overcurrent state.

[0039] According to the current limiting indication circuit of the embodiment of the present disclosure, the current limiting hysteresis ICL hys It is positively correlated with the second sampling current signal I2, and the second sampling current signal I2 is in a multiple relationship with the load current signal Iout, so the current limiting hysteresis ICL hys There is a multiple relationship with the load current signal Iout, especially when the load current Iout is close to the current limit threshold, then the current limit hysteresis ICL hys It changes with the change of current limiting threshold. When the current limiting threshold is set larger, the corresponding current limiting hysteresis ICL hys When the current limiting threshold is small, the corresponding current limiting hysteresis ICL hys It is also relatively small, and when the load current Iout fluctuates by ±2%, it can be ensured that the current limiting indication signal will not frequently oscillate during the current limiting indication process.

[0040] Figure 3 FIG. 2 shows an exemplary circuit diagram of a current limiting indication circuit 200 according to an embodiment of the present disclosure. Figure 3As shown, the current sampling circuit 210 may include: a first resistor R1, a second resistor R2, a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an error amplifier EA. The first end of the first resistor R1 is coupled to the first voltage terminal V1, and the second end of the first resistor R1 is coupled to the non-inverting input terminal of the error amplifier EA. The first end of the second resistor R2 is coupled to the first voltage terminal V1, and the second end of the second resistor R2 is coupled to the inverting input terminal of the error amplifier EA. The control electrode of the first transistor M1 is coupled to the output terminal of the charge pump 300, the first electrode of the first transistor M1 is coupled to the non-inverting input terminal of the error amplifier EA, and the second electrode of the first transistor M1 is coupled to the load current input terminal Iout and the second voltage terminal V2. The control electrode of the second transistor M2 is coupled to the output terminal of the error amplifier EA, the first electrode of the second transistor M2 is coupled to the inverting input terminal of the error amplifier EA, and the second electrode of the second transistor M2 is coupled to the first electrode of the fourth transistor M4. The control electrode of the third transistor M3 is coupled to the output terminal of the error amplifier EA, the first electrode of the third transistor M3 is coupled to the inverting input terminal of the error amplifier EA, and the second electrode of the third transistor M3 is coupled to the second node N2. The control electrode of the fourth transistor M4 is coupled to the first electrode of the fourth transistor M4, and the second electrode of the fourth transistor M4 is coupled to the second voltage terminal V2. The control electrode of the fifth transistor M5 is coupled to the control electrode of the fourth transistor M4, the first electrode of the fifth transistor M5 is coupled to the first electrode of the sixth transistor M6, and the second electrode of the fifth transistor M5 is coupled to the second voltage terminal V2. The control electrode of the sixth transistor M6 is coupled to the first electrode of the sixth transistor M6, and the second electrode of the sixth transistor M6 is coupled to the first voltage terminal V1. The control electrode of the seventh transistor M7 is coupled to the control electrode of the sixth transistor M6, the first electrode of the seventh transistor M7 is coupled to the first node N1, and the second electrode of the seventh transistor M7 is coupled to the first voltage terminal V1.

[0041] The reference current source 220 is a current source Iset, a first terminal of which is coupled to the first node N1 , and a second terminal of which is coupled to the second voltage terminal V2 .

[0042] The current comparison circuit 230 may include an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a first current source Icp, and a first inverter D1. The control electrode of the eighth transistor M8 is coupled to the first electrode of the eighth transistor M8 and the first node N1, and the second electrode of the eighth transistor M8 is coupled to the second voltage terminal V2. The control electrode of the ninth transistor M9 is coupled to the control electrode of the eighth transistor M8, the first electrode of the ninth transistor M9 is coupled to the output terminal of the charge pump 300, and the second electrode of the ninth transistor M9 is coupled to the second voltage terminal V2. The control electrode of the tenth transistor M10 is coupled to the control electrode of the eighth transistor M8, the first electrode of the tenth transistor M10 is coupled to the first terminal of the first current source Icp, and the second electrode of the tenth transistor M10 is coupled to the second voltage terminal V2. The control electrode of the eleventh transistor M11 is coupled to the current limit indication signal output terminal CL, a first electrode of the eleventh transistor M11 is coupled to the first terminal of the first current source Icp, and a second electrode of the eleventh transistor M11 is coupled to the first electrode of the twelfth transistor M12. The control electrode of the twelfth transistor M12 is coupled to the control electrode of the thirteenth transistor M13, and a second electrode of the twelfth transistor M12 is coupled to the second voltage terminal V2. The control electrode of the thirteenth transistor M13 is coupled to the first electrode of the thirteenth transistor M13 and the second node N2, and a second electrode of the thirteenth transistor M13 is coupled to the second voltage terminal V2. The second terminal of the first current source Icp is coupled to the first voltage terminal V1. The input terminal of the first inverter D1 is coupled to the first terminal of the first current source Icp, and the output terminal of the first inverter D1 is coupled to the current limit indication signal output terminal CL.

[0043] exist Figure 3In the example, a high voltage signal is input from the first voltage terminal V1, and the second voltage terminal V2 is grounded. The driving current provided by the charge pump 300 is twice the set current signal provided by the first current source Icp, that is, the charge pump 300 provides a driving current of 2*Icp to turn on the first transistor M1. The first transistor M1, the fourth transistor M4, the fifth transistor M5, the eighth transistor M8 to the thirteenth transistor M13 are all NMOS transistors, and the width-to-length ratio of the fourth transistor M4 is greater than the width-to-length ratio of the fifth transistor M5. In the embodiment of the present disclosure, for example, the width-to-length ratio of the fourth transistor M4 to the fifth transistor M5 is M. The second transistor M2, the third transistor M3, the sixth transistor M6 and the seventh transistor M7 are all PMOS transistors, and the width-to-length ratio of the second transistor M2 is greater than the width-to-length ratio of the third transistor M3, and the width-to-length ratio of the sixth transistor M6 is greater than the width-to-length ratio of the seventh transistor M7. In the embodiment of the present disclosure, for example, the width-to-length ratio of the second transistor M2 to the third transistor M3 is K, the width-to-length ratio of the sixth transistor M6 to the seventh transistor M7 is N, the resistance ratio of the second resistor R2 to the first resistor R1 is S, the width-to-length ratios of the eighth transistor M8, the ninth transistor M9 and the tenth transistor M10 are equal, and the width-to-length ratios of the twelfth transistor M12 and the thirteenth transistor M13 are equal. Those skilled in the art should understand that based on the above inventive concept, Figure 3 The variation of the circuit shown should also fall within the scope of protection of the present disclosure. In this variation, the above-mentioned transistor and voltage terminal may also have the same Figure 3 Examples of different setups are shown.

[0044] The following combination Figure 3 The working process of the current limiting indicating circuit 200 according to the embodiment of the present disclosure is explained with an example.

[0045] When the load current Iout is input to the current limit indicating circuit 200, due to the clamping effect of the error amplifier EA and the characteristic that the voltages at its non-inverting input and inverting input are equal, when the current flowing through the first resistor R1 is the load current Iout, since R2 / R1=S, the current flowing through the second resistor R2 is Iout / S, which is also the current flowing through the second transistor M2. Because the second transistor M2 and the third transistor M3 form a mirror image relationship and their width-to-length ratio is K, when the current flowing through the third transistor M3 is set to Isen, the current flowing through the second transistor M2 is K*Isen, thus Iout / S=K*Isen, and Isen=Iout / (S*K). The current Isen of the third transistor M3 is injected into the thirteenth transistor M13 through the second node N2, that is, the second sampling current signal I2=Isen. The thirteenth transistor M13 and the twelfth transistor M12 form a current mirror structure, and the width-to-length ratio of the thirteenth transistor M13 and the twelfth transistor M12 is 1:1. Therefore, the current of the twelfth transistor M12 is the second sampling current signal I2.

[0046] The current K*Isen flowing through the second transistor M2 is injected into the fourth transistor M4. Since the fourth transistor M4 and the fifth transistor M5 form a mirrored structure with a width-to-length ratio of M, the current flowing through the fifth transistor M5 is K*Isen / M. The current K*Isen / M of the fifth transistor M5 is injected into the sixth transistor M6. Since the sixth transistor M6 and the seventh transistor M7 form a mirrored structure with a width-to-length ratio of N, the current flowing through the seventh transistor M7 is K*Isen / (M*N). The current K*Isen / (M*N) of the seventh transistor M7 is injected into the eighth transistor M8 through the node N1, i.e., the first sampled current signal I1 = K*Isen / (M*N). Since the eighth transistor M8 and the tenth transistor M10 form a mirrored structure with a width-to-length ratio of 1, the current flowing through the tenth transistor M10 is the difference between the first sampled current signal I1 and the reference current signal Iset. The resulting first comparison signal Is1 = K*Isen / (M*N)-Iset.

[0047] When the first comparison signal Is1 is greater than the set current signal Icp, the node A is at a low level, which is then flipped to a high level after passing through the inverter D1, and the output current limit indication signal CL is a high level signal. At this time, the eleventh transistor M11 is turned on, so that the sum of the second sampling current signal I2 and the first comparison signal Is1 needs to be compared with the set current signal Icp. When the sum of the first comparison signal Is1 and the second sampling current signal I2 is less than the set current signal Icp, the node A is at a high level, which is flipped to a low level after passing through the inverter D1, and the output current limit indication signal CL can then become a low level signal.

[0048] exist Figure 3In the example, according to the circuit structure and theoretical deduction, the overcurrent indication value ICL H As shown in the following formula (5):

[0049] ICL H =(Icp+Iset)*A Formula (5)

[0050] Overcurrent status release value ICL L As shown in the following formula (6):

[0051] ICL L =(Icp+Iset-Isen)*A Formula (6)

[0052] The current limiting hysteresis is shown in the following formula (7):

[0053] ICL hys =ICL H -ICL L =Isen*A=Iout*A / (K*S) Formula (7)

[0054] When the load current Iout is very close to the current limit threshold Ilim, the above formula (7) can be equivalent to the following formula (8):

[0055] ICL hys =Iout*A / (K*S)≈Ilim*A / (K*S) Formula (8)

[0056] From the above formula (8), we can know that the current limiting hysteresis ICL hys The improvement effect is shown below: In practical applications, if A=9200, S=1300, and K=200 are set, then formula (8) can be equivalent to: ICL hys =3.5%*Ilim. When Iout is extremely close to Ilim, the current limiting indication circuit provided by the embodiment of the present disclosure can filter the ±2% fluctuation of the load current Iout, ensuring that the current limiting indication signal does not frequently oscillate during the current limiting indication process.

[0057] An embodiment of the present disclosure further provides a chip. The chip includes a current limiting indication circuit according to an embodiment of the present disclosure. The chip is, for example, used in a chip requiring current limiting indication.

[0058] An embodiment of the present disclosure further provides an electronic device. The electronic device includes a chip according to an embodiment of the present disclosure. The electronic device may be, for example, a power tube, a USB, an LCD TV, or a smartphone.

[0059] Unless the context clearly indicates otherwise, as used herein and in the appended claims, the singular includes the plural, and vice versa. Thus, when referring to the singular, the plural of the corresponding term is generally included. Similarly, the words "include" and "comprising" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it follows a group of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or comprehensive.

[0060] Further aspects and scope of adaptability become apparent from the description provided herein. It should be understood that various aspects of the present application can be implemented individually or in combination with one or more other aspects. It should also be understood that the description and specific embodiments herein are intended to be illustrative only and are not intended to limit the scope of the present application.

[0061] Several embodiments of the present disclosure have been described in detail above, but it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The scope of protection of the present disclosure is defined by the appended claims.

Claims

1. A current limiting indicating circuit connected to a charge pump providing a driving current, characterized in that: The current limiting indication circuit includes: a current sampling circuit, a reference current source, and a current comparison circuit. The current sampling circuit is configured to generate a first sampling current signal and a second sampling current signal that are multiples of the load current signal according to the received load current signal, and provide the first sampling current signal and the second sampling current signal to the current comparison circuit via a first node and a second node respectively; The reference current source is configured to generate a reference current signal and provide the reference current signal to the current comparison circuit via the first node; The current comparison circuit is configured to compare the first sampling current signal with the reference current signal to obtain a first comparison signal, and output a current limit indication signal based on a comparison result between the first comparison signal and a set current signal, and a comparison result between a sum of the first comparison signal and the second sampling current signal and the set current signal. The second sampling current signal, which has a multiple relationship with the load current signal, is positively correlated with the current limiting hysteresis. The current comparison circuit includes: an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a first current source and a first inverter. The control electrode of the eighth transistor is coupled to the first electrode of the eighth transistor and the first node, and the second electrode of the eighth transistor is coupled to the second voltage terminal; The control electrode of the ninth transistor is coupled to the control electrode of the eighth transistor, the first electrode of the ninth transistor is coupled to the output terminal of the charge pump, and the second electrode of the ninth transistor is coupled to the second voltage terminal; A control electrode of the tenth transistor is coupled to the control electrode of the eighth transistor, a first electrode of the tenth transistor is coupled to the first terminal of the first current source, and a second electrode of the tenth transistor is coupled to the second voltage terminal; The control electrode of the eleventh transistor is coupled to the current limit indication signal output terminal, the first electrode of the eleventh transistor is coupled to the first terminal of the first current source, and the second electrode of the eleventh transistor is coupled to the first electrode of the twelfth transistor; The control electrode of the twelfth transistor is coupled to the control electrode of the thirteenth transistor, and the second electrode of the twelfth transistor is coupled to the second voltage terminal; The control electrode of the thirteenth transistor is coupled to the first electrode of the thirteenth transistor and the second node, and the second electrode of the thirteenth transistor is coupled to the second voltage terminal; The second terminal of the first current source is coupled to the first voltage terminal; An input terminal of the first inverter is coupled to the first terminal of the first current source, and an output terminal of the first inverter is coupled to the current-limiting indication signal output terminal.

2. The current limiting indicating circuit according to claim 1, characterized in that: The current sampling circuit includes: a first resistor, a second resistor, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and an error amplifier. Wherein, the first end of the first resistor is coupled to the first voltage end, and the second end of the first resistor is coupled to the non-inverting input end of the error amplifier; A first end of the second resistor is coupled to the first voltage terminal, and a second end of the second resistor is coupled to the inverting input terminal of the error amplifier; The control electrode of the first transistor is coupled to the output terminal of the charge pump, the first electrode of the first transistor is coupled to the non-inverting input terminal of the error amplifier, and the second electrode of the first transistor is coupled to the load current input terminal and the second voltage terminal; The control electrode of the second transistor is coupled to the output terminal of the error amplifier, the first electrode of the second transistor is coupled to the inverting input terminal of the error amplifier, and the second electrode of the second transistor is coupled to the first electrode of the fourth transistor; A control electrode of the third transistor is coupled to the output terminal of the error amplifier, a first electrode of the third transistor is coupled to the inverting input terminal of the error amplifier, and a second electrode of the third transistor is coupled to the second node; The control electrode of the fourth transistor is coupled to the first electrode of the fourth transistor, and the second electrode of the fourth transistor is coupled to the second voltage terminal; The control electrode of the fifth transistor is coupled to the control electrode of the fourth transistor, the first electrode of the fifth transistor is coupled to the first electrode of the sixth transistor, and the second electrode of the fifth transistor is coupled to the second voltage terminal; The control electrode of the sixth transistor is coupled to the first electrode of the sixth transistor, and the second electrode of the sixth transistor is coupled to the first voltage terminal; A control electrode of the seventh transistor is coupled to the control electrode of the sixth transistor, a first electrode of the seventh transistor is coupled to the first node, and a second electrode of the seventh transistor is coupled to the first voltage terminal.

3. The current limiting indicating circuit according to claim 1, characterized in that: A first terminal of the reference current source is coupled to the first node, and a second terminal of the reference current source is coupled to a second voltage terminal.

4. The current limiting indicating circuit according to claim 1, characterized in that: in, When the first comparison signal is greater than the set current signal, the output current limiting indication signal is a high level signal; when the sum of the first comparison signal and the second sampling current signal is less than the set current signal, the output current limiting indication signal is a low level signal.

5. The current limiting indicating circuit according to claim 2, characterized in that: The first transistor, the fourth transistor and the fifth transistor are all NMOS transistors, and the width-to-length ratio of the fourth transistor is greater than the width-to-length ratio of the fifth transistor; the second transistor, the third transistor, the sixth transistor and the seventh transistor are all PMOS transistors, and the width-to-length ratio of the second transistor is greater than the width-to-length ratio of the third transistor, and the width-to-length ratio of the sixth transistor is greater than the width-to-length ratio of the seventh transistor.

6. The current limiting indicating circuit according to claim 1, characterized in that: The eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor and the thirteenth transistor are all NMOS transistors, and the eighth transistor, the ninth transistor and the tenth transistor have the same width-to-length ratio, and the twelfth transistor and the thirteenth transistor have the same width-to-length ratio.

7. The current limiting indicating circuit according to claim 1, characterized in that: The driving current provided by the charge pump is twice the setting current signal.

8. A chip, characterized in that: The invention comprises a current limiting indicating circuit according to any one of claims 1 to 7.

9. An electronic device, characterized in that: Comprising the chip according to claim 8.

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