A multi-channel trench MOS device and a method for fabricating the same

Abstract

The application provides a multi-channel trench MOS device and a manufacturing method thereof. The multi-channel trench MOS device comprises a substrate, an epitaxial layer arranged on the substrate, and a plurality of first device units and a plurality of second device units formed in the epitaxial layer, wherein the first device units and the second device units are arranged alternately, each of the first device units comprises one shielding area and four trench gates surrounding the shielding area, and a source area is formed in the trench gate; each of the second device units comprises one trench gate and four shielding areas surrounding the trench gate, and a source area is formed in the trench gate. The first device units and the second device units are arranged alternately, so that the shielding areas and the trench gates are arranged alternately in a first cross section along a first direction, thereby shortening the distance between the shielding areas, increasing the surge capacity of the device, and improving the voltage resistance and reliability of the device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular to a multi-channel trench MOS device and a manufacturing method thereof. BACKGROUND

[0002] The planar MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) reduces the on-resistance by reducing the cell size, but has reached the limit of the planar MOSFET. The trench MOSFET changes the channel current from lateral to vertical, which can greatly improve the cell density and significantly reduce the on-resistance.

[0003] However, the trench structure exposes the breakdown field region at the bottom of the trench, which reduces the voltage resistance and surge voltage resistance of the trench MOSFET, especially in high-voltage and large-current applications.

[0004] Therefore, it is very important to improve the voltage resistance and surge voltage resistance of the trench MOSFET to improve the reliability of the device. SUMMARY

[0005] A series of simplified concepts are introduced in the summary section, which will be further described in detail in the specific embodiment section. The summary section of the present application does not mean to attempt to limit the key features and necessary technical features of the claimed technical solution, nor to attempt to determine the protection scope of the claimed technical solution.

[0006] In view of the existing problems, the present application provides a multi-channel trench MOS device, comprising: a substrate; an epitaxial layer disposed on the substrate, a plurality of first device units and a plurality of second device units are formed in the epitaxial layer, the first device units and the second device units are arranged alternately, wherein: each first device unit comprises a shielding area and four trench gates around the shielding area, a source area is formed in the trench gate; each second device unit comprises a trench gate and four shielding areas around the trench gate, a source area is formed in the trench gate.

[0007] Exemplarily, on a first cross section along a first direction, the shielding areas and the trench gates are arranged alternately.

[0008] Exemplarily, on a second cross section along the first direction, the trench gates and the source areas are arranged alternately.

[0009] Exemplarily, on a cross section along a second direction, the trench gate and the source region are arranged between adjacent shielding regions, and the second direction forms an angle of 45 degrees with the first direction.

[0010] Exemplarily, the shielding region has a first conductive type, and the source region has a second conductive type.

[0011] Exemplarily, a well region is further formed in the epitaxial layer, the well region has the first conductive type, and the source region is formed in the well region.

[0012] Exemplarily, the shielding region is a regular quadrilateral, and the trench gate is a regular octagon, and the side length of the shielding region is equal to the side length of the trench gate.

[0013] Exemplarily, the plurality of repeatedly arranged device units form double channels in (11-20) direction and (1-100) direction, and the first direction includes (11-20) direction or (1-100) direction.

[0014] In another aspect, the application further provides a manufacturing method of a multi-channel trench MOS device, comprising: providing a substrate, forming an epitaxial layer on the substrate; performing first ion implantation to form a source region on the top of the epitaxial layer; performing second ion implantation to form a shielding region on the top of the epitaxial layer; etching the epitaxial layer between the source region and the shielding region to form a trench in the epitaxial layer; and filling the trench to form a trench gate; wherein the epitaxial layer forms a plurality of first device units and a plurality of second device units, and the first device units and the second device units are arranged alternately, wherein: each first device unit includes one shielding region and four trench gates surrounding the shielding region, and a source region is formed in the trench gate; and each second device unit includes one trench gate and four shielding regions surrounding the trench gate, and a source region is formed in the trench gate.

[0015] Exemplarily, the method further includes a step of forming a well region before forming the source region, and the source region is formed in the well region.

[0016] The multi-channel trench MOS device of the application, by alternately arranging the first device units and the second device units, makes the shielding region and the trench gate arranged alternately on a first cross section along the first direction, i.e. only the trench gate needs to be crossed between adjacent shielding regions without crossing the source region, thereby shortening the distance between the shielding regions, and the formed multi-channel interface can increase the unit current; when the device is off, the induced current existing in the circuit can flow out of the device through the shielding region, thereby avoiding the device from burning out and increasing the surge capacity of the device; and the effective electric field coupling can occur through the shielding region, thereby protecting the gate oxide, reducing the electric field strength, and improving the voltage resistance and reliability of the device. BRIEF DESCRIPTION OF DRAWINGS

[0017] The following drawings are included here as part of this application to provide an understanding of the application. The embodiments of the application illustrated in the drawings and described in the detailed description are intended to be illustrative and not limiting of the application. The drawings contain the following figures:

[0018] In the drawings:

[0019] FIG. 1A A partial plan view of a multi-channel trench MOS device according to one embodiment of the present application is shown.

[0020] FIG. 1B A first cross-sectional view of a multi-channel trench MOS device according to one embodiment of the present application is shown along a first direction.

[0021] FIG. 1C A second cross-sectional view of a multi-channel trench MOS device according to one embodiment of the present application is shown along a first direction.

[0022] FIG. 1D A cross-sectional view of a multi-channel trench MOS device according to one embodiment of the present application is shown along a second direction.

[0023] FIG. 1E A cross-sectional view of a multi-channel trench MOS device according to one embodiment of the present application is shown along a second direction. FIG. 1A A cross-sectional view of a multi-channel trench MOS device according to one embodiment of the present application is shown along a second direction.

[0024] FIG. 2 A flow chart of a method of fabricating a multi-channel trench MOS device according to one embodiment of the present application is shown.

[0025] FIGS. 3A-3H A cross-sectional view of a multi-channel trench MOS device according to one embodiment of the present application is shown along a second direction. DETAILED DESCRIPTION

[0026] In the following description, numerous specific details are given to provide a thorough understanding of the application. However, it will be apparent that the application can be practiced without one or more of the specific details. In other instances, well-known features are not described in order to avoid obscuring the application. Unless the context clearly requires otherwise, throughout the description, the terms "comprise," "comprising," "comprises," "include," "including," "includes," "contain," "containing," "contains," "have," "having," "has," "may," "might," "must," "can," "could," "should," "will," "would," and the like are to be construed as open-ended terms (i.e., terms that are used to note "including but not limited to," "including at least the elements listed") that describe the presence of something intended, but not limited to, that which is described at that time. As used herein, the term "about" when used in connection with a numerical value, means that the value is within 10% of the recited value.

[0027] It is to be understood that the application can be carried out by specifically different embodiments and that the application is not limited to the embodiments here presented. On the contrary, the intention is to cover by the application all modifications, enhancements and alternatives falling within the scope of the application. In the drawings, the sizes and relative sizes of layers and regions are exaggerated for clarity. Identical reference numerals have been used, where applicable, to designate corresponding elements with the same or similar functions which are illustrated in the figures.

[0028] It will be understood that when an element or layer is referred to as being "on", "adjacent", "connected" or "coupled" to another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly adjacent", "directly connected" or "directly coupled" to another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

[0029] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0030] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0031] The trench MOSFET can greatly increase the cell density and significantly reduce the on-resistance by changing the channel current from lateral to vertical. However, the trench structure exposes the breakdown field region at the bottom of the trench, which reduces the anti-peak voltage capability of the trench MOSFET, especially in the high-voltage and high-current application field.

[0032] Therefore, in view of the foregoing technical problems, the present application provides a multi-channel trench MOS device, comprising: a substrate; an epitaxial layer disposed on the substrate, a plurality of first device units and a plurality of second device units are formed in the epitaxial layer, the first device units and the second device units are arranged alternately, wherein: each of the first device units comprises one shielding area and four trench gates around the shielding area, a source area is formed in the trench gate; each of the second device units comprises one trench gate and four shielding areas around the trench gate, a source area is formed in the trench gate.

[0033] The multi-channel trench MOS device of the present application, in the first cross section along the first direction, the shielding area and the trench gate are arranged alternately, that is, only the trench gate needs to be crossed between the adjacent shielding areas without crossing the source area, thereby shortening the distance between the shielding areas, the multi-channel interface formed can increase the unit current; when the device is off, the inductive current existing in the circuit can flow out of the device through the shielding area, thereby avoiding the device from burning out and increasing the surge capacity of the device; and effective electric field coupling can occur through the shielding area, thereby protecting the gate oxide, reducing the electric field strength, and improving the voltage resistance and reliability of the device.

[0034] In order to thoroughly understand the present application, detailed steps and structures will be proposed in the following description in order to explain the technical solutions proposed by the present application. The preferred embodiments of the present application are described in detail as follows, however, in addition to these detailed descriptions, the present application can have other implementation manners.

[0035] Embodiment one

[0036] In the following, reference FIGS. 1A-1E The multi-channel trench MOS device of the present application is described in detail, wherein, FIG. 1A A partial top view of the multi-channel trench MOS device of one specific embodiment of the present application is shown, FIG. 1E A schematic view of the cross section of the broken line shown. FIG. 1A A schematic view of the cross section of the broken line shown.

[0037] Exemplarily, the multi-channel trench MOS device of the present application comprises: a substrate; an epitaxial layer disposed on the substrate, a plurality of first device units and a plurality of second device units are formed in the epitaxial layer, the first device units and the second device units are arranged alternately, wherein: each of the first device units comprises one shield region 110 and four trench gates 120 surrounding the shield region 110, a source region 130 is formed in the trench gate 120; each of the second device units comprises one trench gate 120 and four shield regions 110 surrounding the trench gate 120, a source region 130 is formed in the trench gate 120.

[0038] Specifically, the substrate can be any suitable semiconductor substrate, for example, bulk silicon substrate, which can also be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductor, also including multi-layer structure composed of these semiconductors, etc., or silicon-on-insulator (SOI), stacked silicon-on-insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), or can also be double side polished wafers (DSP), ceramic substrate such as aluminum oxide, quartz or glass substrate, etc.

[0039] In some embodiments of the present application, the substrate can be a single layer of semiconductor material, such as silicon carbide substrate and the like.

[0040] The material of the epitaxial layer can be the same as or different from that of the substrate. Exemplarily, the epitaxial layer is made of any suitable material such as silicon carbide and the like.

[0041] In some embodiments of the present application, a well region is formed in the epitaxial layer, the well region is formed in the top of the epitaxial layer, a source region 130 is formed in the well region, and the source region 130 is formed in the top of the well region. Exemplarily, the well region has a first conductivity type, and the source region 130 has a second conductivity type, or the well region has a second conductivity type, and the source region 130 has a first conductivity type.

[0042] In some embodiments of the present application, the shield region 110 is located in the epitaxial layer and extends longitudinally from the top of the source region 130 towards the substrate, the bottom of the shield region 110 is located in the epitaxial layer below the well region, and the sidewall of the shield region 110 is spaced apart from the sidewall of the trench. The shield region 110 can electrically connect the source region 130, the well region, the contact metal layer (see below description), and the epitaxial layer between the bottom of the well region and the top of the shield region 110, forming an equipotential network. Exemplarily, the shield region 110 has a first conductivity type, and the source region 130 has a second conductivity type, or the shield region 110 has the second conductivity type, and the source region 130 has the first conductivity type.

[0043] In some embodiments of the present application, a trench is formed in the epitaxial layer, and the trench gate 120 is formed in the trench. The trench gate 120 can include a gate material layer and a gate dielectric layer surrounding the bottom and sidewall of the gate material layer. The gate material layer is electrically isolated from the substrate, the well region, and the source region 130 by the gate dielectric layer. The gate material layer can be, for example, a polysilicon material such as N-type doped or P-type doped polysilicon, and the gate dielectric layer can be, for example, silicon oxide or a high-k dielectric with a dielectric constant k greater than 7.

[0044] Exemplarily, a plurality of first device units and a plurality of second device units are formed in the epitaxial layer, and the first device units and the second device units are arranged alternately, wherein: each of the first device units includes one shield region 110 and four trench gates 120 surrounding the shield region 110, and the source region 130 is formed in the trench gate 120; each of the second device units includes one trench gate 120 and four shield regions 110 surrounding the trench gate 120, and the source region 130 is formed in the trench gate, as shown in FIG. 1A .

[0045] Further, the alternately repeated first device units and second device units form double channels in the (11-20) direction and the (1-100) direction, as shown in FIG. 1A . Further, the first direction described below includes the (11-20) direction or the (1-100) direction. It should be noted that the direction and number of channels formed in the device shown in FIG. 1 are exemplary only, and the present application does not limit the same.

[0046] Exemplarily, in a first cross section along the first direction, the shield regions and the trench gates are arranged alternately. FIG. 1B A schematic diagram of a first cross section along the first direction is shown, i.e., a cross-sectional view along the dashed line 01 in FIG. 1A . As shown in FIG. 1A and 1BAs shown, on the first cross section along the first direction, only the shielding regions 110 are arranged alternately with the trench gates 120, that is, only the trench gates 120 need to be crossed between adjacent shielding regions 110 without crossing the source regions 130, thereby shortening the interval between the shielding regions 110.

[0047] Exemplarily, on the second cross section along the first direction, the trench gates 120 are arranged alternately with the source regions 130. FIG. 1C As shown, the second cross section along the first direction is a cross section along the dashed line 02 in the middle. FIG. 1A As shown, on the second cross section along the first direction, only the trench gates 120 are arranged alternately with the source regions 130, without involving the shielding regions 110. FIG. 1A and 1C As shown, on the second cross section along the first direction, only the trench gates 120 are arranged alternately with the source regions 130, without involving the shielding regions 110.

[0048] Exemplarily, on the cross section along the second direction, the trench gates 120 and the source regions 130 are arranged between adjacent shielding regions 110. The second direction is at an angle of 45° with the first direction, and specifically, the second direction includes the (01-10) direction or the (10-10) direction. FIG. 1D As shown, the cross section along the second direction is a cross section along the dashed line 03 in the middle. FIG. 1A

[0049] In some embodiments of the present application, the shielding regions 110 are regular quadrilaterals, and the trench gates 120 are regular octagons, and the side length of the shielding regions 110 is equal to the side length of the trench gates 120, as shown. FIG. 1A In addition, the source regions 130 are formed in the trench gates 120, and the shape of the source regions 130 can be the same as or different from the trench gates 120. It should be noted that, in actual production, due to the influence of process precision, the shielding regions 110 and the trench gates 120 are difficult to form standard regular quadrilaterals and regular octagons, and the edges of the shielding regions 110 and the trench gates 120 that coincide with each other have an arc or fluctuation, and the corners of the shielding regions 110 or the trench gates 120 are arc-shaped, which all fall within the scope of the present application.

[0050] In some embodiments of the present application, a buffer layer is further formed between the substrate and the epitaxial layer, which can make the epitaxial layer and the substrate have better concentration matching, and is beneficial to accurately controlling the doping concentration of the epitaxial layer during the growth process.

[0051] ​In some embodiments of the present application, an interlayer dielectric layer is formed on the epitaxial layer, and the interlayer dielectric layer is located above the trench gate 120 and part of the well region and part of the source region 130. The top and sidewall of the interlayer dielectric layer are formed with a contact metal layer surrounding the interlayer dielectric layer, and the interlayer dielectric layer serves as an insulating medium layer sandwiched between the contact metal layer and the epitaxial layer. The interlayer dielectric layer is made of at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and a low-k dielectric with a dielectric constant k less than 3, and the contact metal layer is made of at least one of, for example, nickel (Ni), aluminum (Al), copper (Cu), gold (Au), titanium (Ti), tungsten (W), platinum (Pt), silver (Ag), etc.

[0052] In some embodiments of the present application, for an n-type trench MOS device, the second conductivity type is n-type and the first conductivity type is p-type, and for a p-type trench MOS device, the second conductivity type is p-type and the first conductivity type is n-type. The p-type impurities or ions are, for example, boron, boron fluoride, etc., and the n-type impurities or ions are, for example, phosphorus, etc.

[0053] In summary, the multi-channel trench MOS device of the present application, by alternately arranging the first device unit and the second device unit, makes the shielding region and the trench gate alternately arranged in the first cross section along the first direction, i.e. only the trench gate needs to be crossed between adjacent shielding regions without crossing the source region, thereby shortening the distance between the shielding regions, and the multi-channel interface formed can increase the unit current; when the device is off, the induced current existing in the circuit can flow out of the device through the shielding region, thereby avoiding the device from burning out and increasing the surge capacity of the device; and effective electric field coupling can occur through the shielding region, thereby protecting the gate oxide, reducing the electric field strength, and improving the voltage resistance and reliability of the device.

[0054] Embodiment Two

[0055] The present application also provides a manufacturing method of a multi-channel trench MOS device. As shown in FIG. 2 the manufacturing method comprises the following steps:

[0056] S1, providing a substrate and forming an epitaxial layer on the substrate;

[0057] S2, performing first ion implantation to form a source region on the top of the epitaxial layer;

[0058] S3, performing second ion implantation to form a shielding region on the top of the epitaxial layer;

[0059] S4, etching the epitaxial layer between the source region and the shielding region to form a trench in the epitaxial layer;

[0060] S5, filling the trench to form a trench gate;

[0061] The epitaxial layer contains a plurality of first device units and a plurality of second device units, which are arranged alternately. Each first device unit includes a shielding region and four trench gates surrounding the shielding region, and a source region is formed within the trench gates. Each second device unit includes a trench gate and four shielding regions surrounding the trench gates, and a source region is formed within the trench gates.

[0062] To further illustrate the fabrication process of multi-channel trench MOS devices, the following section combines data from 3A to... FIG. 3H The above production method will be explained in detail.

[0063] First, execute step S1, as follows: FIG. 3A As shown, a substrate 201 is provided, on which an epitaxial layer 203 is formed.

[0064] Specifically, the substrate 201 can be any suitable semiconductor substrate 201, such as a bulk silicon substrate, or it can be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or it can be silicon on insulator (SOI), silicon on insulator (SSOI), silicon on insulator (S-SiGeOI), silicon on insulator (SiGeOI) and germanium on insulator (GeOI), or it can be a double-side polished wafer (DSP), or it can be a ceramic substrate such as alumina, a quartz or glass substrate, etc.

[0065] In some embodiments of this application, the substrate 201 may be a single-layer semiconductor material, such as a silicon carbide substrate.

[0066] An epitaxial layer 203 can be formed on the substrate 201 using epitaxial growth processes such as vapor phase epitaxy, liquid phase epitaxy, and molecular beam epitaxy. The material of the epitaxial layer 203 can be the same as or different from the material of the substrate 201. For example, the epitaxial layer 203 can be made of any suitable material such as silicon carbide.

[0067] In some embodiments of this application, such as FIG. 3A As shown, before forming the epitaxial layer 203, a buffer layer 202 can also be formed on the substrate 201. The buffer layer 202 is located between the substrate 201 and the epitaxial layer 203. The buffer layer 202 enables better concentration matching between the epitaxial layer 203 and the substrate 201, which is beneficial for the precise control of the doping concentration of the epitaxial layer 203 during the growth process.

[0068] Next, proceed to step S2, as follows:FIGS. 3B-3E As shown, a first ion implantation is performed to form source regions 207 on top of the epitaxial layer 203.

[0069] Specifically, a patterned first mask layer is formed on the surface of the epitaxial layer 203 to form source region implantation windows (not shown in the figure) on both sides of the first mask layer for defining the source regions 207 to be formed. The first ion implantation is performed with the patterned first mask layer as a mask to form the source regions 207 on both sides of the first mask layer.

[0070] In one exemplary embodiment, the step of forming the well regions 205 is further included before forming the source regions 207, and the source regions 207 are formed within the well regions 205. In this case, the step of forming the well regions 205 can be as follows: FIGS. 3B-3C As shown, the step of forming the well regions 205 can be as follows:

[0071] A mask layer is formed on the surface of the epitaxial layer 203, and the mask layer is subjected to photolithography and etching to form a patterned mask layer 204 for defining the well regions 205 to be formed. Exemplarily, well region implantation windows (not shown in the figure) are defined on both sides of the patterned mask layer 204. The well ions are implanted into the surface layer of the epitaxial layer 203 with the patterned mask layer 204 as a mask to form the well regions 205 in the surface layer of the epitaxial layer 203 on both sides of the patterned mask layer 204. The mask layer can be made of polycrystalline silicon, SiO2, Si3N4 or any other suitable material, the well ions can be boron ions or boron fluoride ions, and the implantation direction can be perpendicular to the surface of the epitaxial layer 203.

[0072] After forming the well regions 205, as shown in FIG. 3D and FIG. 3E a sidewall 206 can be formed on the sidewall of the patterned mask layer 204 by, for example, a sidewall self-alignment process, the sidewall 206 shielding part of the well regions 205, and the patterned mask layer 204 and the sidewall 206 together forming a first mask layer. The first ion implantation is performed with the first mask layer as a mask to form the source regions 207 in the surface layer of the well regions 205 on both sides of the first mask layer. The material of the sidewall 206 can be the same as or different from that of the mask layer 204. Exemplarily, the material of the sidewall 206 can be polycrystalline silicon or any other suitable material.

[0073] After forming the source regions 207, the first mask layer on the surface of the epitaxial layer 203 can be removed by, for example, ashing, wet etching or the like, i.e. the patterned mask layer 204 and the sidewall 206 are removed.

[0074] Then, step S3 is performed, as shown in FIG. 3F A second ion implantation is performed to form a shielding region 208 in a plan view on top of the epitaxial layer 203.

[0075] Specifically, as shown inFIG. 3F As shown, a patterned second mask layer is formed on the surface of the epitaxial layer 203, the well region 205, and a portion of the source region 207 to form shielding region implantation windows (not shown) on both sides of the second mask layer to define the shielding region 208 to be formed. A second ion implantation is performed using the patterned second mask layer as a mask to implant second ions into the source region 207, the well region 205, and a portion of the epitaxial layer 203 below the well region 205, thereby forming the shielding region 208 longitudinally within the source region 207, the well region 205, and the portion of the epitaxial layer 203 below the well region 205. The second ion can be a diffusing boron ion or a non-diffusing aluminum ion, etc., and the top view of the formed shielding region 208 can be a structural representation.

[0076] After the shielding area 208 is formed, the second mask layer can be removed by means such as ashing or wet etching.

[0077] Next, proceed to step S4, as follows: FIG. 3G As shown, the epitaxial layer 203 between the source region 207 and the shielding region 208 is etched to form a trench in the epitaxial layer 203 as shown in the top view.

[0078] Specifically, a patterned third mask layer is formed on the surfaces of the well region 205, the source region 207, and the shielding region 208 to form a trench etching window (not shown) in the center of the third mask layer for defining the trench to be formed. The epitaxial layer 203 is etched using the patterned third mask layer as a mask to form a trench in the epitaxial layer 203, the depth of which exceeds that of the well region 205.

[0079] After the shielding area 208 is formed, the third mask layer can be removed by means such as ashing or wet etching.

[0080] Next, step S5 is performed to fill the trench to form a trench gate.

[0081] Specifically, such as FIG. 3G As shown, any suitable deposition method, such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition, can be used to form a gate dielectric layer 209 at the bottom and sidewalls of the trench. The material of the gate dielectric layer 209 can be silicon oxide or a high-k dielectric with a dielectric constant k greater than 7.

[0082] Then, as FIG. 3G As shown, any suitable deposition method, such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition, can be used to fill the gate material layer 210 in the gate dielectric layer 209. The gate material layer 210 can be a polycrystalline silicon material, such as N-type doped or P-type doped polycrystalline silicon.

[0083] Then, a planarization process such as chemical mechanical polishing can be performed to planarize the surface of the gate material layer 210 and the gate dielectric layer 209, so as to form a trench gate which is flush with the surface of the shielding region 208.

[0084] In one example, as shown in FIG. 2B, after forming the trench gate, an interlayer dielectric layer 211 can be formed above the trench gate, the partial well region 205 and the partial source region 207, and a contact metal layer 212 can be formed on the top and sidewall of the interlayer dielectric layer 211, which surrounds the interlayer dielectric layer 211 and serves as an insulating medium layer between the contact metal layer 212 and the epitaxial layer 203. The interlayer dielectric layer 211 can be made of at least one of silicon oxide, silicon nitride, silicon oxynitride and low-k dielectric with a dielectric constant k less than 3, and the contact metal layer 212 can be made of at least one of nickel Ni, aluminum Al, copper Cu, gold Au, titanium Ti, tungsten W, platinum Pt, silver Ag, etc. FIG. 3H

[0085] It is worth mentioning that the order of the above steps is only an example, and the order of the above steps can be changed or alternated without conflict.

[0086] The multi-channel trench MOS device formed by the above steps has an epitaxial layer in which a plurality of first device units and a plurality of second device units are formed, and the first device units and the second device units are arranged alternately, wherein: each of the first device units comprises one shielding region and four trench gates surrounding the shielding region, and a source region is formed in the trench gate; and each of the second device units comprises one trench gate and four shielding regions surrounding the trench gate, and a source region is formed in the trench gate.

[0087] Exemplarily, in a first cross section along a first direction, the shielding regions and the trench gates are arranged alternately, in a second cross section along the first direction, the trench gates and the source regions are arranged alternately, and in a cross section along a second direction, the trench gates and the source regions are arranged between adjacent shielding regions, and the second direction forms an angle of 45° with the first direction.

[0088] ​In summary, the multi-channel trench MOS device obtained by the manufacturing method of the present application, by alternately arranging the first device unit and the second device unit, makes the shielding region and the trench gate alternately arranged in the first cross section along the first direction, i.e. only the trench gate needs to be crossed between the adjacent shielding regions without crossing the source region, thereby shortening the distance between the shielding regions, and the multi-channel interface formed can increase the unit current; when the device is off, the induced current existing in the circuit can flow out of the device through the shielding region, thereby avoiding the device from burning out and increasing the surge capacity of the device; and the effective electric field coupling can occur through the shielding region, thereby protecting the gate oxide, reducing the electric field strength, and improving the voltage resistance and reliability of the device.

[0089] The present application has been described by the above-mentioned embodiments, but it should be understood that the above-mentioned embodiments are only for the purpose of example and illustration, and are not intended to limit the present application to the scope of the described embodiments. Furthermore, those skilled in the art can understand that the present application is not limited to the above-mentioned embodiments, and more various modifications and changes can be made according to the teachings of the present application, which all fall within the scope of the present application claimed. The scope of protection of the present application is defined by the attached claims and their equivalent scope.

Claims

1. A multi-channel trench MOS device, characterized by, The method comprises: providing a substrate, and forming an epitaxial layer on the substrate; performing a first ion implantation to form source regions on top of the epitaxial layer; performing a second ion implantation to form shielding regions on top of the epitaxial layer; etching the epitaxial layer between the source regions and the shielding regions to form trenches in the epitaxial layer; filling the trenches to form trench gates; wherein the epitaxial layer forms a plurality of first device units and a plurality of second device units, the first device units and the second device units are arranged alternately, wherein: each of the first device units comprises one shielding region and four trench gates surrounding the shielding region, and source regions are formed in the trench gates; each of the second device units comprises one trench gate and four shielding regions surrounding the trench gate, and source regions are formed in the trench gate; the shielding region is a regular quadrilateral, the trench gate is a regular octagon, and the length of the side of the shielding region is equal to the length of the side of the trench gate; 2. The multichannel trench MOS device of claim 1, wherein, in a first cross-section along a first direction, the shielding regions and the trench gates are arranged alternately, and there is no source region between the shielding regions and the trench gates.

3. The multichannel trench MOS device of claim 2, wherein, the shielding region is formed by ion implantation.

4. The multichannel trench MOS device of claim 1, wherein, in a second cross-section along the first direction, the trench gates and the source regions are arranged alternately.

5. The multichannel trench MOS device of claim 4, wherein, in a cross-section along a second direction, the trench gates and the source regions are arranged between adjacent shielding regions, and the second direction forms an angle of 45° with the first direction.

6. The multichannel trench MOS device of claim 1, wherein, the shielding region has a first conductivity type, and the source region has a second conductivity type.

7. A method for fabricating a multi-channel trench MOS device, comprising the steps of: the epitaxial layer further forms a well region, the well region has the first conductivity type, and the source region is formed in the well region. a plurality of repeatedly arranged device units form a double channel in the (11-20) direction and the (1-100) direction, and the first direction includes the (11-20) direction or the (1-100) direction. The method comprises: providing a substrate, and forming an epitaxial layer on the substrate; performing a first ion implantation to form source regions on top of the epitaxial layer; performing a second ion implantation to form shielding regions on top of the epitaxial layer; etching the epitaxial layer between the source regions and the shielding regions to form trenches in the epitaxial layer; filling the trenches to form trench gates; wherein the epitaxial layer forms a plurality of first device units and a plurality of second device units, the first device units and the second device units are arranged alternately, wherein: each of the first device units comprises one shielding region and four trench gates surrounding the shielding region, and source regions are formed in the trench gates; each of the second device units comprises one trench gate and four shielding regions surrounding the trench gate, and source regions are formed in the trench gate; 8. The method of claim 7, wherein, the shielding region is a regular quadrilateral, the trench gate is a regular octagon, and the length of the side of the shielding region is equal to the length of the side of the trench gate; in a first cross-section along a first direction, the shielding regions and the trench gates are arranged alternately, and there is no source region between the shielding regions and the trench gates. before forming the source region, a step of forming a well region is further included, and the source region is formed in the well region.

Images