A dual-phase peak current mode buck inductor current sampling and current sharing circuit

Abstract

This invention belongs to the field of power management technology, specifically relating to a dual-phase peak current mode Buck inductor current sampling and current sharing circuit. Based on a dual-phase peak current mode control loop, this invention proposes an inductor current sampling and current sharing circuit. The sampling section amplifies the voltage across the inductor current sampling resistor, thus enabling the setting of the sampling gain and increasing the design complexity of the subsequent comparator circuit. Furthermore, by combining the output of the sampling circuit with the current sharing circuit, it effectively solves the current mismatch problem caused by power inductor mismatch or parameter mismatch between the two phases.

Description

Technical Field

[0001] This invention belongs to the field of power management technology, specifically relating to a dual-phase peak current mode Buck inductor current sampling and current sharing circuit. Background Technology

[0002] With the development of information technology, power supply chips face increasingly larger load throughput, thus requiring them to operate effectively under heavy loads. Considering efficiency optimization and chip heat dissipation, multi-phase Buck converters have been adopted. By interleaving multiple phases in parallel, they can handle heavy loads while improving efficiency and reducing power transistor heat dissipation. However, multi-phase operation can lead to inductor current imbalances due to imperfect phase matching, sometimes necessitating the introduction of current-sharing circuits. Furthermore, Buck's current-mode control strategy is suitable for high-current applications because its current loop effectively limits the maximum current, preventing current from flowing into a single phase and exceeding the maximum inductor current. Summary of the Invention

[0003] This invention proposes an inductor current sampling and current sharing circuit based on a dual-phase peak current mode control loop. The sampling circuit can amplify the voltage across the inductor current sampling resistor, thus enabling the setting of the sampling gain and increasing the design difficulty of the subsequent comparator circuit. In addition, by combining the output of the sampling circuit with the current sharing circuit, the current mismatch problem caused by power inductor mismatch or parameter mismatch between the two phases can be effectively solved.

[0004] The technical solution of this invention is:

[0005] A dual-phase peak current-mode Buck inductor current sampling and current sharing circuit for a BUCK converter includes an inductor current sampling circuit and a current sharing circuit. The inductor current sampling circuit is used to sample the voltage V across the sampling resistor. SNS The voltage V is sampled and amplified to a ground reference voltage. SEN And a voltage V that reflects the average value of the inductor current. SENavThe inductor current sampling circuit includes a first current source, a second current source, a third current source, a fourth current source, a first resistor, a second resistor, a third resistor, a first transistor, a second transistor, a third transistor, a fourth transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, a first operational amplifier, a second operational amplifier, and a low-pass filter circuit.

[0006] The gate of the first transistor is connected to the positive terminal of the sampling resistor, its emitter is connected to the first current source and the base of the third transistor, and the collector of the first transistor is grounded.

[0007] The gate of the second transistor is connected to the negative terminal of the sampling resistor, its emitter is connected to the second current source and the base of the fourth transistor, and the collector of the second transistor is grounded.

[0008] The emitter of the third transistor is connected to the third current source and one end of the first resistor. The collector of the third transistor is connected to the drain and gate of the first NMOS transistor, the gate of the second NMOS transistor, the gate of the fifth NMOS transistor, and the gate of the sixth NMOS transistor.

[0009] The emitter of the fourth transistor is connected to the fourth current source and the other end of the first resistor. The collector of the fourth transistor is connected to the drain and gate of the third NMOS transistor, the gate of the fourth NMOS transistor, the gate of the seventh NMOS transistor, and the gate of the eighth NMOS transistor.

[0010] The source of the first NMOS transistor is connected to the drain of the second NMOS transistor, and the source of the second NMOS transistor is grounded; the source of the third NMOS transistor is connected to the drain of the fourth NMOS transistor, and the source of the fourth NMOS transistor is grounded; the source of the fifth NMOS transistor is connected to the drain of the sixth NMOS transistor, and the source of the sixth NMOS transistor is grounded; the source of the seventh NMOS transistor is connected to the drain of the eighth NMOS transistor, and the source of the eighth NMOS transistor is grounded.

[0011] The source of the first PMOS transistor is connected to the power supply, and its gate is connected to the gate and drain of the second PMOS transistor, the drain of the fifth NMOS transistor, the gate of the third PMOS transistor, and the gate of the fourth PMOS transistor. The drain of the first PMOS transistor is connected to the source of the second PMOS transistor.

[0012] The source of the third PMOS transistor is connected to the power supply, and its drain is connected to the source of the fourth PMOS transistor. The drain of the fourth PMOS transistor is connected to the drain of the seventh NMOS transistor, the gate and drain of the sixth PMOS transistor, the gate of the fifth PMOS transistor, the gate of the seventh PMOS transistor, the gate of the eighth PMOS transistor, the gate of the ninth PMOS transistor, and the gate of the tenth PMOS transistor.

[0013] The source of the fifth PMOS transistor is connected to the power supply, and its drain is connected to the source of the sixth PMOS transistor.

[0014] The source of the seventh PMOS transistor is connected to the power supply, and its drain is connected to the drain of the eighth PMOS transistor. The drain of the eighth PMOS transistor is connected to the output of the first operational amplifier through the second resistor. The positive input of the first operational amplifier is connected to the bias voltage, and the negative input of the first operational amplifier is connected to its output. The connection point between the eighth PMOS transistor and the second resistor outputs a reference voltage V to ground. SEN ;

[0015] The source of the ninth PMOS transistor is connected to the power supply, and its drain is connected to the source of the tenth PMOS transistor. The drain of the tenth PMOS transistor is connected to the output of the first operational amplifier through the third resistor.

[0016] The connection point between the drain of the tenth PMOS transistor and the third resistor is connected to the positive input of the second operational amplifier after passing through a low-pass filter circuit. The negative input of the second operational amplifier is connected to its output. The output of the second operational amplifier outputs a voltage V equal to the average value of the inductor current. SENav ;

[0017] The current sharing circuit includes an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, a fifteenth PMOS transistor, a sixteenth PMOS transistor, a seventeenth PMOS transistor, an eighteenth PMOS transistor, a nineteenth PMOS transistor, a twentieth PMOS transistor, a twenty-first PMOS transistor, a twenty-second PMOS transistor, a twenty-third PMOS transistor, a twenty-fourth PMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, a seventeenth NMOS transistor, an eighteenth NMOS transistor, a nineteenth NMOS transistor, a twentieth NMOS transistor, a first capacitor, a second capacitor, a fifth current source, and a sixth current source.

[0018] The source of the eleventh PMOS transistor is connected to the power supply, and its gate is connected to the gate and drain of the twelfth PMOS transistor, the gate of the thirteenth PMOS transistor, the gate of the fourteenth PMOS transistor, and the drain of the ninth NMOS transistor. The drain of the PMOS transistor shown in the diagram is connected to the source of the twelfth PMOS transistor.

[0019] The source of the ninth NMOS transistor is connected to the drain of the tenth NMOS transistor, and the gate of the ninth NMOS transistor is connected to the gate and drain of the eleventh NMOS transistor, the gate of the tenth NMOS transistor, the gate of the twelfth NMOS transistor, and the drain of the fifteenth PMOS transistor; the source of the eleventh NMOS transistor is connected to the drain of the twelfth NMOS transistor, and the sources of the tenth and twelfth NMOS transistors are grounded.

[0020] The gate of the fifteenth PMOS transistor is connected to the inductor current sampling voltage of the second phase sampled by the inductor current sampling circuit, defined as V. SENav2 The source of the fifteenth PMOS transistor is connected to the source of the sixth current source and the source of the sixteenth PMOS transistor.

[0021] The gate of the sixteenth PMOS transistor is connected to the inductor current sampling circuit, which samples the first phase of the inductor current sampling voltage, defined as V. SENav1 The drain of the sixteenth PMOS transistor is connected to the drain and gate of the thirteenth NMOS transistor, the gate of the fourteenth NMOS transistor, the gate of the fifteenth NMOS transistor, and the gate of the sixteenth NMOS transistor.

[0022] The source of the thirteenth NMOS transistor is connected to the drain of the fourteenth NMOS transistor, and the drain of the sixteenth NMOS transistor is connected to the source of the fifteenth NMOS transistor; the sources of the fourteenth and sixteenth NMOS transistors are grounded.

[0023] The source of the thirteenth PMOS transistor is connected to the power supply, and its drain is connected to the source of the fourteenth PMOS transistor. The drain of the fourteenth PMOS transistor is connected to the drain of the fifteenth NMOS transistor, the drain of the twenty-fourth PMOS transistor, the drain of the twentieth NMOS transistor, and one end of the first capacitor. The other end of the first capacitor is connected to the source of the twenty-fourth PMOS transistor, the source of the twentieth NMOS transistor, the source of the twenty-third PMOS transistor, the drain of the seventeenth PMOS transistor, and the gate of the twenty-second PMOS transistor.

[0024] The gate of the 24th PMOS transistor is connected to the power-on signal, and the gate of the 20th NMOS transistor is connected to the inverted power-on signal.

[0025] The source of the seventeenth PMOS transistor is connected to the power supply, and its gate is connected to the gate of the eighteenth PMOS transistor, the gate of the nineteenth PMOS transistor, the fifth current source, and the gate and drain of the twentieth PMOS transistor.

[0026] The source of the eighteenth PMOS transistor is connected to the power supply, and its drain is connected to the gate of the twenty-third PMOS transistor, one end of the second capacitor, and the drain of the seventeenth NMOS transistor; the drain of the twenty-third PMOS transistor and the source of the seventeenth NMOS transistor are grounded.

[0027] The gate of the seventeenth NMOS transistor is connected to the other end of the second capacitor, the drain of the twenty-first PMOS transistor, and the drain of the nineteenth NMOS transistor.

[0028] The source of the nineteenth PMOS transistor is connected to the power supply, and its drain is connected to the source of the twenty-first PMOS transistor and the source of the twenty-second PMOS transistor.

[0029] The drain of the 22nd PMOS transistor is connected to the drain and gate of the 18th NMOS transistor and the gate of the 19th NMOS transistor, while the source of the 18th NMOS transistor and the source of the 19th NMOS transistor are grounded.

[0030] The source of the 20th PMOS transistor is connected to the power supply, and the gate of the 21st PMOS transistor is connected to the output voltage of the error amplifier in the BUCK converter.

[0031] The beneficial effects of this invention are as follows: The inductor current sampling and current sharing circuit proposed in this invention can be applied to the Buck chip with dual-phase peak current mode control, which can achieve high-precision sampling of inductor current while avoiding current mismatch between phases. Attached Figure Description

[0032] Figure 1 This is a block diagram of a dual-phase peak current-mode Buck system suitable for the present invention.

[0033] Figure 2 This is a block diagram of the inductor current sampling and current sharing circuit of the present invention.

[0034] Figure 3 This is the circuit for the inductor current sampling section of the present invention.

[0035] Figure 4 This is the circuit for the inductor current sampling and current sharing control section of the present invention.

[0036] Figure 5 This is a simulation of the loop stability of the current sharing control circuit for inductor current sampling in this invention.

[0037] Figure 6 This is a time-domain simulation diagram of the inductor current sampling circuit of this invention.

[0038] Figure 7 This is a time-domain simulation of the current sharing function of the current sampling and current sharing control circuit of the present invention.

[0039] Figure 8 This is a time-domain transient simulation of the current sharing function of the current sampling and current sharing control circuit of the inductor current in this invention. Detailed Implementation

[0040] The invention will now be further described with reference to the accompanying drawings.

[0041] This invention amplifies the voltage sampled by the resistor to control the loop sampling gain; it also allows for current sharing of the inductor currents in the two phases.

[0042] Figure 1 This is a block diagram of a dual-phase peak current-mode Buck chip system to which this invention applies. The main point is that this invention is applicable to the control voltage V output of this dual-phase shared unified error amplifier EA. C The multi-phase scheme has a separate sampling circuit for each phase and an output signal of the clock OSC.

[0043] Figure 2 This is a block diagram of the inductor current sampling and current sharing circuit of the present invention. First, the sampling module samples the current through the sampling resistor R. SNS Voltage V at both ends SNS The voltage V is sampled and amplified to a ground reference voltage. SEN And a voltage V that reflects the average value of the inductor current. SENav For the current sharing circuit of this invention, the sampling master-slave current sharing approach involves using one phase as the master phase, and adjusting the current sharing module to make the other phases follow the inductor current of the master phase. For the peak current mode, the inductor current and its control voltage satisfy the following relationship:

[0044] I L ·R i =V C (1)

[0045] Where I L R is the inductor current. i This is the inductor current sampling gain, the magnitude of which will be explained later. V C The output voltage of the error amplifier EA is used. Therefore, this paper detects the average current of the two phases to obtain the common control voltage V. C By dynamically adjusting the control voltage of the second phase as a reference, the current sharing of the inductor current can be achieved, as explained below. Figure 2 As shown in the lower dashed box, with the first phase as the main phase, the control voltage V generated by the loop is... C As its peak voltage, the second phase no longer directly uses Vc as its peak voltage, but instead dynamically adjusts Vc through a transconductance amplifier. C Get V C1 As the peak voltage, since the input of the transconductance amplifier is the average inductor current of each of the two phases, therefore, when V C1 When stable, this means that the average inductance currents of the two phases are basically the same. For example, when the current in the first phase is larger, the transconductance amplifier's response to capacitor C... F Charging, voltage V C2The rising phase means that the inductor current in the second phase increases. Since the total load current remains unchanged, the current in the first phase decreases, and eventually the two phases gradually become equal.

[0046] Figure 3 and Figure 4 The circuit diagram shows the specific inductor current sampling circuit and current sharing circuit. The inductor current sampling structure of this invention is as follows: Figure 2 As shown in the figure, the sampling resistor sampling method is used to detect the sampling resistor R. SNS The sampling voltages at both ends are V SNSP and V SNSN The ripple voltage V can be obtained by subtracting the voltage across the resistor sampled by the inductor current sampling circuit. SNS This voltage reflects the magnitude of the inductor current and its ripple. Since the sampling resistor is only 1-2 mΩ, the sampled voltage ripple information is only about 10-15 mV. If this voltage is directly introduced into the PWM, it will be limited by the PWM input accuracy, causing offset. Therefore, the inductor current sampling circuit needs to amplify the sampling gain to optimize this problem. Furthermore, the voltage V... SNS The relationship that satisfies is V SNS =I L R SNS If the inductor current is 0, then V SNS This value is also close to 0, which limits the design of the circuit's common-mode range. Therefore, the inductor current sampling circuit also needs to generate a zero-bias voltage for the inductor current. The inductor current sampling circuit of this invention is as follows: Figure 3 As shown, the sampling and input stage first shifts the voltage level across the sampling resistor by the emitter-base voltage of a transistor to prevent insufficient common-mode input range. Additionally, transistors T3 and T4, along with resistor R... N1 The sampled voltage can be converted into two current streams, satisfying the following relationship:

[0047]

[0048]

[0049] For bias current I S2 The setting needs to be much larger than (V) SNSP -V SNSN ) / R N1 In this way, the circuit I1 and I2 will not have excessive misalignment.

[0050] After passing through the subsequent current mirror, currents I1 and I2 flow into and out of node X respectively, resulting in current I3, the magnitude of which is...

[0051]

[0052] Current I3 flows through resistor R N2 and R N3 Two voltages V are obtained. SEN and V SEN1 Their respective sizes are

[0053]

[0054]

[0055] Therefore, by converting the current to a voltage level, it can be observed that the inductor current sampling gain is increased by 2R. N3 / R N1 and 2R N2 / R N1 Times, by setting the resistor R N1 R N2 R N3 The ratio relationship ultimately enables amplification of the inductor current sampling gain, while simultaneously controlling the voltage V. SEN_bias The value of the control voltage VC can be set when the inductor current is zero. Two voltages V were sampled and obtained. SEN and V SEN1 The former can be controlled by inputting PWM, in which case the inductor current sampling gain is Ri = R SNS ·2R N3 / R N1 The latter is used for current sharing control of the subsequent inductor current, through R L1 C L1 The low-pass filter structure is used to obtain the DC value V of the inductor current. SNEav The input is fed into the subsequent current sharing circuit. For the low-pass filter constant, it is necessary to ensure that R... L1 C L1 >>1 / f SW .

[0056] The circuit of the current sharing section of the inductor in this invention is as follows: Figure 4 As shown. Due to inductor mismatch or incomplete phase matching during inductor current sampling, inductor current will experience mismatch issues, causing different heat generation between phases and reducing efficiency. Therefore, when sharing the same control voltage V... C In a two-phase parallel configuration, inductor mismatch leads to inconsistent peak-to-peak inductor currents between phases, resulting in unequal average inductor currents. The current-sharing principle of this invention is to dynamically adjust the control voltage V for all phases except the first phase by detecting the average inductor current of each phase. Ci This achieves a balance in the average inductor current. The current sharing circuit includes a voltage buffer stage, which balances the capacitor C. F The lower electrode is set to control voltage VC The size of the capacitor C is determined by the transconductance amplification stage, which detects the phase difference between two phases. F The upper plate is charged and discharged. Taking a two-phase system as an example, the first phase is the main control phase, and its control voltage is V. C The second phase is V C1 First, through the inductor current sampling circuit, the average inductor current sampling voltage V for each of the two phases is obtained. SENav1 and V SENav2 Through the transconductance amplification stage, V will be SENav1 and V SENav2 The voltage difference is converted into current and supplied to capacitor C. F Charging and discharging, through V C The unity-gain negative feedback loop of the buffer stage, capacitor C F The size of the lower electrode is V C Thus, if V SENav1 >V SENav2 That is, the average inductor current of the first phase is greater than that of the second phase, and the transconductance amplifier stage is related to capacitor C. F Charging, V C2 Start comparing V C Big, V SENav1 and V SENav2 They gradually become equal, at which point V C1 The current remains constant at the beginning, thus completing the current balancing process.

[0057] For capacitor C F The numerical design takes into account the multi-stage low-pass filter circuit of the inductor current sampling circuit. Since the entire inductor current sharing circuit consists of low-frequency information, it will not affect the main loop of the peak current mode. If C... F Too small, will V SENav1 and V SENav2 The introduction of high-frequency disturbance information in the capacitor C causes oscillation, thus affecting the capacitance C. F The settings should meet the following requirements.

[0058]

[0059] Among them G m This represents the overall transconductance of the transconductance amplification stage in the current-sharing circuit. Typically, the value of CF is between 10pF and 40pF. If the switching frequency f... SW It is 1MHz.

[0060] Considering the chip power-on process, a transmission gate composed of MOSFETs MN20 and MP24 is opened by logic level EN3 during power-on, allowing V to... C1 =V C Once power-on is complete, the transmission gate is closed, which enables the current sharing function.

[0061] Figure 5 For current sharing circuit V C The loop stability simulation diagram of the buffer stage can be guaranteed by properly setting the Miller capacitor.

[0062] Figure 6 The simulation diagram of the inductor current sampling circuit shows that the present invention can effectively amplify the voltage across the inductor current sampling resistor and convert it into a voltage reference to the chip ground, with no obvious distortion in the ripple voltage.

[0063] Figure 7 This is a time-domain simulation diagram of the inductor current sharing function of the present invention. After the chip is powered on, the current sharing circuit is enabled, and the control voltage V of the two phases is dynamically adjusted. C and V C1 Ultimately, this achieves the equality of the average inductor current.

[0064] Figure 8 The transient simulation diagram of the current sharing function of the inductor current of the present invention shows that once the inductor current is balanced, the current sharing function continues to work regardless of the magnitude of the transient, without affecting the transient performance.

[0065] In fact, the circuit of this invention can be extended to more phase peak current mode Buck according to the master-slave multi-phase control mode. The principle is the same, so it will not be described again.

Claims

1. A dual-phase peak current-mode Buck inductor current sampling and current sharing circuit for a BUCK converter, characterized in that, It includes an inductor current sampling circuit and a current sharing circuit. The inductor current sampling circuit is used to sample the voltage V across the sampling resistor. SNS The voltage V is sampled and amplified to a ground reference voltage. SEN And a voltage V that reflects the average value of the inductor current. SENav The inductor current sampling circuit includes a first current source, a second current source, a third current source, a fourth current source, a first resistor, a second resistor, a third resistor, a first transistor, a second transistor, a third transistor, a fourth transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, a first operational amplifier, a second operational amplifier, and a low-pass filter circuit. The base of the first transistor is connected to the positive terminal of the sampling resistor, its emitter is connected to the base of the first current source and the third transistor, and the collector of the first transistor is grounded. The base of the second transistor is connected to the negative terminal of the sampling resistor, its emitter is connected to the base of the second current source and the fourth transistor, and the collector of the second transistor is grounded. The emitter of the third transistor is connected to the third current source and one end of the first resistor. The collector of the third transistor is connected to the drain and gate of the first NMOS transistor, the gate of the second NMOS transistor, the gate of the fifth NMOS transistor, and the gate of the sixth NMOS transistor. The emitter of the fourth transistor is connected to the fourth current source and the other end of the first resistor. The collector of the fourth transistor is connected to the drain and gate of the third NMOS transistor, the gate of the fourth NMOS transistor, the gate of the seventh NMOS transistor, and the gate of the eighth NMOS transistor. The source of the first NMOS transistor is connected to the drain of the second NMOS transistor, and the source of the second NMOS transistor is grounded; the source of the third NMOS transistor is connected to the drain of the fourth NMOS transistor, and the source of the fourth NMOS transistor is grounded; the source of the fifth NMOS transistor is connected to the drain of the sixth NMOS transistor, and the source of the sixth NMOS transistor is grounded; the source of the seventh NMOS transistor is connected to the drain of the eighth NMOS transistor, and the source of the eighth NMOS transistor is grounded. The source of the first PMOS transistor is connected to the power supply, and its gate is connected to the gate and drain of the second PMOS transistor, the drain of the fifth NMOS transistor, the gate of the third PMOS transistor, and the gate of the fourth PMOS transistor. The drain of the first PMOS transistor is connected to the source of the second PMOS transistor. The source of the third PMOS transistor is connected to the power supply, and its drain is connected to the source of the fourth PMOS transistor. The drain of the fourth PMOS transistor is connected to the drain of the seventh NMOS transistor, the gate and drain of the sixth PMOS transistor, the gate of the fifth PMOS transistor, the gate of the seventh PMOS transistor, the gate of the eighth PMOS transistor, the gate of the ninth PMOS transistor, and the gate of the tenth PMOS transistor. The source of the fifth PMOS transistor is connected to the power supply, and its drain is connected to the source of the sixth PMOS transistor. The source of the seventh PMOS transistor is connected to the power supply, and its drain is connected to the drain of the eighth PMOS transistor. The drain of the eighth PMOS transistor is connected to the output of the first operational amplifier through the second resistor. The positive input of the first operational amplifier is connected to the bias voltage, and the negative input of the first operational amplifier is connected to its output. The voltage V output from the junction of the eighth PMOS transistor and the second resistor is a reference voltage to ground. SEN ; The source of the ninth PMOS transistor is connected to the power supply, and its drain is connected to the source of the tenth PMOS transistor. The drain of the tenth PMOS transistor is connected to the output of the first operational amplifier through the third resistor. The connection point between the drain of the tenth PMOS transistor and the third resistor is connected to the positive input of the second operational amplifier after passing through a low-pass filter circuit. The negative input of the second operational amplifier is connected to its output. The output of the second operational amplifier outputs a voltage V equal to the average value of the inductor current. SENav ; The current sharing circuit includes an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, a fifteenth PMOS transistor, a sixteenth PMOS transistor, a seventeenth PMOS transistor, an eighteenth PMOS transistor, a nineteenth PMOS transistor, a twentieth PMOS transistor, a twenty-first PMOS transistor, a twenty-second PMOS transistor, a twenty-third PMOS transistor, a twenty-fourth PMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, a seventeenth NMOS transistor, an eighteenth NMOS transistor, a nineteenth NMOS transistor, a twentieth NMOS transistor, a first capacitor, a second capacitor, a fifth current source, and a sixth current source. The source of the eleventh PMOS transistor is connected to the power supply, and its gate is connected to the gate and drain of the twelfth PMOS transistor, the gate of the thirteenth PMOS transistor, the gate of the fourteenth PMOS transistor, and the drain of the ninth NMOS transistor. The drain of the eleventh PMOS transistor is connected to the source of the twelfth PMOS transistor. The source of the ninth NMOS transistor is connected to the drain of the tenth NMOS transistor, and the gate of the ninth NMOS transistor is connected to the gate and drain of the eleventh NMOS transistor, the gate of the tenth NMOS transistor, the gate of the twelfth NMOS transistor, and the drain of the fifteenth PMOS transistor; the source of the eleventh NMOS transistor is connected to the drain of the twelfth NMOS transistor, and the sources of the tenth and twelfth NMOS transistors are grounded. The gate of the fifteenth PMOS transistor is connected to the inductor current sampling voltage of the second phase sampled by the inductor current sampling circuit, defined as V. SENav2 The source of the fifteenth PMOS transistor is connected to the source of the sixth current source and the source of the sixteenth PMOS transistor. The gate of the sixteenth PMOS transistor is connected to the inductor current sampling circuit, which samples the first phase of the inductor current sampling voltage, defined as V. SENav1 The drain of the sixteenth PMOS transistor is connected to the drain and gate of the thirteenth NMOS transistor, the gate of the fourteenth NMOS transistor, the gate of the fifteenth NMOS transistor, and the gate of the sixteenth NMOS transistor. The source of the thirteenth NMOS transistor is connected to the drain of the fourteenth NMOS transistor, and the drain of the sixteenth NMOS transistor is connected to the source of the fifteenth NMOS transistor; the sources of the fourteenth and sixteenth NMOS transistors are grounded. The source of the thirteenth PMOS transistor is connected to the power supply, and its drain is connected to the source of the fourteenth PMOS transistor. The drain of the fourteenth PMOS transistor is connected to the drain of the fifteenth NMOS transistor, the drain of the twenty-fourth PMOS transistor, the drain of the twentieth NMOS transistor, and one end of the first capacitor. The other end of the first capacitor is connected to the source of the twenty-fourth PMOS transistor, the source of the twentieth NMOS transistor, the source of the twenty-third PMOS transistor, the drain of the seventeenth PMOS transistor, and the gate of the twenty-second PMOS transistor. The gate of the 24th PMOS transistor is connected to the power-on signal, and the gate of the 20th NMOS transistor is connected to the inverted power-on signal. The source of the seventeenth PMOS transistor is connected to the power supply, and its gate is connected to the gate of the eighteenth PMOS transistor, the gate of the nineteenth PMOS transistor, the fifth current source, and the gate and drain of the twentieth PMOS transistor. The source of the eighteenth PMOS transistor is connected to the power supply, and its drain is connected to the gate of the twenty-third PMOS transistor, one end of the second capacitor, and the drain of the seventeenth NMOS transistor; the drain of the twenty-third PMOS transistor and the source of the seventeenth NMOS transistor are grounded. The gate of the seventeenth NMOS transistor is connected to the other end of the second capacitor, the drain of the twenty-first PMOS transistor, and the drain of the nineteenth NMOS transistor. The source of the nineteenth PMOS transistor is connected to the power supply, and its drain is connected to the source of the twenty-first PMOS transistor and the source of the twenty-second PMOS transistor. The drain of the 22nd PMOS transistor is connected to the drain and gate of the 18th NMOS transistor and the gate of the 19th NMOS transistor, while the source of the 18th NMOS transistor and the source of the 19th NMOS transistor are grounded. The source of the 20th PMOS transistor is connected to the power supply, and the gate of the 21st PMOS transistor is connected to the output voltage of the error amplifier in the BUCK converter.

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