A delay chain circuit with configurable delay time length

Abstract

The application discloses a delay chain circuit with configurable delay time, and relates to the field of digital circuits.The delay chain circuit comprises a coarse adjustment module and a fine adjustment module.The coarse adjustment module is controlled by a coarse adjustment configuration signal in configuration signals and generates two loopback outputs corresponding to the coarse adjustment configuration signal.The fine adjustment module is controlled by a fine adjustment configuration signal in the configuration signals and performs phase interpolation on the two loopback outputs to generate a clock output signal with equal delay difference.The delay time of the clock output signal relative to a clock input signal corresponds to the configuration signal obtained by the delay chain circuit, so that the delay time from input to output can be changed by changing the configuration signal, thereby obtaining the required delay time, avoiding the delay uncertainty of a traditional delay phase-locked loop circuit, and enabling flexible and accurate configuration of the delay time.

Description

TECHNICAL FIELD

[0001] The application relates to the field of digital circuits, in particular to a delay chain circuit with configurable delay time. BACKGROUND

[0002] The delay chain circuit is a kind of delay-locked loop circuit, which is mainly used for phase delay compensation and clock adjustment in digital circuits. A traditional simple delay-locked loop circuit includes four cascaded delay units and a phase detector. The phase difference between the input clock and the output clock of the last delay unit is detected by inserting the phase detector, so as to generate a proportional average voltage to negatively feedback and adjust the delay time of each delay unit.

[0003] For a large loop gain, the phase difference between the input clock and the output clock of the last delay unit is small, that is, the four cascaded delay units delay the input clock by almost exactly one clock period, so as to establish an accurate clock edge interval. However, in fact, the total delay time generated by the four cascaded delay units cannot be exactly equal to one clock period, so that the four cascaded delay units may delay the input clock by one clock period or two clock periods, so that the time interval of adjacent clock edges may be fixed at 2 / 4 clock periods instead of 1 / 4 clock periods, and the interval of adjacent clock edges is uncertain, and the delay is uncertain. SUMMARY

[0004] In view of the above problems and technical requirements, the applicant proposes a delay chain circuit with configurable delay time. The technical scheme of the application is as follows:

[0005] The delay chain circuit includes a coarse adjustment module and a fine adjustment module. The coarse adjustment module includes M cascaded delay units and a plurality of data selectors. The data selectors are connected to form a loopback structure. The input end of the first delay unit obtains a clock input signal. The two output ends of the loopback structure formed by the data selectors are connected to the fine adjustment module. The coarse adjustment module controls the conduction state of each data selector according to a coarse adjustment configuration signal obtained from a configuration end, and generates and outputs a first loopback output Va and a second loopback output Vb corresponding to the coarse adjustment configuration signal to the fine adjustment module. The phase difference between the first loopback output Va and the second loopback output Vb is the delay time generated by one delay unit.

[0006] The fine adjustment module performs phase interpolation between the obtained first loopback output Va and the obtained second loopback output Vb according to a fine adjustment configuration signal obtained from the configuration end, to generate a clock output signal with a delay time corresponding to the configuration signal relative to the clock input signal. The configuration signal includes the coarse adjustment configuration signal provided to the coarse adjustment module and the fine adjustment configuration signal provided to the fine adjustment module.

[0007] The further technical scheme is that the coarse adjustment module comprises M basic modules which are cascaded in sequence, each basic module comprises a delay unit and a plurality of data selectors, the delay units in the M basic modules are connected in sequence to form a cascade structure, the data selectors in the M basic modules are connected in sequence to form a loopback structure, and the control ends of the plurality of data selectors in the same basic module are connected.

[0008] The first input end of the delay unit in the first basic module obtains a clock input signal, the second input end of the delay unit in the first basic module is connected to a high level, and the first input end of the delay unit in each of the other basic modules is connected to the output end of the delay unit in the previous basic module, and the second input end is connected to the control end of the data selector in the previous basic module.

[0009] The further technical scheme is that each basic module comprises a data selector MUX1 and a data selector MUX2, and the loopback structure formed by the data selectors in each basic module comprises:

[0010] The first input end of the MUX1 in each basic module is connected to the output end of the delay unit in the same basic module, the second input end of the MUX1 is connected to the output end of the MUX1 in the next basic module, the output end of the MUX1 in the first basic module is connected to the second loopback output Vb of the fine adjustment module, and the second input end of the MUX1 in the last basic module is connected to a high level.

[0011] The first input end of the MUX2 in each basic module is connected to the first input end of the delay unit in the same basic module, the second input end of the MUX2 is connected to the output end of the MUX2 in the next basic module, the output end of the MUX2 in the first basic module is connected to the first loopback output Va of the fine adjustment module, and the second input end of the MUX2 in the last basic module is connected to a high level.

[0012] The control ends of the data selectors in the same basic module obtain a high level, the MUX1 and the MUX2 are simultaneously turned on at the second input ends thereof, or the control ends of the data selectors in the same basic module obtain a low level, and the MUX1 and the MUX2 are simultaneously turned on at the first input ends thereof.

[0013] The further technical scheme is that the method for controlling the turn-on state of each data selector by the coarse adjustment module according to the coarse adjustment configuration signal obtained from the configuration end comprises:

[0014] The binary coarse adjustment configuration signal obtained by the configuration end is converted into a decimal value Q by a conversion unit; a high level is provided to the control end of the data selector in the first Q-1 basic modules, so that the MUX1 and MUX2 in the first Q-1 basic modules are simultaneously turned on to the second input end; and a low level is provided to the control end of the data selector in the Qth basic module, so that the MUX1 and MUX2 in the Qth basic module are simultaneously turned on to the first input end.

[0015] Further, in each delay unit, the first input end of the first NAND gate is connected to the second input end of the delay unit, the second input end of the first NAND gate is connected to the first input end of the delay unit, the output end of the first NAND gate is connected to the second input end of the second NAND gate, the first input end of the second NAND gate is connected to the second input end of the delay unit, and the output end of the second NAND gate is connected to the output end of the delay unit through an inverter.

[0016] Further, the fine adjustment module comprises a data selector MUX3, a data selector MUX4 and a phase interpolation circuit, the first input end of the MUX3 is connected to the first loopback output Va obtained by the coarse adjustment module, the first loopback output Va is inverted by an inverter to generate a Va_0 output to the second input end of the MUX3 and the first input end of the MUX4, the second input end of the MUX4 is connected to the second loopback output Vb obtained by the coarse adjustment module; the output end of the MUX3 is connected to one input end of the phase interpolation circuit, the output end of the MUX4 is connected to the other input end of the phase interpolation circuit, and the output end of the phase interpolation circuit outputs a clock output signal through an inverter.

[0017] The phase difference between the Va_0 and the first loopback output Va and the second loopback output Vb is equal, the control ends of the MUX3 and the MUX4 are connected to simultaneously turn on the first input ends or the second input ends of the MUX3 and the MUX4, the fine adjustment module controls the conduction states of the MUX3 and the MUX4 and the working state of the phase interpolation circuit according to the fine adjustment configuration signal obtained by the configuration end.

[0018] Further, the delay chain circuit further comprises a zero delay module and a calibration module, the clock input signal is provided to the calibration module through the zero delay module, the clock output signal generated by the fine adjustment module is also provided to the calibration module, the calibration module generates a calibration signal according to the input signals, and the calibration signal is used to indicate the delay time length between the clock output signal and the clock input signal.

[0019] The method for generating the configuration signal of the delay chain circuit comprises: adjusting the configuration signal of the delay chain circuit according to the calibration signal until the clock output signal has a target delay time length relative to the clock input signal.

[0020] Further, the calibration module comprises a first trigger unit, a second trigger unit and a phase detector, the clock signal output by the zero delay module is connected to the first input end of the phase detector through the first trigger unit, the clock output signal is connected to the second input end of the phase detector through the second trigger unit, and the output end of the phase detector is connected to the output end of the calibration module and is used for outputting a calibration signal; the output of the first trigger unit is switched from low level to high level at the rising edge of the (N+1)th clock cycle of the clock input signal, the output of the second trigger unit is switched from low level to high level at the rising edge of the first clock cycle of the clock output signal, and N is a parameter and the initial value is 1.

[0021] Further, the method for generating the configuration signal of the delay chain circuit comprises:

[0022] The configuration signal is adjusted in sequence until the calibration signal output by the calibration module is switched from low level to high level, and the configuration signal that makes the clock output signal have the target delay time length of N clock cycles relative to the clock input signal is obtained.

[0023] The phase detector outputs low level when the phase of the signal at the first input end is later than the phase of the signal at the second input end, and outputs high level when the phase of the signal at the first input end is not later than the phase of the signal at the second input end.

[0024] Further, N=1, the first trigger unit comprises a first DQ flip-flop and a second DQ flip-flop, the clock signal output by the zero delay module is connected to the clock end of the first DQ flip-flop and the clock end of the second DQ flip-flop, the input end D of the first DQ flip-flop obtains the enable signal of the calibration module, the output end Q of the first DQ flip-flop is connected to the input end D of the second DQ flip-flop through two inverters connected in sequence, and the output end Q of the second DQ flip-flop is connected to the first input end of the phase detector; the signal output by the output end Q of the second DQ flip-flop has a delay time length of one clock cycle relative to the clock input signal.

[0025] The second trigger unit comprises a third DQ flip-flop, the clock output signal is connected to the clock end of the third DQ flip-flop, the input end D of the third DQ flip-flop obtains the enable signal of the calibration module, and the output end Q of the third DQ flip-flop is connected to the second input end of the phase detector.

[0026] The beneficial technical effects of the application are:

[0027] The application discloses a delay chain circuit with configurable delay time, which comprises a coarse adjustment module controlled by a coarse adjustment configuration signal in configuration signals and a fine adjustment module controlled by a fine adjustment configuration signal in the configuration signals. The clock output signal with the required delay time relative to the clock input signal can be obtained by using the coarse adjustment module and the fine adjustment module, i.e. the delay time corresponds to the configuration signal, thereby avoiding the delay uncertainty of the traditional delay-locked loop circuit, and the delay time can be accurately configured.

[0028] Moreover, the delay time of the clock output signal relative to the clock output signal corresponds to the configuration signal, so that the clock output signal with different delay time can be obtained by changing the configuration signal, and the delay time is flexible and adjustable.

[0029] The delay chain circuit further comprises a calibration module, by which the required configuration signal can be accurately calibrated, so that the required clock output signal can be accurately output. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 FIG. 1 is a circuit structure diagram of the delay chain circuit in one embodiment of the application.

[0031] Figure 2 FIG. 2 is a circuit structure diagram of a single delay unit in one embodiment of the application.

[0032] Figure 3 FIG. 3 is a circuit structure diagram of the fine adjustment module in one embodiment of the application.

[0033] Figure 4 FIG. 4 is a circuit structure diagram of the delay chain circuit in another embodiment of the application.

[0034] Figure 5 FIG. 5 is a circuit structure diagram of the calibration module in one embodiment of the application.

[0035] Figure 6 FIG. 6 is a working timing diagram under two configuration signals in one example, (a) is a working timing diagram when the configuration signal is 000000000, and (b) is a working timing diagram when the configuration signal is 011010010. DETAILED DESCRIPTION

[0036] The specific embodiments of the application will be further described in combination with the drawings.

[0037] The application discloses a delay chain circuit with configurable delay time, please refer to Figure 1The delay chain circuit comprises a coarse adjustment module and a fine adjustment module. The coarse adjustment module comprises a configuration end, and the coarse adjustment module obtains a coarse adjustment configuration signal S1 through the configuration end. The fine adjustment module comprises a configuration end, and the fine adjustment module obtains a fine adjustment configuration signal S2 through the configuration end. The coarse adjustment configuration signal S1 and the fine adjustment configuration signal S2 are both from a configuration signal provided to the delay chain circuit. In an embodiment, the configuration signal, the coarse adjustment configuration signal S1 and the fine adjustment configuration signal S2 are all in binary format, and the configuration signal is spliced from the coarse adjustment configuration signal S1 and the fine adjustment configuration signal S2. For example, the coarse adjustment configuration signal S1 is a high bit part of the configuration signal, and the fine adjustment configuration signal S2 is a low bit part of the configuration signal.

[0038] The coarse adjustment module comprises M delay units connected in sequence and a plurality of data selectors. Each delay unit is used to form the same delay time. The data selectors are connected to form a loopback structure, and the output ends of the delay units are all connected to the loopback structure formed by the data selectors. The input end of the first delay unit obtains a clock input signal clk_in. Two output ends of the loopback structure formed by the data selectors are connected to the fine adjustment module. The coarse adjustment module controls the conduction state of each data selector according to the coarse adjustment configuration signal S1 obtained through the configuration end, and generates a first loopback output Va and a second loopback output Vb corresponding to the coarse adjustment configuration signal S1 and outputs to the fine adjustment module. The phase difference between the first loopback output Va and the second loopback output Vb is the delay time of one delay unit.

[0039] The fine adjustment module performs phase interpolation between the first loopback output Va and the second loopback output Vb obtained according to the fine adjustment configuration signal S2 obtained according to the configuration bit, and finally generates a clock output signal clk_out having a delay time corresponding to the complete configuration signal obtained with respect to the clock input signal clk_in, so as to realize the adjustment of the delay time.

[0040] In an embodiment, the coarse adjustment module comprises M basic modules connected in sequence, as shown in Figure 1 Each basic module comprises a delay unit and a plurality of data selectors. The delay units in the M basic modules are connected in sequence to form a cascade structure, and the data selectors in the M basic modules are connected in sequence to form a loopback structure. The control ends of the plurality of data selectors in the same basic module are connected.

[0041] The first input end In1 of the delay unit in the first basic module obtains the clock input signal clk_in, and the second input end In2 of the delay unit in the first basic module is connected to a high level. The first input end In1 of the delay unit in each of the remaining basic modules is connected to the output end Out of the delay unit in the previous basic module, and the second input end In2 of the delay unit in each of the remaining basic modules is connected to the control end of the data selector in the previous basic module. For example,Figure 1 In the basic module 1, the control terminals of the two data selectors MUX1 and MUX2 are connected to ctrl[0], and the second input terminal In2 of the delay unit in the basic module 2 is connected to the control terminal of the data selector in the basic module 1, i.e. to ctrl[0]. Similarly, in the basic module 2, the control terminals of the two data selectors MUX1 and MUX2 are connected to ctrl[1], and the second input terminal In2 of the delay unit in the basic module 3 is connected to the control terminal of the data selector in the basic module 2, i.e. to ctrl[1]. Although not shown in the figure, the same applies to the subsequent basic modules.

[0042] The delay unit in each basic module has the same structure and is used to realize delay. Please refer to Figure 2 In one embodiment, in each delay unit, the first input terminal of the first NAND gate NAND1 is connected to the second input terminal In2 of the delay unit, and the second input terminal of the first NAND gate NAND1 is connected to the first input terminal In1 of the delay unit. The output terminal of the first NAND gate NAND1 is connected to the second input terminal of the second NAND gate NAND2, the first input terminal of the second NAND gate NAND2 is connected to the second input terminal In2 of the delay unit, and the output terminal of the second NAND gate NAND2 is connected to a plurality of inverters connected in sequence and then connected to the output terminal Out of the delay unit. Figure 2 Only one inverter is shown. When the coarse adjustment configuration signal is changed, In2 will also change, and when In2 is 0, the delay information represented by In1 will be blocked and will not be transmitted to the next stage.

[0043] In one embodiment, each basic module includes a data selector MUX1 and a data selector MUX2, and the data selectors in each basic module form a loopback structure including, please refer to Figure 1 The first input terminal of MUX1 in each basic module is connected to the output terminal Out of the delay unit in the same basic module, the second input terminal of MUX1 is connected to the output terminal of MUX1 in the next basic module, the output terminal of MUX1 in the first basic module is connected to the fine adjustment module to output the second loopback output Vb, and the second input terminal of MUX1 in the last basic module is connected to high level. The first input terminal of MUX2 in each basic module is connected to the first input terminal In1 of the delay unit in the same basic module, the second input terminal of MUX2 is connected to the output terminal of MUX2 in the next basic module, the output terminal of MUX2 in the first basic module is connected to the fine adjustment module to output the first loopback output Va, and the second input terminal of MUX2 in the last basic module is connected to high level.

[0044] Since the control terminals of the data selectors in the same basic module are connected, the on-off states of the data selectors in the same basic module are the same. In this application, when the control terminal of the data selector in the same basic module obtains a high level, the MUX1 and MUX2 in the basic module are turned on at the second input terminals, that is, the MUX in the basic module selects the output of the MUX in the next basic module as the input terminal to output. Or, when the control terminal of the data selector in the same basic module obtains a low level, the MUX1 and MUX2 in the basic module are turned on at the first input terminals, that is, the MUX in the basic module selects the delay information of the first input terminal In1 and the output terminal Out of the delay unit in the basic module to output, for example, in Figure 1 the first input terminal of the MUX1 is 0 and the second input terminal is 1, the first input terminal of the MUX2 is 0 and the second input terminal is 1. For example, when the control terminal ctrl[0] of the data selector in the basic module 1 obtains a high level, the MUX1 and MUX2 in the basic module 1 are turned on at the terminal 1. For example, when the control terminal ctrl[1] of the data selector in the basic module 2 obtains a low level, the MUX1 and MUX2 in the basic module 1 are turned on at the terminal 0.

[0045] In one embodiment, the method for controlling the on-off states of the data selectors according to the coarse adjustment configuration signal S1 obtained by the configuration terminal includes: converting the binary coarse adjustment configuration signal S1 obtained by the configuration terminal into a decimal number Q by using a conversion unit, and then providing the required high level or low level to the control terminal of the MUX in each basic module according to the decimal number Q, so as to extract the delay information of the corresponding number of delay units. When the delay information of Q delay units is required to be extracted: the high level is provided to the control terminal of the data selector in the first Q-1 basic modules, so that the MUX1 and MUX2 in the first Q-1 basic modules are turned on at the second input terminals; and the low level is provided to the control terminal of the data selector in the Qth basic module, so that the MUX1 and MUX2 in the Qth basic module are turned on at the first input terminals. Thus, the delay unit is used to process the clock input signal clk_in and output Va and Vb. For the basic modules after the Qth basic module, the high level or the low level can be provided to the control terminal of the data selector in the basic module, which has no effect on the output Va and Vb.

[0046] In one embodiment, please refer to Figure 3The fine adjustment module includes a data selector MUX3, a data selector MUX4 and a phase interpolation circuit, a first input terminal of the MUX3 is connected to the coarse adjustment module to obtain the first loopback output Va, the first loopback output Va generates a Va_0 output to a second input terminal of the MUX3 and a first input terminal of the MUX4 after passing through an inverter. The phase difference between the Va_0 and the first loopback output Va and the second loopback output Vb is equal. A second input terminal of the MUX4 is connected to the coarse adjustment module to obtain the second loopback output Vb. An output terminal of the MUX3 is connected to one input terminal of the phase interpolation circuit, an output terminal of the MUX4 is connected to another input terminal of the phase interpolation circuit, and an output terminal of the phase interpolation circuit outputs a clock output signal clk_out through an inverter. The control terminals of the MUX3 and the MUX4 are connected, when the control terminals of the MUX3 and the MUX4 obtain a high level, the MUX3 and the MUX4 simultaneously turn on the second input terminals (1 ends) of the MUX3 and the MUX4 respectively; when the control terminals of the MUX3 and the MUX4 obtain a low level, the MUX3 and the MUX4 simultaneously turn on the first input terminals (0 ends) of the MUX3 and the MUX4 respectively. Figure 3 Figure 3

[0047] The fine adjustment module provides a high level or a low level to the control terminals of the MUX3 and the MUX4 according to the fine adjustment configuration signal S2 obtained from the configuration end to control the turn-on state of the MUX3 and the MUX4, and the fine adjustment module also controls the working state of the phase interpolation circuit according to the fine adjustment configuration signal S2 obtained from the configuration end.

[0048] In one embodiment, the highest bit or the lowest bit of the fine adjustment configuration signal S2 can be directly provided to the control terminals of the MUX3 and the MUX4, and the phase interpolation circuit is controlled according to the fine adjustment configuration signal S2 of the remaining bits.

[0049] Please refer to Figure 3 When a low level is provided to the control terminals of the MUX3 and the MUX4, the MUX3 and the MUX4 are both selected to the 0 end, that is, the first input terminal, the MUX3 outputs the Va to the phase interpolation circuit, the MUX4 outputs the Va_0 to the phase interpolation circuit, and the phase interpolation circuit performs phase interpolation between the Va and the Va_0. When a high level is provided to the control terminals of the MUX3 and the MUX4, the MUX3 and the MUX4 are both selected to the 1 end, that is, the second input terminal, the MUX3 outputs the Va_0 to the phase interpolation circuit, the MUX4 outputs the Vb to the phase interpolation circuit, and the phase interpolation circuit performs phase interpolation between the Va and the Va_0.

[0050] The structure of the commonly used phase interpolation circuit is as follows Figure 3 ​​As shown, the phase interpolation circuit includes 2K branches which are identical, K is the length of phase interpolation, which determines the number of interpolated phases, each branch includes an inverter with a control terminal, the fine adjustment module provides high or low level to the control terminal S1-SK and G1-GK according to the fine adjustment configuration signal S2, to control the weight of the output signal of MUX3 and the output signal of MUX4, so as to determine whether the output clk_out is closer to the output signal of MUX3 or the output signal of MUX4. The specific adjustment mode of the phase interpolation circuit can refer to the existing working logic of the phase interpolation circuit, which is not described here.

[0051] As described above in this application, the configuration signal can be used to control the coarse adjustment module and the fine adjustment module, so as to output the clock output signal clk_out with the required delay time length relative to the clock input signal clk_in. In order to make the accuracy of the delay time length of the output clock output signal clk_out higher, in one embodiment, the delay chain circuit further includes a zero delay module and a calibration module, and a method for determining the configuration signal by using the zero delay module and the calibration module. Please refer to Figure 4 , the clock input signal clk_in provides clk_ref to the calibration module after passing through the zero delay module, and the clock output signal clk_out generated by the fine adjustment module is also provided to the calibration module, and the calibration module generates a calibration signal val_out according to the two input signals clk_ref and clk_out, which is used to indicate the delay time length between the clock output signal clk_out and the clock input signal clk_in. Then adjust the configuration signal of the delay chain circuit according to the calibration signal val_out until the clock output signal clk_out has the target delay time length relative to the clock input signal clk_in, that is, the configuration signal of the delay chain circuit can be generated, and then the configuration signal is provided to the coarse adjustment module and the fine adjustment module, so as to output the required clock output signal clk_out.

[0052] Among them, the clock signal clk_ref output by the zero delay module has a fixed delay relative to the clock input signal clk_in, which is fixed and cannot be selected. And when the configuration signal is all 0, all data selectors in the coarse adjustment module and the fine adjustment module select the first input terminal, the clock output signal clk_out generated by the fine adjustment module also has the fixed delay relative to the clock input signal clk_in. The zero delay module can be realized by using the existing common zero delay circuit.

[0053] In one embodiment, the calibration module comprises a first trigger unit, a second trigger unit and a phase detector, the clock signal clk_ref outputted by the zero delay module is connected to the first input terminal of the phase detector through the first trigger unit, the clock output signal clk_out generated by the fine adjustment module is connected to the second input terminal of the phase detector through the second trigger unit, and the output terminal of the phase detector is connected to the output terminal of the calibration module and used for outputting the calibration signal val_out. The output of the first trigger unit is switched from low level to high level at the rising edge of the (N+1)th clock cycle of the clock input signal clk_in, the output of the second trigger unit is switched from low level to high level at the rising edge of the first clock cycle of the clock output signal clk_out, and N is a parameter and the initial value is 1.

[0054] The phase detector outputs low level when the phase of the signal at the first input terminal is later than the phase of the signal at the second input terminal, and outputs high level when the phase of the signal at the first input terminal is not later than the phase of the signal at the second input terminal. Then the configuration signal is adjusted in turn from 0 until the calibration signal val_out outputted by the calibration module is switched from low level to high level, and the configuration signal that makes the clock output signal clk_out have the target delay time length of N clock cycles relative to the clock input signal clk_in is obtained.

[0055] In actual application, the clock output signal clk_out that needs to have a delay time length of one clock cycle relative to the clock input signal clk_in is commonly used. Then N=1, as shown in the following formula: Figure 5 The first trigger unit comprises a first DQ flip-flop U1 and a second DQ flip-flop U2, the clock signal clk_ref outputted by the zero delay module is connected to the clock terminal of the first DQ flip-flop U1 and the clock terminal of the second DQ flip-flop U2, the input terminal D of the first DQ flip-flop U1 obtains the enable signal EN of the calibration module, the output terminal Q of the first DQ flip-flop is connected to the input terminal D of the second DQ flip-flop U2 through two inverters connected in turn, and the output terminal Q of the second DQ flip-flop is connected to the first input terminal of the phase detector. Due to the rising edge trigger of the DQ flip-flop, the addition of two inverters after the output terminal Q of the first DQ flip-flop U1 makes the rising edge of the input terminal D of the second DQ flip-flop U2 later than the first rising edge of the clock input of the second DQ flip-flop U2, so that the signal outputted by the output terminal Q of the second DQ flip-flop has a delay time length of one clock cycle relative to the clock input signal.

[0056] The second trigger unit comprises a third DQ flip-flop U3, the clock output signal clk_out outputted by the fine adjustment module is connected to the clock terminal of the third DQ flip-flop U3, the input terminal D of the third DQ flip-flop U3 obtains the enable signal EN of the calibration module, and the output terminal Q of the third DQ flip-flop U3 is connected to the second input terminal of the phase detector.

[0057] When all bits of the configuration signal are 0, the clock output signal clk_out from the fine-tuning module is in phase with the clock signal clk_ref from the zero-delay module. Therefore, the output terminals A and C of the first DQ flip-flop U1 and the third DQ flip-flop U3 are also in phase. This causes the output terminal B of the second DQ flip-flop U2 to be later than the output terminal C, resulting in the calibration signal val_out from the phase detector being low. Since the enable signal EN of the calibration module and the clock signal clk_ref from the zero-delay module are fixed, the configuration signal is adjusted by incrementing the corresponding decimal value by one step to increase the delay of clk_out relative to clk_in. This gradually adjusts the phase of terminal C to become later and closer to the phase of terminal B, until the phase of terminal C is no later than the phase of terminal B. At this point, the calibration signal val_out switches from low to high. The phase of terminal C may be in phase with the phase of terminal B, or it may be slightly later than the phase of terminal B within the accuracy range. The configuration signal at this time is obtained. Using the obtained configuration signal to control the coarse adjustment module and the fine adjustment module, clk_out can have a delay of exactly one clock cycle relative to clk_in.

[0058] A commonly used configuration signal is the configuration signal S for the P bit.<P-1:0> The high M bit serves as the coarse adjustment configuration signal S1, and the low PM bit serves as the fine adjustment configuration signal S2. The coarse adjustment module includes 2... M Each basic module, controlled by a coarse adjustment configuration signal S1, generates two loopback outputs differing by one coarse adjustment delay unit. The coarse adjustment module can generate a total of 2... M The fine-tuning module can generate a total of 2 steps with delay. P-M With a delay step, the entire delay chain circuit can generate a total of 2 steps. P The delay information is evenly distributed.

[0059] For example, in one instance, suppose the configuration signal consists of 9 bits, where the high 5 bits are provided as coarse adjustment configuration signal S1 to the coarse adjustment module, and the low 4 bits are provided as fine adjustment configuration signal S2 to the fine adjustment module. The timing diagram when all configuration bits of the configuration signal are 0, resulting in a configuration signal of 000000000, is as follows. Figure 6 As shown in (a) above. The timing diagram for the operation when the configuration signal is increased sequentially to step 210, i.e., when the configuration signal becomes 011010010, is as follows. Figure 6 As shown in (b) above. By comparing (a) and (b), it can be seen that by increasing the configuration signal, the phase of clk_out is continuously delayed until the calibration signal val_out switches from low level to high level. Thus, the required configuration signal is 011010010, which is the configuration signal when the output is delayed by one clock cycle relative to the input.

[0060] The above merely preferred embodiments of the present application, the present application is not limited to the above examples. It is understood that the skilled in the art without departing from the spirit and concept of the present application directly derived or thought of other improvements and changes, should be considered to be included within the scope of the protection of the present application.

Claims

1. A delay chain circuit with configurable delay duration, characterized in that, The delay chain circuit includes a coarse adjustment module and a fine adjustment module. The coarse adjustment module includes M-stage cascaded delay units and several data selectors. The data selectors are connected to form a loop structure. The input terminal of the first-stage delay unit obtains the clock input signal, and the two output terminals of the loop structure formed by the data selectors are connected to the fine adjustment module. The coarse adjustment module controls the conduction state of each data selector according to the coarse adjustment configuration signal obtained from the configuration terminal, and generates a first loopback output Va and a second loopback output Vb corresponding to the coarse adjustment configuration signal and outputs them to the fine adjustment module. The phase difference between the first loopback output Va and the second loopback output Vb is the delay duration generated by a delay unit. The fine-tuning module performs phase interpolation between the first loopback output Va and the second loopback output Vb based on the fine-tuning configuration signal obtained from the configuration terminal, generating a clock output signal with a delay duration corresponding to the configuration signal relative to the clock input signal. The configuration signal includes a coarse-tuning configuration signal provided to the coarse-tuning module and a fine-tuning configuration signal provided to the fine-tuning module.

2. The delay chain circuit according to claim 1, characterized in that, The coarse adjustment module includes M levels of cascaded basic modules. Each basic module includes a delay unit and several data selectors. The delay units in the M basic modules are connected in sequence to form a cascaded structure, and the data selectors in the M basic modules are connected in sequence to form a loop structure. The control terminals of multiple data selectors in the same basic module are connected. The first input terminal of the delay unit in the first-level basic module obtains the clock input signal, and the second input terminal of the delay unit in the first-level basic module is connected to a high level. The first input terminal of the delay unit in each of the other basic modules is connected to the output terminal of the delay unit in the previous level basic module, and the second input terminal is connected to the control terminal of the data selector in the previous level basic module.

3. The delay chain circuit according to claim 2, characterized in that, Each basic module includes data selector MUX1 and data selector MUX2. The loop structure formed by the data selectors in each basic module includes: The first input terminal of MUX1 in each basic module is connected to the output terminal of the delay unit in the same basic module, and the second input terminal of MUX1 is connected to the output terminal of MUX1 in the next basic module. The output terminal of MUX1 in the first basic module is connected to the fine-tuning module to output the second loopback output Vb. The second input terminal of MUX1 in the last basic module is connected to a high level. The first input terminal of MUX2 in each basic module is connected to the first input terminal of the delay unit in the same basic module; the second input terminal of MUX2 is connected to the output terminal of MUX2 in the next basic module; the output terminal of MUX2 in the first basic module is connected to the fine-tuning module to output the first loopback output Va; the second input terminal of MUX2 in the last basic module is connected to a high level. When the control terminal of the data selector in the same basic module receives a high level, MUX1 and MUX2 simultaneously turn on their respective second input terminals; or, when the control terminal of the data selector in the same basic module receives a low level, MUX1 and MUX2 simultaneously turn on their respective first input terminals.

4. The delay chain circuit according to claim 3, characterized in that, The method by which the coarse adjustment module controls the conduction state of each data selector based on the coarse adjustment configuration signal obtained from the configuration terminal includes: The conversion unit converts the binary coarse adjustment configuration signal obtained through the configuration terminal into a decimal value Q; a high level is provided to the control terminal of the data selector in the first Q-1 stage basic module, so that MUX1 and MUX2 in the first Q-1 stage basic module simultaneously turn on the second input terminal, and a low level is provided to the control terminal of the data selector in the Q stage basic module, so that MUX1 and MUX2 in the Q stage basic module simultaneously turn on the first input terminal.

5. The delay chain circuit according to claim 2, characterized in that, In each delay unit, the first input of the first NAND gate is connected to the second input of the delay unit, the second input of the first NAND gate is connected to the first input of the delay unit, the output of the first NAND gate is connected to the second input of the second NAND gate, the first input of the second NAND gate is connected to the second input of the delay unit, and the output of the second NAND gate is connected to an inverter and then to the output of the delay unit.

6. The delay chain circuit according to claim 1, characterized in that, The fine-tuning module includes a data selector MUX3, a data selector MUX4, and a phase interpolation circuit. The first input of MUX3 is connected to the coarse-tuning module to obtain the first loopback output Va. The first loopback output Va is inverted to generate Va_0, which is output to the second input of MUX3 and the first input of MUX4. The second input of MUX4 is connected to the coarse-tuning module to obtain the second loopback output Vb. The output of MUX3 is connected to one input of the phase interpolation circuit, and the output of MUX4 is connected to the other input of the phase interpolation circuit. The output of the phase interpolation circuit outputs the clock output signal through an inverter. Wherein, Va_0 has the same phase difference with the first loopback output Va and the second loopback output Vb. The control terminals of MUX3 and MUX4 are connected so that their respective first input terminals or their respective second input terminals are turned on at the same time. The fine-tuning module controls the conduction state of MUX3 and MUX4 and the working state of the phase interpolation circuit according to the fine-tuning configuration signal obtained by the configuration terminal.

7. The delay chain circuit according to claim 1, characterized in that, The delay chain circuit also includes a zero-delay module and a calibration module. The clock input signal is provided to the calibration module through the zero-delay module, and the clock output signal generated by the fine-tuning module is also provided to the calibration module. The calibration module generates a calibration signal based on the input signal. The calibration signal is used to indicate the delay duration between the clock output signal and the clock input signal. The method for generating the configuration signal of the delay chain circuit includes: adjusting the configuration signal of the delay chain circuit according to the calibration signal until the clock output signal has a target delay duration relative to the clock input signal.

8. The delay chain circuit according to claim 7, characterized in that, The calibration module includes a first trigger unit, a second trigger unit, and a phase detector. The clock signal output by the zero-delay module is connected to the first input terminal of the phase detector via the first trigger unit. The clock output signal is connected to the second input terminal of the phase detector via the second trigger unit. The output terminal of the phase detector is connected to the output terminal of the calibration module and is used to output the calibration signal. The output of the first trigger unit switches from low to high at the rising edge of the (N+1)th clock cycle of the clock input signal, and the output of the second trigger unit switches from low to high at the rising edge of the first clock cycle of the clock output signal. N is a parameter with an initial value of 1.

9. The delay chain circuit according to claim 8, characterized in that, The method for generating the configuration signal for the delay chain circuit includes: The configuration signals are adjusted sequentially until the calibration signal output by the calibration module switches from low level to high level, thereby obtaining a configuration signal that makes the clock output signal have a target delay of N clock cycles relative to the clock input signal; Specifically, the phase detector outputs a low level when the phase of the signal at the first input terminal is later than the phase of the signal at the second input terminal, and outputs a high level when the phase of the signal at the first input terminal is not later than the phase of the signal at the second input terminal.

10. The delay chain circuit according to claim 8, characterized in that, N=1, the first triggering unit includes a first DQ flip-flop and a second DQ flip-flop, the clock signal output by the zero-delay module is connected to the clock terminals of the first DQ flip-flop and the second DQ flip-flop, the input terminal D of the first DQ flip-flop receives the enable signal of the calibration module, the output terminal Q of the first DQ flip-flop is connected to the input terminal D of the second DQ flip-flop through two inverters connected in sequence, and the output terminal Q of the second DQ flip-flop is connected to the first input terminal of the phase detector; the signal output by the output terminal Q of the second DQ flip-flop has a delay of one clock cycle relative to the clock input signal. The second triggering unit includes a third DQ flip-flop. The clock output signal is connected to the clock terminal of the third DQ flip-flop. The input terminal D of the third DQ flip-flop acquires the enable signal of the calibration module. The output terminal Q of the third DQ flip-flop is connected to the second input terminal of the phase detector.

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