Analog-digital conversion circuit and chip, driving device, electrical equipment and vehicle and device

Abstract

The application discloses an analog-digital conversion circuit and chip, a motor driving device, an electrical equipment, and a vehicle and equipment, wherein the analog-digital conversion circuit comprises an analog signal sampling module, a clock signal generating module and a flip-flop, the analog signal sampling module is used for acquiring an analog signal and generating an analog sampling signal; the clock signal generating module is used for generating a clock signal; a first input end of the flip-flop is connected with an output end of the analog signal sampling module, a second input end of the flip-flop is connected with an output end of the clock signal generating module, and an output end of the flip-flop is connected with a switch control end of the analog signal sampling module; the flip-flop is used for controlling a duty cycle of an output signal according to the clock signal and the analog sampling signal to generate a digital pulse signal. The analog-digital conversion circuit of the embodiment has a wider collection range for the analog signal, and the circuit has a wide application range. The motor driving device, the electrical equipment, the vehicle and the equipment have more stable performances.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and more particularly to an analog-to-digital converter circuit, as well as chips, motor drives, electrical equipment, vehicles, and devices including the analog-to-digital converter circuit. Background Technology

[0002] In harsh working environments with high requirements for safety and reliability, it is often necessary to sample the chip's operating temperature and feed it back to the controller for processing. The controller can monitor the ambient temperature in real time and provide timely protection under overheating conditions. One method for sampling the chip's operating temperature is to connect an external NTC (Negative Temperature Coefficient) device to the chip. Specifically, the chip provides a fixed current source to power the NTC device to generate an analog voltage level. The absolute value of this analog voltage level changes with temperature using a certain temperature coefficient. Internally, the chip needs to convert the analog voltage level into a signal that the controller can recognize, such as a duty cycle signal, to achieve real-time temperature sampling and feedback. When the ambient temperature changes, the voltage drop across the NTC device also changes, and the corresponding duty cycle signal inside the chip will change accordingly. When using an analog-to-digital converter circuit to acquire the operating temperature of a chip, the chip typically provides a constant current source and a constant reference voltage. The analog level signal acquisition branch and the duty cycle signal generation branch are coupled and share common parts to convert the sampled analog level signal into a duty cycle signal.

[0003] However, using the aforementioned analog-to-digital converter circuit requires ensuring that the provided constant reference voltage is greater than the acquired analog level signal. Therefore, to guarantee a sufficiently large sampling range for the analog level signal, the constant reference voltage also needs to be sufficiently high. Furthermore, if a larger duty cycle is required for the given analog level signal, a correspondingly higher constant reference voltage is needed. However, in practical applications, the required constant reference voltage may exceed the power supply voltage, and the constant reference voltage also has relatively high requirements regarding temperature characteristics. Therefore, the aforementioned analog-to-digital converter circuit has a limited sampling range for analog signals, high hardware requirements, and a narrow range of applications. Summary of the Invention

[0004] The present invention aims to at least solve one of the technical problems existing in the prior art. To this end, one of the objectives of the present invention is to provide an analog-to-digital converter circuit that has a wider sampling range for analog signals, lower hardware requirements, and a wider range of applications.

[0005] The second objective of this invention is to propose a chip.

[0006] The third objective of this invention is to provide a motor drive device.

[0007] The fourth objective of this invention is to provide an electrical device.

[0008] The fifth objective of this invention is to provide a vehicle.

[0009] The sixth objective of this invention is to provide a device.

[0010] To achieve the above objectives, the analog-to-digital conversion circuit proposed in the first aspect of the present invention includes: an analog signal sampling module for acquiring an analog signal and generating an analog sampling signal; a clock signal generation module for generating a clock signal; and a trigger, wherein a first input terminal of the trigger is connected to the output terminal of the analog signal sampling module, a second input terminal of the trigger is connected to the output terminal of the clock signal generation module, and the output terminal of the trigger is connected to the switch control terminal of the analog signal sampling module. The trigger is used to control the duty cycle of the output signal according to the clock signal and the analog sampling signal to generate a digital pulse signal.

[0011] The analog-to-digital converter circuit proposed in this embodiment of the invention is based on an architecture of an analog signal sampling module, a clock signal generation module, and a flip-flop. The clock signal generation module generates a clock signal corresponding to the working cycle of the desired digital pulse signal. This clock signal generation module is set independently of the analog signal sampling module. Therefore, the component specifications and circuit layout of the analog signal sampling module and the clock signal generation module can be independently adjusted according to design requirements, reducing hardware requirements and enabling a wider sampling range for the analog signal. This also increases the adjustable range of the duty cycle of the output digital pulse signal. Therefore, this analog-to-digital converter circuit has a wider range of applications.

[0012] In some embodiments of the present invention, the clock signal generation module includes: a first current source; a first capacitor, a first terminal of which is connected to the first current source, and a second terminal of which is grounded; a first comparator, a first input terminal of which is connected to the first terminal of the first capacitor, a second input terminal of which is used to input a reference voltage, and an output terminal of which is connected to the second input terminal of the flip-flop, for generating the clock signal according to the voltage of the first capacitor and the reference voltage; and a first switch, a first terminal of which is connected to the first current source and the first terminal of the first capacitor, a second terminal of which is grounded, and a switching control terminal of which is connected to the output terminal of the first comparator, for turning on or off according to the clock signal to control the voltage of the first capacitor.

[0013] In some embodiments of the present invention, the clock signal generation module further includes: a frequency divider, the input terminal of which is connected to the output terminal of the first comparator, for dividing the clock signal to obtain a frequency-divided signal; and a narrow pulse generation circuit unit, the input terminal of which is connected to the output terminal of the frequency divider, and the output terminal of which is connected to the second input terminal of the flip-flop, for generating a narrow pulse signal based on the frequency-divided signal as the final clock signal.

[0014] In some embodiments of the present invention, the narrow pulse generation circuit unit is a leading edge blanking circuit, which is used to perform leading edge blanking processing on the frequency division signal to generate the narrow pulse signal.

[0015] In some embodiments of the present invention, the analog signal sampling module includes: a second current source; a second capacitor, the first terminal of which is connected to the second current source and the second terminal of which is grounded; a second switch, the first terminal of which is connected to the first terminal of the second capacitor and the second terminal of which is grounded, the switching control terminal of which is connected to the output terminal of the flip-flop, for controlling the voltage of the second capacitor by turning it on or off according to the output signal of the flip-flop; and a second comparator, the first input terminal of which is connected to the first terminal of the second capacitor, the second input terminal of which is used to receive an analog signal, and the output terminal of which is connected to the first input terminal of the flip-flop, for generating the analog sampling signal according to the voltage of the second capacitor and the analog signal.

[0016] In some embodiments of the present invention, the reference voltage is set according to the capacitance ratio of the first capacitor and the second capacitor and the current ratio of the second current source and the first current source, wherein the reference voltage is inversely proportional to the capacitance ratio or the current ratio.

[0017] In some embodiments of the present invention, the first current source and the second current source are configured by a common source cascode current mirror according to a preset current ratio to improve the duty cycle accuracy of the output digital pulse signal.

[0018] In some embodiments of the present invention, the capacitance values ​​of the first capacitor and the second capacitor are set in equal proportions to improve the duty cycle accuracy of the output digital pulse signal.

[0019] To achieve the above objectives, the chip proposed in the second aspect of the present invention includes the analog-to-digital conversion circuit described in any of the preceding claims.

[0020] According to the chip proposed in the embodiments of the present invention, the analog-to-digital conversion circuit of any of the above embodiments is used. The analog-to-digital conversion circuit generates a clock signal for the required digital pulse signal working cycle by setting a clock signal generation module. The clock signal generation module is set independently of the analog signal sampling module. Therefore, the component specifications or circuit layout of the analog signal sampling module and the clock signal generation module can be independently adjusted according to design requirements, which reduces the hardware level requirements and makes the sampling range of analog signals wider. It can also increase the adjustable range of the duty cycle of the output digital pulse signal and has a wider range of applications.

[0021] Furthermore, by using the analog-to-digital conversion circuit of the above embodiment, the capacitance value matching setting and the current source synchronization setting can improve the duty cycle accuracy of the output digital pulse signal and enable accurate detection of analog signals.

[0022] To achieve the above objectives, the motor drive device of the third aspect of the present invention includes the analog-to-digital conversion circuit and the drive circuit of the above embodiment, wherein the analog-to-digital conversion circuit and the drive circuit are connected.

[0023] According to the motor drive device of the present invention, by using the analog-to-digital conversion circuit of the above embodiment, a wider sampling range of analog signals can be obtained, and the signal detection is more accurate. Therefore, the device is applicable to more diverse environments and has more stable performance.

[0024] To achieve the above objectives, the electrical device of the fourth aspect of the present invention includes the chip and power module of the above embodiment, wherein the chip and the power module are connected.

[0025] According to the electrical equipment of the present invention, the chip of the above embodiment is used. The analog-to-digital conversion circuit of the chip can make the sampling range of analog signals wider and increase the adjustable range of the duty cycle of the output digital pulse signal, thus making it more widely applicable. Therefore, the electrical equipment is applicable to more diverse environments and has more stable performance.

[0026] To achieve the above objectives, the vehicle according to the fifth aspect of the present invention includes at least one electrical device from the above embodiments. For example, the electrical device may include a motor drive unit, an on-board charger, a high-voltage heating device, etc. The chip of the electrical device uses the analog-to-digital conversion circuit of the above embodiments, which can obtain data with a wider sampling range and has a wider range of applications. Therefore, the vehicle's performance, such as motor drive, charging, and high-voltage heating, is more stable.

[0027] To achieve the above objectives, the device proposed in the sixth aspect embodiment of the present invention includes: the chip described in the second aspect embodiment above, used to convert analog signals into digital pulse signals; and a controller connected to the chip, used to receive the digital pulse signals and generate control commands based on the digital pulse signals.

[0028] The device proposed according to the embodiments of the present invention uses the chip of the above embodiments. The chip includes the analog-to-digital conversion circuit of any of the above embodiments. The analog-to-digital conversion circuit has a wide range of applications and can meet the different chip requirements of the device, making the device work more stably.

[0029] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0030] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0031] Figure 1 A block diagram of an analog-to-digital converter circuit according to an embodiment of the present invention;

[0032] Figure 2 This is a schematic diagram of an analog-to-digital converter circuit according to an embodiment of the present invention;

[0033] Figure 3 This is a signal waveform diagram in an analog-to-digital converter circuit according to an embodiment of the present invention;

[0034] Figure 4 This is a schematic diagram of a clock signal generation module according to an embodiment of the present invention;

[0035] Figure 5 This is a schematic diagram of an analog-to-digital converter circuit according to another embodiment of the present invention;

[0036] Figure 6 This is a signal waveform diagram in an analog-to-digital converter circuit according to another embodiment of the present invention;

[0037] Figure 7 A block diagram of a chip according to an embodiment of the present invention;

[0038] Figure 8 This is a block diagram of a motor drive device according to an embodiment of the present invention;

[0039] Figure 9 This is a block diagram of an electrical device according to an embodiment of the present invention;

[0040] Figure 10 A block diagram of a vehicle according to an embodiment of the present invention;

[0041] Figure 11 This is a block diagram of a device according to an embodiment of the present invention.

[0042] Figure label:

[0043] Equipment 1000, vehicles 2000;

[0044] Chip 100, controller 200, motor drive device 300, electrical equipment 400;

[0045] Analog-to-digital converter circuit 10, drive circuit 20;

[0046] Analog signal sampling module 1, clock signal generation module 2, trigger 3, power module 401;

[0047] Frequency divider 21, narrow pulse generation circuit unit 22, first current source I1, first capacitor C1, first comparator P1 and first switch NM1, second current source I2, second capacitor C2, second switch NM2, second comparator P2, common source cascode current mirror L;

[0048] Voltage VC1, voltage VC2, reference voltage V1, analog signal VIN, analog sampling signal CT2, clock signal CT1, duty cycle D of digital pulse signal, output signal CT3, frequency divider signal CT4. Detailed Implementation

[0049] To provide a more detailed understanding of the features and technical content of the embodiments of the present invention, the implementation of the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of the present invention. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be simplified in their depiction to simplify the drawings.

[0050] The following is for reference. Figures 1-6 An analog-to-digital converter circuit 10 according to an embodiment of the present invention is described.

[0051] In some embodiments of the present invention, such as Figure 1 The diagram shown is a block diagram of an analog-to-digital converter circuit according to an embodiment of the present invention, wherein the analog-to-digital converter circuit 10 includes an analog signal sampling module 1, a clock signal generation module 2, and a flip-flop 3.

[0052] The analog signal sampling module 1 is used to acquire analog signals and generate analog sampled signals. In this embodiment, the analog signal can be ambient temperature, ambient humidity, or other electrical signals converted from acquired signals, etc., and no specific limitations are imposed here.

[0053] The clock signal generation module 2 is used to generate a clock signal. The clock signal can be a signal used to control the working cycle of the digital pulse signal output by the analog-to-digital converter circuit 10; in some embodiments, the clock signal is a narrow pulse signal.

[0054] The first input terminal of flip-flop 3 is connected to the output terminal of analog signal sampling module 1, the second input terminal of flip-flop 3 is connected to the output terminal of clock signal generation module 2, and the output terminal of flip-flop 3 is connected to the switch control terminal of analog signal sampling module 1. The circuit of flip-flop 3 can be composed of logic gates, and flip-flop 3 can handle the mutual influence between input signal, output signal, and clock frequency. In an embodiment of the present invention, flip-flop 3 is used to control the duty cycle of the output signal according to the clock signal and the analog sampling signal to generate a digital pulse signal. In an embodiment, flip-flop 3 can be an RS flip-flop, with analog signal sampling module 1 connected to the S terminal of RS flip-flop and clock signal generation module 2 connected to the R terminal of RS flip-flop.

[0055] Specifically, in the initial state, the output of flip-flop 3 is 0. When both the analog sampling signal and the clock signal are 0, the output of flip-flop 3 remains 0. Once the analog sampling signal becomes 1, the output of flip-flop 3 will flip to 1 and be fed back to the switch control terminal of the analog signal sampling module 1, triggering the analog sampling signal output by the analog signal sampling module 1 to flip to 0. However, since the second input terminal of flip-flop 3 is also 0, the output of flip-flop 3 will remain 1 until the clock signal generation module 2 outputs a clock signal, i.e., the clock signal flips to 1. At this point, flip-flop 3 is reset, and its output flips to 0, thus outputting a digital pulse signal. This cycle repeats, thereby converting the acquired analog signal into a corresponding digital pulse signal.

[0056] The analog-to-digital converter circuit 10 proposed in this embodiment of the invention is based on an architecture of an analog signal sampling module 1, a clock signal generation module 2, and a flip-flop 3. The clock signal generation module 2 is configured to generate a clock signal for the required digital pulse signal working cycle, and this clock signal generation module 2 is set independently of the analog signal sampling module 1. Therefore, the component specifications and circuit layout of the analog signal sampling module 1 and the clock signal generation module 2 can be independently adjusted according to design requirements, reducing the hardware requirements and allowing for a wider sampling range for the analog signal. This also increases the adjustable range of the duty cycle of the output digital pulse signal. Therefore, the analog-to-digital converter circuit 10 has a wider range of applications.

[0057] Specifically, it can be combined with Figure 2 and Figure 3 The analog signal sampling module 1 of this embodiment is described.

[0058] In some embodiments, such as Figure 2The diagram shown is a schematic of an analog-to-digital conversion circuit according to an embodiment of the present invention. The analog signal sampling module 1 includes a second current source I2, a second capacitor C2, a second switch NM2, and a second comparator P2. The second switch NM2 may be an NMOS (N-Metal-Oxide-Semiconductor) transistor.

[0059] In this configuration, the first terminal of the second capacitor C2 is connected to the second current source I2, and the second terminal of the second capacitor C2 is grounded. The first terminal of the second switch NM2 is connected to the first terminal of the second capacitor C2, and the second terminal of the second switch NM2 is grounded. The switching control terminal of the second switch NM2 is connected to the output terminal of the trigger 3, and is used to control the voltage of the second capacitor C2 by turning it on or off according to the output signal of the trigger 3, i.e., the digital pulse signal.

[0060] The first input terminal of the second comparator P2 is connected to the first terminal of the second capacitor C2. The second input terminal of the second comparator P2 is used to receive the analog signal. The output terminal of the second comparator P2 is connected to the first input terminal of the flip-flop 3 and is used to generate an analog sampling signal based on the voltage of the second capacitor C2 and the analog signal.

[0061] Here, the analog signal is denoted as VIN, the voltage across the second capacitor C2 is denoted as voltage VC2, and the analog sampled signal is denoted as CT2. The analog signal VIN is the given signal.

[0062] Specifically, such as Figure 3 The diagram shown is a signal waveform diagram in an analog-to-digital converter circuit according to an embodiment of the present invention, where the D waveform represents the output signal of the flip-flop 3, i.e., the digital pulse signal. In the initial state, no charge accumulates on the second capacitor C2, i.e., the voltage VC2 of the second capacitor C2 is equal to 0, the second switch NM2 is off, and the second current source I2 charges the second capacitor C2. At this time, the voltage VC2 of the second capacitor C2 gradually increases. The voltage VC2 is compared with the analog signal VIN. When the voltage VC2 is less than the analog signal VIN, the signal output by the second comparator P2 is 0. When the voltage VC2 is greater than or equal to the analog signal VIN, the second comparator P2 outputs a pulse signal, i.e., the analog sampling signal CT2, which is input to the flip-flop 3.

[0063] Furthermore, when the second comparator P2 outputs the analog sampling signal CT2, the output of flip-flop 3 is high. At this time, the second switch NM2 receives the high level output from the flip-flop and turns on. The second current source I2 no longer charges the second capacitor C2, and the voltage VC2 of the second capacitor C2 quickly drops to 0 and remains there. When the output of flip-flop 3 is low, the second switch NM2 turns off, and the second current source I2 charges the second capacitor C2 again, thus repeating the above signal change pattern. In other words, flip-flop 3 outputs a high level according to the analog sampling signal CT2 output by the second comparator P2, and the low level output from the output of flip-flop 3 can reversely adjust the voltage VC2 of the second capacitor C2, causing the voltage VC2 to quickly drop to 0.

[0064] Furthermore, the time required for the second capacitor C2 to be charged from the second current source I2 until the voltage VC2 equals the analog signal VIN is... .

[0065] The analog signal acquisition module 1 of this embodiment of the invention has been described above. The following description refers to the appendix. Figure 2-4 The clock signal generation module 2 according to an embodiment of the present invention is described.

[0066] In some embodiments, the clock signal generation module 2 is used to generate a clock signal CT1. For example... Figure 4 The diagram shown is a schematic of a clock signal generation module according to an embodiment of the present invention. The clock signal generation module 2 includes a first current source I1, a first capacitor C1, a first comparator P1, and a first switching transistor NM1. The first switching transistor NM1 may be an NMOS transistor.

[0067] Specifically, the first terminal of the first capacitor C1 is connected to the first current source I1, and the second terminal of the first capacitor I1 is grounded. The first input terminal of the first comparator P1 is connected to the first terminal of the first capacitor C1, the second input terminal of the first comparator P1 is used to input a reference voltage, and the output terminal of the first comparator P1 is connected to the second input terminal of the flip-flop 3, used to generate a clock signal based on the voltage of the first capacitor C1 and the reference voltage. Here, the reference voltage is represented by V1, the voltage of the first capacitor C1 by VC1, and the clock signal by CT1.

[0068] The first terminal of the first switching transistor NM1 is connected to the first current source I1 and the first terminal of the first capacitor C1. The second terminal of the first switching transistor NM1 is grounded. The switching control terminal of the first switching transistor NM1 is connected to the output terminal of the first comparator P1, and is used to control the voltage VC1 of the first capacitor C1 by turning it on or off according to the clock signal CT1.

[0069] Specifically, the principle of clock signal generation module 2 is similar to that of analog signal sampling module 1. For example... Figure 3As shown, in the initial state, there is no charge accumulated on the first capacitor C1, that is, the voltage VC1 of the first capacitor C1 is equal to 0, the first switch NM1 is in the off state, and the first current source I1 charges the first capacitor C1. At this time, the voltage VC1 of the first capacitor C1 gradually increases. When the voltage VC1 is compared with the reference voltage V1, the voltage VC2 is less than the reference voltage V1, and the signal output by the first comparator P1 is 0. When the voltage VC1 is greater than or equal to the reference voltage V1, the level signal output by the first comparator P1 changes from "0" to "1". When the switching control terminal of the first switch NM1 detects that the signal output by the first comparator P1 is high, that is, when the first comparator P1 outputs a clock signal CT1, the first switch NM1 is turned on, the first current source I1 stops charging the first capacitor C1, and the voltage VC1 of the first capacitor C1 is quickly pulled down to 0. Since the clock signal CT1 output by the first comparator P1 is a pulse signal, its level will rapidly flip from "1" to "0". At this time, the switching control terminal of the first switch NM1 detects that the signal output by the first comparator P1 has become low, and the first switch NM1 turns off again. Consequently, the first current source I1 charges the first capacitor C1 again, repeating the above signal change pattern. Let the output period of the clock signal CT1 be T0. To reduce the error of the duty cycle D, the clock signal generation module 2 outputs a clock signal CT1 with a duration as narrow as possible in each cycle, so that it can be ignored compared to the overall cycle.

[0070] Taking flip-flop 3 as an RS flip-flop as an example, the S terminal of the RS flip-flop is connected to the output terminal of the analog signal sampling module 1, the R terminal of the RS flip-flop is connected to the output terminal of the clock signal generation module 2, and the output terminal of the RS flip-flop is connected to the control terminal of the second switching transistor NM2 in the analog signal sampling module 1.

[0071] Specifically, such as Figure 3 As shown, based on the signal change pattern in the clock signal generation module 2 and the signal change pattern in the analog signal sampling module 1, it can be seen that when the analog signal sampling module 1 outputs a pulse signal, i.e., the analog sampling signal CT2, the output signal of the trigger 3 changes from low level to high level. When the clock signal generation module 2 outputs the clock signal CT1, the output signal of the trigger 3 changes from high level to low level. This continues until the analog signal sampling module 1 outputs the analog sampling signal CT2 again, at which point the output signal of the trigger 3 changes from low level to high level again. This cycle repeats, thus converting the acquired analog signal into the corresponding digital pulse signal.

[0072] In some embodiments, according to the formula in the above embodiments Taking the clock signal CT1 with an output period of T0 as an example, the duty cycle D of the corresponding output digital pulse signal can be obtained as follows: .

[0073] Furthermore, according to the formula and formula available:

[0074] ;

[0075] Therefore, the reference voltage V1 is obtained as follows: .

[0076] As shown in the formula above, the reference voltage V1 is inversely proportional to the capacitance ratio or current ratio. The larger the values ​​of C1 / C2 and I2 / I1, the lower the corresponding reference voltage V1. The reference voltage V1 is set based on the capacitance ratio of the first capacitor C1 to the second capacitor C2 and the current ratio of the first current source I1 to the second current source I2, thus avoiding the influence of the temperature characteristics of the capacitors or current sources on the output signal. By sampling a reference V1 with good temperature characteristics, the other given parameters in the relationship between the duty cycle of the output digital pulse signal and the input analog signal VIN have good temperature characteristics, thereby ensuring that the duty cycle of the output digital pulse signal is relatively stable compared to the input analog signal. The bandgap reference is typically 1.2V. When using a bandgap reference for output, it is necessary to ensure that the first capacitor C1 and the second capacitor C2 are matched, and that the first current source I1 and the second current source I2 are matched, to improve the duty cycle accuracy of the output digital pulse signal.

[0077] In other embodiments, if the value of the analog signal VIN is a given value, and the duty cycle D of the output digital pulse signal is fixed, it is necessary to ensure precise matching of the first capacitor C1 and the second capacitor C2, as well as precise matching of the first current source I1 and the second current source I2. In some embodiments, this can be achieved through circuit and layout design to improve the accuracy of the duty cycle D of the output digital pulse signal. For example, the two current sources can be configured to be mirrored by a common-source cascode current mirror L. Specifically, as... Figure 2 As shown, the first current source I1 and the second current source I2 are configured to share a common current source according to a preset current ratio using a common-source cascode current mirror L. Furthermore, the capacitance values ​​of the first capacitor C1 and the second capacitor C2 can be set proportionally and precisely matched through layout to improve the accuracy of the duty cycle of the output digital pulse signal and enhance the accuracy of analog signal detection.

[0078] The analog-to-digital converter circuit 10 proposed in this embodiment of the invention is based on an architecture of an analog signal sampling module 1, a clock signal generation module 2, and a flip-flop 3. The clock signal generation module 2 is set independently of the analog signal sampling module 1 and can be adjusted according to design requirements. This enables adjustment of the duty cycle D of the output digital pulse signal, and has a wide range of applications. Furthermore, the first current source I1 and the second current source I2 are generated by mirroring through a common-source cascode current mirror L. By configuring the common current source according to a preset current ratio and configuring the capacitance values ​​of the first capacitor C1 and the second capacitor C2 proportionally, the accuracy of the duty cycle D of the output digital pulse signal is improved.

[0079] In some applications, there are requirements for the output frequency of the duty cycle D of the digital pulse signal output by the analog-to-digital converter circuit 10. When a lower duty cycle D is required, the absolute value of the period T0 of the corresponding output clock signal CT1 must be larger. This can be achieved by increasing the value of the first capacitor C1, but if the value of the first capacitor C1 is too large, it will significantly increase the production cost. Alternatively, it can be achieved by decreasing the value of the first current source I1, but if the required value of the first current source I1 is too small, it will be difficult to achieve high precision in I2 / I1. Therefore, in the embodiments of the present invention, the first current source I1 and the second current source I2 are precisely matched.

[0080] In other embodiments of the present invention, considering application scenarios where the absolute value of the period T0 of the output clock signal CT1 is required to be relatively large, the clock signal generation module 2 further includes a frequency divider 21 and a narrow pulse generation circuit unit 22. Specifically, it can be combined with... Figure 5 and Figure 6 The frequency divider 21 and the narrow pulse generation circuit unit 22 of the present invention are described in an embodiment of the present invention.

[0081] like Figure 5 The diagram shown is a schematic of an analog-to-digital converter circuit according to another embodiment of the present invention. The input terminal of the frequency divider 21 is connected to the output terminal of the first comparator P1, and is used to divide the output signal of the first comparator P1 (i.e., the clock signal) to obtain a divided frequency signal. The output signal of the first comparator P1 is represented by CT3, and the divided frequency signal is represented by CT4. The output signal CT3 of the first comparator P1 is a pulse signal.

[0082] The frequency divider 21 can reduce the output period T0 of the clock signal CT1 by a factor of two, thereby reducing the required capacitance value of the first capacitor C1 or increasing the required value of the first current source I1, thus reducing the hardware requirements.

[0083] like Figure 6The diagram shows a signal waveform in an analog-to-digital converter circuit according to another embodiment of the present invention. Taking a frequency divider 21 as an example of a 2-way divider, the signal frequency is reduced to half of the original signal frequency. Specifically, in the initial state, when the first current source I1 charges the first capacitor C1, the voltage VC1 gradually increases. If the charging time from the start of charging to when the voltage VC1 rises to a level greater than or equal to the reference voltage V1 is short, the frequency of the output signal CT3 of the first comparator P1 will be higher. With the added 2-way divider 21, in the initial state, when the first current source I1 charges the first capacitor C1 and the voltage VC1 is greater than or equal to the reference voltage V1, the first comparator P1 outputs a pulse signal, i.e., the output signal CT3. After receiving the output signal CT3, the frequency divider 21 outputs a high-level divided signal CT4 and maintains it. When the frequency divider 21 receives the output signal CT3 again, the output divided signal CT4 changes from high to low. In other words, every time the frequency divider 21 receives a pulse signal, the electrical average of the output frequency divider signal CT4 will change, thereby reducing the frequency of the frequency divider signal CT4 to half the frequency of the output signal CT3.

[0084] The input terminal of the narrow pulse generation circuit unit 22 is connected to the output terminal of the frequency divider 21, and the output terminal of the narrow pulse generation circuit unit 22 is connected to the second input terminal of the flip-flop 3. It is used to generate a narrow pulse signal based on the frequency division signal CT4 as the final clock signal CT1. Through the frequency divider 21 and the narrow pulse generation circuit unit 22, the clock signal output period can be adjusted, that is, the duty cycle of the output digital pulse signal can be adjusted.

[0085] In some embodiments, the narrow pulse generation circuit unit 22 can be implemented using a leading-edge blanking circuit. The leading-edge blanking circuit is used to perform leading-edge blanking processing on the frequency division signal to generate the narrow pulse signal. Specifically, the leading-edge blanking circuit can be implemented using an RC circuit or other circuits with leading-edge blanking function composed of comparators, switching transistors, or delay circuits. At the instant of a pulse edge input, for example... Figure 6 When the falling edge of the frequency divider signal CT4 is input to the leading edge blanking circuit, the leading edge blanking circuit outputs a set narrow pulse signal CT1 as the clock signal for the final output to flip-flop 3, which can adjust the duty cycle of the output digital pulse signal.

[0086] In this embodiment, the narrow pulse generation circuit unit 22 generates a narrow pulse signal as the clock signal CT1 each time it detects the frequency division signal CT4 transitioning from a high level to a low level. The output period T0 of the clock signal CT1 is then: That is, for the same output frequency with the same duty cycle D, C1 / I1 can also be reduced to half of its original value. If it is necessary to further reduce the output period T0 of the clock signal CT1, a larger frequency divider 21 can be used, such as a 3 / 4, 4 / 5, or 8 / 8 divider, to reduce the output period T0 of the clock signal CT1 to one-third, one-quarter, or one-eighth of the original output signal period. Thus, the duty cycle of the output digital pulse signal can be adjusted.

[0087] Furthermore, trigger 3 controls the duty cycle D of the output signal according to the clock signal CT1 and the analog sampling signal CT2 to generate a digital pulse signal. Trigger 3 outputs a high level according to the analog sampling signal CT2 output by analog signal sampling module 1, and flips to a low level according to the clock signal CT1 output by clock signal generation module 2, and repeats this pattern in a loop to realize the output of digital pulse signal, thereby realizing the conversion of the acquired analog signal into a digital pulse signal.

[0088] According to the embodiment of the present invention, the analog-to-digital conversion circuit 10 can reduce the output period T0 of the clock signal CT1 by a factor of two by adding a frequency divider 21 and a narrow pulse generation circuit unit 22 to the clock signal generation module 2. This satisfies the requirements of various application scenarios for the duty cycle D output frequency without increasing the first capacitor C1 or reducing the first current source I1, thus effectively reducing costs. It also satisfies the precise matching of the first current source I1 and the second current source I2, thereby reducing hardware requirements.

[0089] In some embodiments of the present invention, such as Figure 7 The diagram shown is a block diagram of a chip according to an embodiment of the present invention, wherein the chip 100 includes the analog-to-digital conversion circuit 10 of any of the above embodiments.

[0090] Specifically, by employing the analog-to-digital converter circuit 10 of any of the above embodiments in the chip 100, and by integrating the analog-to-digital converter circuit 10 inside the chip 100, two current sources are set to power the analog signal sampling module 1 and the clock signal generation module 2 respectively through the common source common gate current mirror L, so as to output the analog sampling signal CT2 and the clock signal CT1 respectively, and the flip-flop 3 controls the duty cycle D of the output signal according to the clock signal CT1 and the analog sampling signal to form a digital pulse signal.

[0091] In this embodiment of the invention, the duty cycle of the digital pulse signal output by chip 100 is affected by the input analog signal. Based on the analog sampling signal and clock signal, a digital pulse signal with a duty cycle that varies with the input analog signal can be output. Taking temperature acquisition as an example, when chip 100 is working, analog-to-digital conversion circuit 10 acquires the ambient temperature signal collected by NTC device in real time as the input analog signal, and then converts the ambient temperature signal into a corresponding digital pulse signal to achieve accurate detection of the ambient temperature signal. Based on the digital pulse signal, a control strategy can be generated, such as cooling or heating control, to ensure the working performance of the chip.

[0092] According to the chip 100 proposed in the embodiments of the present invention, an analog-to-digital converter circuit 10 of any of the above embodiments is adopted. The analog-to-digital converter circuit is provided with a clock signal generation module to generate a clock signal for the working cycle of the digital pulse signal. The clock signal generation module is set independently of the analog signal sampling module. Therefore, the component specifications or circuit layout of the analog signal sampling module and the clock signal generation module can be independently adjusted according to design requirements, so that the sampling range of the analog signal is wider, the adjustable range of the duty cycle of the output digital pulse signal can be increased, and the application range is wider.

[0093] Furthermore, by using the analog-to-digital conversion circuit of the above embodiment, the capacitance matching setting and current source synchronization setting can improve the duty cycle accuracy of the output digital pulse signal and achieve accurate detection of analog signals.

[0094] The following is a reference to the appendix. Figure 8 A motor drive device according to an embodiment of a third aspect of the present invention is described.

[0095] Figure 8 This is a block diagram of a motor drive device according to an embodiment of the present invention, such as... Figure 8 As shown, the motor drive device 300 of this embodiment includes an analog-to-digital conversion circuit 10 and a drive circuit 20 as described in any of the above embodiments, with the analog-to-digital conversion circuit 10 connected to the drive circuit 20.

[0096] The specific implementation structure of the analog-to-digital conversion circuit 10 can be referred to the description in the above embodiment, and will not be repeated here. The analog-to-digital conversion circuit 10 is used to convert the acquired analog signal into a digital pulse signal. The digital pulse signal is sent to the MCU (Microcontroller Unit). The MCU can monitor the acquired analog signal, such as the temperature, based on the received digital pulse signal. When an abnormality is detected by the digital pulse signal, the MCU sends a shutdown signal to the drive circuit 20. The drive circuit 20 shuts down the power module, such as the IGBT (Insulated Gate Bipolar Transistor) module, to control the motor to stop running. Conversely, when no abnormality is detected by the digital pulse signal, the MCU sends a control signal to enable the drive circuit 20 to drive the power module to conduct, so that the motor can run normally.

[0097] According to the embodiment of the present invention, the motor drive device 300 adopts the analog-to-digital conversion circuit 10 of the above embodiment, which can obtain analog signals with a wider sampling range and more accurate signal detection. Therefore, the device is applicable to more diverse environments and has more stable performance.

[0098] The following is a reference to the appendix. Figure 9 An electrical device according to an embodiment of a fourth aspect of the present invention is described.

[0099] Figure 9 This is a block diagram of an electrical device according to an embodiment of the present invention, such as... Figure 9 As shown, the electrical device 400 of this embodiment includes the chip 100 and power module 401 from the previous embodiment, with the chip 100 connected to the power module 401. The power module 401 may include transistors such as IGBTs and MOSFETs, or circuits composed of them, for driving electronic appliances. The chip 100 includes an analog-to-digital converter (ADC) circuit for converting input analog signals into digital pulse signals. This ADC circuit includes an independently configured clock signal generation module and an analog signal sampling module; the specific structure can be referred to the description of the previous embodiment, and will not be repeated here.

[0100] In some embodiments, the electrical equipment 400 may include a motor drive, an on-board charger, a high-voltage heating device, etc.

[0101] According to the embodiment of the present invention, the electrical device 400 adopts the chip 100 of the above embodiment. The analog-to-digital conversion circuit of the chip 100 can make the sampling range of analog signals wider and increase the adjustable range of the duty cycle of the output digital pulse signal, thus making it more widely applicable. Therefore, the electrical device 400 is applicable to more diverse environments and has more stable performance.

[0102] The following is a reference to the appendix. Figure 10 A vehicle according to an embodiment of the fifth aspect of the present invention is described.

[0103] Figure 10 This is a block diagram of a vehicle according to an embodiment of the present invention, such as... Figure 10 As shown, the vehicle 2000 of this embodiment includes at least one electrical device 400 from the above embodiments. For example, the electrical device 400 may include a motor drive device, an on-board charger, a high-voltage heating device, etc. The chip of the electrical device 400 uses the analog-to-digital conversion circuit of the above embodiments, which can obtain data with a wider sampling range and has a wider range of applications. Therefore, the performance of the vehicle 2000, such as motor drive, charging, and high-voltage heating, is more stable.

[0104] Based on the analog-to-digital conversion circuit and chip of the above embodiments, a sixth aspect of the present invention proposes a device. Figure 11 A block diagram of a device according to an embodiment of the present invention, such as Figure 11 As shown, the device 1000 includes the chip 100 and controller 200 of the second aspect embodiment above.

[0105] Chip 100 is used to convert the acquired analog signal VIN into a digital pulse signal. Specifically, chip 100 includes an analog-to-digital converter circuit 10. When chip 100 is working, the analog-to-digital converter circuit 10 is used to generate an analog sampling signal CT2 based on the analog signal VIN, generate a clock signal CT1, and control the duty cycle D of the output signal based on the clock signal CT1 and the analog sampling signal to generate a digital pulse signal, thereby realizing the accurate detection of analog signals such as ambient temperature.

[0106] The controller 200 is connected to the chip 100 and is used to receive digital pulse signals and generate control commands based on the digital pulse signals, enabling more precise control strategies. For example, when the chip 100 is working, the analog-to-digital converter 10 acquires the ambient temperature signal collected by the NTC device in real time as the input analog signal, and then converts the ambient temperature signal into a corresponding digital pulse signal to achieve accurate detection of the ambient temperature signal. Based on this digital pulse signal, a control strategy can be generated, such as cooling or heating control, to ensure the chip's working performance and improve the stability of the device.

[0107] The device 1000 proposed according to the embodiments of the present invention uses the chip of the above embodiments. The chip includes the analog-to-digital conversion circuit of any of the above embodiments. The analog-to-digital conversion circuit has a wide range of applications and can meet the different requirements of the device for the chip. The signal detection is more accurate and the device works more stably.

[0108] Other configurations and operations of the chip 100 and device 1000 according to embodiments of the present invention are known to those skilled in the art and will not be described in detail here.

[0109] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

[0110] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example.

[0111] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims

1. An analog-to-digital converter circuit, characterized in that, include: An analog signal sampling module, which is used to acquire analog signals and generate analog sampled signals; A clock signal generation module, wherein the clock signal generation module is used to generate a clock signal; A trigger, wherein the first input terminal of the trigger is connected to the output terminal of the analog signal sampling module, the second input terminal of the trigger is connected to the output terminal of the clock signal generation module, and the output terminal of the trigger is connected to the switch control terminal of the analog signal sampling module. The trigger is used to control the duty cycle of the output signal according to the clock signal and the analog sampling signal to generate a digital pulse signal. The clock signal generation module includes a first current source, a first capacitor, and a first comparator. The first terminal of the first capacitor is connected to the first current source, the second terminal of the first capacitor is grounded, the first input terminal of the first comparator is connected to the first terminal of the first capacitor, the second input terminal of the first comparator is used to input a reference voltage, and the output terminal of the first comparator is connected to the second input terminal of the flip-flop. The analog signal sampling module includes a second current source and a second capacitor. The first terminal of the second capacitor is connected to the second current source, and the second terminal of the second capacitor is grounded. The reference voltage is set according to the capacitance ratio of the first capacitor and the second capacitor, and the current ratio of the second current source and the first current source.

2. The analog-to-digital converter circuit according to claim 1, characterized in that, The first comparator is used to generate the clock signal based on the voltage of the first capacitor and the reference voltage; The clock signal generation module further includes: a first switching transistor, the first end of which is connected to the first current source and the first end of the first capacitor, the second end of which is grounded, and the switching control terminal of which is connected to the output terminal of the first comparator, for controlling the voltage of the first capacitor by turning it on or off according to the clock signal.

3. The analog-to-digital converter circuit according to claim 2, characterized in that, The clock signal generation module further includes: A frequency divider, wherein the input terminal of the frequency divider is connected to the output terminal of the first comparator, is used to divide the clock signal to obtain a frequency-divided signal; A narrow pulse generation circuit unit is provided, wherein the input terminal of the narrow pulse generation circuit unit is connected to the output terminal of the frequency divider, and the output terminal of the narrow pulse generation circuit unit is connected to the second input terminal of the flip-flop, for generating a narrow pulse signal based on the frequency division signal as the final clock signal.

4. The analog-to-digital converter circuit according to claim 3, characterized in that, The narrow pulse generation circuit unit is a leading edge blanking circuit, which is used to perform leading edge blanking processing on the frequency division signal to generate the narrow pulse signal.

5. The analog-to-digital converter circuit according to any one of claims 2-4, characterized in that, The analog signal sampling module further includes: The second switch has its first terminal connected to the first terminal of the second capacitor, its second terminal grounded, and its switching control terminal connected to the output terminal of the trigger, for controlling the voltage of the second capacitor by turning it on or off according to the output signal of the trigger. The second comparator has its first input terminal connected to the first terminal of the second capacitor, its second input terminal used to receive an analog signal, and its output terminal connected to the first input terminal of the flip-flop, used to generate the analog sampling signal based on the voltage of the second capacitor and the analog signal.

6. The analog-to-digital converter circuit according to claim 5, characterized in that, The reference voltage is set according to the capacitance ratio of the first capacitor to the second capacitor and the current ratio of the second current source to the first current source, wherein the reference voltage is inversely proportional to the capacitance ratio or the current ratio.

7. The analog-to-digital converter circuit according to claim 6, characterized in that, The first current source and the second current source are configured to share a common current source according to a preset current ratio by a common source cascode current mirror.

8. The analog-to-digital converter circuit according to claim 6, characterized in that, The capacitance values ​​of the first capacitor and the second capacitor are set in equal proportion.

9. A chip, characterized in that, Includes the analog-to-digital converter circuit as described in any one of claims 1-8.

10. A motor drive device, characterized in that, It includes the analog-to-digital conversion circuit and the driving circuit as described in any one of claims 1-8, wherein the analog-to-digital conversion circuit is connected to the driving circuit.

11. An electrical device, characterized in that, The electrical device includes the chip and power module as described in claim 9, wherein the chip is connected to the power module.

12. A vehicle, characterized in that, It includes at least one electrical device as described in claim 11.

13. A device, characterized in that, include: The chip of claim 9 is used to convert the acquired analog signal into a digital pulse signal; A controller, connected to the chip, is used to receive the digital pulse signal and generate control commands based on the digital pulse signal.

Images