A network processor based on chiplet architecture

Abstract

The purpose of this application is to provide a network processor based on a chiplet architecture. The processor includes a network task processing die and several computing dies. The computing dies are connected to the network task processing die, offloading network processing tasks to the network task processing die. The computing dies send data to the network task processing die. The network task processing die receives data from the computing dies or an external network, performs corresponding network processing, and then sends the data back to the computing dies or the external network. This application achieves TB / s level interconnect bandwidth by encapsulating the computing dies and network task processing dies within the same package. By offloading network processing tasks to other dies within the same package, the computing dies only need to handle general computing tasks, thereby freeing up CPU computing resources and improving CPU computing power.

Description

Technical Field

[0001] This application relates to the field of network communication technology, and more specifically, to a network processor based on chiplet architecture. Background Technology

[0002] A network interface card (NIC) is a Layer 2 (Link Layer) network component that serves as the interface between a computer and the transmission medium in a local area network (LAN). It not only establishes the physical connection and electrical signal matching between the LAN and the transmission medium but also handles frame transmission and reception, frame encapsulation and decapsulation, media access control, data encoding and decoding, and data buffering. Currently, NICs primarily use the PCIe standard, with the host controlling the NIC to send and receive network data via the PCIe protocol. However, with the increase in network bandwidth, all PCIe devices compete for limited PCIe bandwidth, and the host and PCIe NIC need to communicate by transmitting additional descriptors. Therefore, under the requirements of high bandwidth and low latency, PCIe has gradually become a performance bottleneck for 40G, 100G, and even higher network bandwidths.

[0003] Meanwhile, as Moore's Law slows down, the gap between network bandwidth and computing power is widening, making traditional CPUs insufficient for network processing. For example, processing network protocols at line speed for 10G requires approximately four Xeon CPU cores. This means that processing network data packets alone can consume half the computing power of an 8-core high-end CPU. Considering high-speed networks like 40G and 100G, the performance overhead becomes even more unbearable. Summary of the Invention

[0004] The purpose of this application is to provide a network processor based on a chiplet architecture. By changing the structure of the network processor, the network processing tasks are offloaded to other dies within the same package, so that the computing dies only need to handle general computing tasks, thereby freeing up the CPU's computing resources and improving the CPU's computing power.

[0005] The processor includes a network task processing die and several computing dies;

[0006] The computing dies are connected to the network task processing dies, and the network processing tasks are offloaded to the network task processing dies.

[0007] The compute die sends data to the network task for processing the die.

[0008] After receiving data from the computing chip or external network, the network task processing chip performs the corresponding network processing and sends it back to the computing chip or external network.

[0009] Optionally, the computing die and the network task processing die use a die-to-die standard.

[0010] Optionally, the computing die and the network task processing die are directly interconnected within the same package.

[0011] Optionally, the network task processing die is an FPGA die;

[0012] The computing die is directly interconnected with the FPGA die, offloading network processing tasks to the FPGA die.

[0013] The computing die sends data directly to the network FPGA die;

[0014] After receiving data from the computing die or an external network, the FPGA die performs the corresponding network processing and sends the processed data back to the computing die or the external network.

[0015] Optionally, the network task processing die is an ASIC die;

[0016] The computing die is directly interconnected with the ASIC die, offloading network processing tasks to the ASIC die.

[0017] The computing die sends data directly to the network ASIC die;

[0018] After receiving data from a computing die or an external network, the ASIC die performs the corresponding network processing and sends the processed data back to the computing die or the external network.

[0019] Optionally, the network task processing die includes ASIC dies and FPGA dies;

[0020] The computing die is interconnected with the FPGA die, the FPGA die is interconnected with the ASIC die, and the computing die offloads network processing tasks to the ASIC die and the FPGA die.

[0021] The computing die directly sends data to the FPGA die;

[0022] The FPGA die receives data from the compute die or ASIC die, performs corresponding network processing, and then sends the processed data back to the compute die or ASIC die.

[0023] After receiving data from the FPGA die or an external network, the ASIC die performs corresponding network processing and sends the processed data to the FPGA die or the external network.

[0024] Optionally, the network processor further includes I / O dies;

[0025] The computing dies and network task processing dies are interconnected via I / O dies.

[0026] Optionally, the network task processing die is an FPGA die;

[0027] The computing die is connected to the FPGA die via an I / O die, offloading network processing tasks to the FPGA die.

[0028] The computing die offloads network processing tasks onto the FPGA die;

[0029] The computing die sends data to the FPGA die via the I / O die;

[0030] The FPGA die receives data from the I / O die or an external network, performs corresponding network processing, and then sends the processed data to the external network, or sends the processed data to the computing die via the I / O die.

[0031] Optionally, the network task processing die is an ASIC die;

[0032] The computing die is connected to the ASIC die via the I / O die, offloading network processing tasks to the ASIC die;

[0033] The computing die offloads network processing tasks onto the ASIC die;

[0034] The computing die sends data to the ASIC die via the I / O die;

[0035] The ASIC die receives data from the I / O die or an external network, performs corresponding network processing, and then sends the processed data to the external network, or sends the processed data to the computing die via the I / O die.

[0036] Optionally, the network task processing die includes ASIC dies and FPGA dies;

[0037] The computing die is interconnected with the FPGA die via an I / O die, and the FPGA die is interconnected with the ASIC die. The computing die offloads network processing tasks to the ASIC die and the FPGA die.

[0038] The computing die sends data to the FPGA die via the I / O die;

[0039] The FPGA die receives data from the I / O die or the ASIC die, performs corresponding network processing, and then sends the processed data to the ASIC die, or sends the processed data to the computing die via the I / O die.

[0040] After receiving data from the FPGA die or an external network, the ASIC die performs corresponding network processing and sends the processed data to the FPGA die or the external network.

[0041] As can be seen from the above, this application provides a network processor based on a chiplet architecture. By packaging the computing die and the network task processing die into the same package, this application can achieve interconnect bandwidth at the TB / s level. The computing die offloads network processing tasks to other dies within the same package, allowing the computing die to handle only general computing tasks, thereby freeing up CPU computing resources and improving CPU computing power.

[0042] Other features and advantages of this application will be set forth in the following description and will be apparent in part from the description or may be learned by practicing embodiments of this application. The objectives and other advantages of this application may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings. Attached Figure Description

[0043] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0044] Figure 1 A block diagram of a network processor based on a chiplet architecture is provided for embodiments of this application;

[0045] Figure 2 A block diagram of a network processor with an FPGA die for processing network tasks.

[0046] Figure 3 A block diagram of a network processor with an ASCII die for processing network tasks.

[0047] Figure 4 A block diagram of a network processor that uses FPGA and ASCII dies for processing network tasks.

[0048] Figure 5 This is a block diagram of a network processor where the FPGA die is used for network task processing, and the FPGA die is interconnected with the compute die via I / O dies.

[0049] Figure 6 This is a block diagram of a network processor where the network task processing die is an ASCI die, and the ASCI die is interconnected with the compute die via an I / O die.

[0050] Figure 7 The network task processing die is an FPGA die and an ASIC die. The network task processing die is interconnected with the computing die through the IO die.

[0051] In the diagram, 1-network processor based on chiplet architecture, 11-computing die, 12-network task processing die, 13-IO die. Detailed Implementation

[0052] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0053] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0054] Please refer to Figure 1 This is a block diagram of a network processor based on a chiplet architecture according to this application. The processor includes a network task processing die 12 and several computing dies 11.

[0055] The computing die 11 is connected to the network task processing die 12, and the network processing task is offloaded to the network task processing die 12.

[0056] The computation die 11 sends data to the network task processing die 12;

[0057] After receiving data from computing chip 11 or an external network, network task processing chip 12 performs corresponding network processing and sends the data to computing chip 11 or the external network.

[0058] According to an embodiment of the present invention, the computing die 11 and the network task processing die 12 use a die-to-die standard.

[0059] It should be noted that the computing die 11 and the network task processing die 12 use a die-to-die standard, rather than the traditional PCIe protocol, thus avoiding PCIe becoming a bottleneck for network performance.

[0060] According to an embodiment of the present invention, the computing die 11 and the network task processing die 12 are directly interconnected within the same package. A dedicated die within the same package is used to process network tasks, instead of an external network interface card (NIC). Higher data bandwidth can be supported within the same package.

[0061] According to an embodiment of the present invention, the network task processing die 12 is an FPGA die;

[0062] The computing die 11 is directly interconnected with the FPGA die, thus offloading network processing tasks to the FPGA die.

[0063] The computing die 11 sends data directly to the network task processing FPGA die;

[0064] After receiving data from computing die 11 or an external network, the FPGA die performs corresponding network processing and sends the processed data to computing die 11 or the external network.

[0065] It should be noted that, as a specific embodiment, such as Figure 2 As shown, the network task processing die 12 is an FPGA die, and within the same package, the computing die 11 and the network task processing FPGA die are directly interconnected through advanced packaging technology. In this structure, multiple computing dies 11 offload network processing tasks to the network task processing FPGA die. The computing dies 11 directly send data to the network task processing FPGA die or directly receive data from the network task processing FPGA die. After receiving data from the computing die 11 or an external network, the network task processing FPGA die performs the corresponding network processing and sends it back to the computing die 11 or the external network.

[0066] According to an embodiment of the present invention, the network task processing die 12 is an ASIC die;

[0067] The computing die 11 is directly interconnected with the ASIC die, offloading network processing tasks to the ASIC die.

[0068] The computing die 11 sends data directly to the network task processing ASIC die;

[0069] After receiving data from computing die 11 or an external network, the ASIC die performs corresponding network processing and sends the processed data to computing die 11 or the external network.

[0070] It should be noted that, as a specific embodiment, such as Figure 3 As shown, the network task processing die 12 is an ASIC die. Within the same package, the computing die 11 and the network task processing ASIC die are directly interconnected using advanced packaging technology. In this structure, multiple computing dies 11 offload network processing tasks to the network task processing ASIC die. The computing dies 11 directly send data to the network task processing ASIC die or directly receive data from the network task processing ASIC die. After receiving data from the computing die 11 or an external network, the network task processing ASIC die performs the corresponding network processing and sends the data back to the computing die 11 or the external network.

[0071] According to an embodiment of the present invention, the network task processing die 12 includes an ASIC die and an FPGA die;

[0072] The computing die 11 is interconnected with the FPGA die, and the FPGA die is interconnected with the ASIC die. The computing die 11 offloads network processing tasks to the ASIC die and the FPGA die.

[0073] The computing die 11 directly sends data to the FPGA die;

[0074] The FPGA die receives data from the computing die 11 or the ASIC die, performs corresponding network processing, and then sends the processed data to the computing die 11 or the ASIC die.

[0075] After receiving data from the FPGA die or an external network, the ASIC die performs corresponding network processing and sends the processed data to the FPGA die or the external network.

[0076] It should be noted that, as a specific embodiment, such as Figure 4As shown, the network task processing die includes an ASIC die and an FPGA die; within the same package, the computing die 11 and the network task processing die 12 are directly interconnected via advanced packaging technology. The network task processing die 12 consists of a network task processing FPGA die and a network task processing ASIC die. In this structure, multiple computing dies 11 offload network processing tasks to the network task processing FPGA die and the network task processing ASIC die. The computing dies 11 directly send data to the network task processing FPGA die or directly receive data from the network task processing FPGA die. After receiving data from the computing die 11 or the network task processing ASIC die, the network task processing FPGA die performs the corresponding network processing and sends the data back to the computing die 11 or the network task processing ASIC die. After receiving data from the network task processing FPGA die or an external network, the network task processing ASIC die performs the corresponding network processing and sends the data back to the network task processing FPGA die or the external network.

[0077] According to an embodiment of the present invention, the network processor further includes an I / O die 13; the computing die 11 and the network task processing die 12 are interconnected through the I / O die 13.

[0078] According to an embodiment of the present invention, the network task processing die 12 is an FPGA die;

[0079] The computing die 11 is connected to the FPGA die via the I / O die 13, offloading the network processing task to the FPGA die;

[0080] The computing die 11 offloads the network processing tasks onto the FPGA die;

[0081] The computing die 11 sends data to the FPGA die via the IO die 13;

[0082] The FPGA die receives data from the IO die 13 or an external network, performs corresponding network processing, and then sends the processed data to the external network, or sends the processed data to the computing die 11 via the IO die 13.

[0083] It should be noted that, as a specific embodiment, such as Figure 5As shown, the network task processing die is an FPGA die. Within the same package, several computing dies 11 and the network task processing FPGA die are connected to the I / O die 13 via advanced packaging technology, thus indirectly interconnecting the computing dies 11 and the network task processing FPGA die. In this structure, multiple computing dies 11 offload network processing tasks to the network task processing FPGA die. The computing dies 11 send data to the network task processing FPGA die via the I / O die 13, or receive data from the network task processing FPGA die via the I / O die 13. After receiving data from the computing dies 11 or the external network, the network task processing FPGA die performs corresponding network processing and sends the data back to the computing dies 11 or the external network.

[0084] According to an embodiment of the present invention, the network task processing die 12 is an ASIC die;

[0085] The computing die 11 is connected to the ASIC die via the I / O die 13, offloading the network processing task to the ASIC die;

[0086] The computing die 11 offloads network processing tasks onto the ASIC die;

[0087] The computing die 11 sends data to the ASIC die via the IO die 13;

[0088] The ASIC die receives data from the IO die 13 or an external network, performs corresponding network processing, and then sends the processed data to the external network, or sends the processed data to the computing die 11 via the IO die 13.

[0089] It should be noted that, as a specific embodiment, such as Figure 6 As shown, the network task processing die 12 is an ASIC die. Within the same package, several computing dies 11 and the network task processing ASIC die are connected to the I / O die 13 via advanced packaging technology, thus indirectly interconnecting the computing dies 11 and the network task processing ASIC die. In this structure, multiple computing dies 11 offload network processing tasks to the network task processing ASIC die. The computing dies 11 send data to the network task processing ASIC die via the I / O die 13, or receive data from the network task processing ASIC die via the I / O die 13. After receiving data from the computing die 11 or the external network, the network task processing ASIC die performs corresponding network processing and sends the data back to the computing die 11 or the external network.

[0090] According to an embodiment of the present invention, the network task processing die 12 includes an ASIC die and an FPGA die;

[0091] The computing die 11 is interconnected with the FPGA die via the I / O die 13, and the FPGA die is interconnected with the ASIC die. The computing die 11 offloads network processing tasks to the ASIC die and the FPGA die.

[0092] The computing die 11 sends data to the FPGA die via the I / O die 13;

[0093] The FPGA die receives data from the IO die 13 or the ASIC die, performs corresponding network processing, and then sends the processed data to the ASIC die, or sends the processed data to the computing die 11 through the IO die 13.

[0094] After receiving data from the FPGA die or an external network, the ASIC die performs corresponding network processing and sends the processed data to the FPGA die or the external network.

[0095] It should be noted that, as a specific embodiment, such as Figure 7 As shown, the network task processing die 12 includes an ASIC die and an FPGA die. Within the same package, several computing dies 11 are connected to the network task processing die 12 via advanced packaging technology to an I / O die 13, thus indirectly interconnecting the computing dies 11 and the network task processing die 12. The network task processing die 12 consists of a network task processing FPGA die and a network task processing ASIC die. In this structure, multiple computing dies 11 offload network processing tasks to the network task processing FPGA die and the network task processing ASIC die. The computing dies 11 send data to the network task processing FPGA die via the I / O die 13, or receive data from the network task processing FPGA die via the I / O die 13. After receiving data from the computing dies 11 or the network task processing ASIC die, the network task processing FPGA die performs corresponding network processing and sends the data to the computing dies 11 or the network task processing ASIC die. After receiving data from the network task processing FPGA die or an external network, the network task processing ASIC die performs corresponding network processing and sends the data to the network task processing FPGA die or the external network.

[0096] This application provides a network processor based on a chiplet architecture. By packaging the computing die 11 and the network task processing die 12 into the same package, this application can achieve interconnect bandwidth at the TB / s level. The computing die 11 offloads network processing tasks to other dies within the same package, allowing the computing die 11 to handle only general computing tasks, thereby freeing up CPU computing resources and improving CPU computing power.

[0097] Furthermore, the network task processing die 12 and the computing die 11 use a die-to-die standard instead of the traditional PCIe protocol. The PCIe protocol can only obtain interconnect bandwidth at the GB / s level, thus avoiding PCIe becoming a bottleneck for network performance.

[0098] Because the computing die 11 and the network task processing die 12 are directly interconnected within the same package, no other modules share the bandwidth, resulting in lower processing latency. In contrast, existing network cards use a PCIe interface, which competes with other PCIe devices for the limited PCIe bandwidth, leading to higher actual processing latency.

[0099] The network task processing chip 12 is divided into FPGA chips and ASIC chips. Network task processing functions can be implemented using either the FPGA chip or the ASIC chip alone, or both can be used simultaneously. The ASIC chip handles more mature and fixed tasks, such as the physical layer and data link layer functions in the OSI model, while more flexible functions requiring continuous updates are implemented using the FPGA chip. This design fully considers the high-performance processing capabilities of the ASIC chip and the high flexibility of the FPGA chip. It can meet the rapidly growing business needs of today's data centers. Furthermore, while meeting high-performance network task processing capabilities, the network card also possesses high flexibility and user-friendly programmability. Existing network cards can only satisfy one of these two aspects—high-performance processing capabilities and high flexibility—or a compromise between the two, unable to simultaneously meet both requirements.

[0100] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces, and the indirect coupling or communication connection between devices or units can be electrical, mechanical, or other forms.

[0101] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units. They may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0102] In addition, each functional unit in the various embodiments of this application can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be implemented in hardware or in the form of hardware plus software functional units.

[0103] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0104] Alternatively, if the integrated units of this invention are implemented as software functional modules and sold or used as independent products, they can also be stored in a readable storage medium. Based on this understanding, the technical solutions of the embodiments of this invention, or the parts that contribute to the prior art, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, ROM, RAM, magnetic disks, or optical disks.

Claims

1. A network processor based on a chiplet architecture, characterized in that, The processor comprises a network task processing die and a plurality of computing dies; The computing dies are connected with the network task processing die to offload network processing tasks to the network task processing die; The computing dies send data to the network task processing die; The network task processing die receives data from the computing dies or an external network, performs corresponding network processing, and sends the processed data to the computing dies or the external network; Die-to-Die standards are used between the computing dies and the network task processing die; The computing dies and the network task processing die are directly interconnected in the same package.

2. The network processor based on the chiplet architecture according to claim 1, wherein, The network task processing die is an FPGA die; The computing dies are directly interconnected with the FPGA die to offload network processing tasks to the FPGA die; The computing dies send data directly to the network FPGA die; The FPGA die receives data from the computing dies or an external network, performs corresponding network processing, and sends the processed data to the computing dies or the external network.

3. The network processor based on the chiplet architecture according to claim 1, wherein, The network task processing die is an ASIC die; The computing dies are directly interconnected with the ASIC die to offload network processing tasks to the ASIC die; The computing dies send data directly to the network ASIC die; The ASIC die receives data from the computing dies or an external network, performs corresponding network processing, and sends the processed data to the computing dies or the external network.

4. The network processor based on chiplet architecture according to claim 1, wherein, The network task processing die comprises an ASIC die and an FPGA die; The computing dies are interconnected with the FPGA die, the FPGA die is interconnected with the ASIC die, and the computing dies offload network processing tasks to the ASIC die and the FPGA die; The computing dies send data directly to the FPGA die; The FPGA die receives data from the computing dies or the ASIC die, performs corresponding network processing, and sends the processed data to the computing dies or the ASIC die; The ASIC die receives data from the FPGA die or an external network, performs corresponding network processing, and sends the processed data to the FPGA die or the external network.

5. The network processor based on chiplet architecture according to claim 1, wherein, The network processor further comprises an IO die; The computing dies and the network task processing die are interconnected through the IO die.

6. The network processor based on chiplet architecture according to claim 5, wherein, The network task processing die is an FPGA die; The computing dies are connected with the FPGA die through the IO die to offload network processing tasks to the FPGA die; The computing dies offload network processing tasks to the FPGA die; The computing dies send data to the FPGA die through the IO die; The FPGA die receives data from the IO die or an external network, performs corresponding network processing, and sends the processed data to the external network or the computing dies through the IO die.

7. The network processor based on chiplet architecture according to claim 5, wherein, The network task processing die is an ASIC die; The computing dies are connected with the ASIC die through the IO die to offload network processing tasks to the ASIC die; The computing dies offload network processing tasks to the ASIC die; The computing dies offload network processing tasks to the ASIC die; The computing die sends data to the ASIC die through the IO die; The ASIC die receives data from the IO die or an external network, performs corresponding network processing, and sends the processed data to the external network or the computing die through the IO die.

8. The network processor based on chiplet architecture according to claim 5, wherein, The network task processing die includes an ASIC die and an FPGA die; The computing die is interconnected with the FPGA die through the IO die, and the FPGA die is interconnected with the ASIC die, and the computing die offloads network processing tasks to the ASIC die and the FPGA die; The computing die sends data to the FPGA die through the IO die; The FPGA die receives data from the IO die or the ASIC die, performs corresponding network processing, and sends the processed data to the ASIC die or the computing die through the IO die; The ASIC die receives data from the FPGA die or an external network, performs corresponding network processing, and sends the processed data to the FPGA die or the external network.

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