Three-dimensional modeling method, system, medium and device for chip layout etching structure
By constructing a 3D model on the chip layout, the problem of the inability to perform 3D scale analysis on 2D layouts is solved, enabling more intuitive analysis of the etching structure.
Patent Information
- Application Number
- CN202310320876.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-03-29
- Publication Date
- 2025-12-09
- Estimated Expiration
- 2043-03-29
AI Technical Summary
In existing technologies, chip layouts are designed as two-dimensional planar graphics, making it impossible to perform intuitive three-dimensional scale analysis, which makes it difficult to check the accuracy of the etched structure.
By determining the modeling area of the chip layout, the first graphic is obtained and an etched pattern is constructed in three-dimensional space. Combined with the deposition pattern and the bridging pattern, a complete three-dimensional model is formed.
It enables the conversion from two-dimensional layout to three-dimensional model, facilitating intuitive three-dimensional scale analysis and improving the visualization and analysis accuracy of etched structures.
Smart Images
Figure CN116167326B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of chip layout design, in particular to a three-dimensional modeling method, system, medium and equipment for chip layout etching structure. BACKGROUND
[0002] The chip layout is the basis for chip preparation. For some chips, a groove or other etching structure needs to be made on the plane through the etching process. Accordingly, in the chip layout design, a graph representing the etching range needs to be drawn. However, since all graphs of the chip layout are drawn on a plane, it is a two-dimensional layout, and the visualization degree of the two-dimensional layout is low, and it is not possible to intuitively analyze in three-dimensional scale to check the accuracy of the layout. The position of the etching structure on the chip layout in the horizontal direction and the vertical direction can only be judged subjectively by human beings. If the two-dimensional layout can be converted into a three-dimensional model, three-dimensional scale analysis can be more subjective. However, the software currently supporting the drawing of the chip layout does not have this function. SUMMARY
[0003] The purpose of the present application is to provide a three-dimensional modeling method, system, medium and equipment for chip layout etching structure, so as to solve the problem that the two-dimensional layout cannot meet the three-dimensional scale analysis in the prior art, and to convert the two-dimensional layout into a three-dimensional model, so as to facilitate intuitive three-dimensional scale analysis.
[0004] To solve the above technical problems, the present application provides a three-dimensional modeling method for chip layout etching structure, comprising:
[0005] Determine the modeling area of the chip layout, and obtain the first graph in the modeling area on the chip layout, the first graph being used to define the shape of etching;
[0006] Determine the feature area which is not overlapped with the first graph in the modeling area;
[0007] Determine the reference surface in the three-dimensional space, and construct the etching block with the first thickness on the reference surface with the feature area as the bottom surface.
[0008] Preferably, the step of constructing the etching block with the first thickness on the reference surface with the feature area as the bottom surface comprises:
[0009] Constructing a feature bottom surface with the same shape as the feature area on the reference surface;
[0010] Geometrically stretching the feature bottom surface in the direction perpendicular to the reference surface according to the first thickness to obtain the etching block.
[0011] Preferably, the method further comprises:
[0012] constructing a foundation block with a preset thickness on the reference surface and taking the modeling region as a bottom surface;
[0013] aligning the bottom surface of the foundation block with the bottom surface of the etching block and placing the etching block on the foundation block.
[0014] Preferably, the step of constructing a foundation block with a preset thickness on the reference surface and taking the modeling region as a bottom surface comprises:
[0015] constructing a foundation bottom surface with the same shape as the modeling region on the reference surface;
[0016] geometrically stretching the foundation bottom surface in a direction perpendicular to the reference surface according to the preset thickness to obtain the foundation block.
[0017] Preferably, the chip layout further has a second pattern located in the modeling region and overlapping the first pattern, and the second pattern is used to define the shape of deposition.
[0018] acquiring the second pattern located in the modeling region on the chip layout;
[0019] determining the overlapping region and the non-overlapping region of the second pattern and the first pattern;
[0020] constructing a first deposition block with a second thickness on the reference surface and taking the overlapping region as a bottom surface, and constructing a second deposition block with the second thickness and taking the non-overlapping region as a bottom surface;
[0021] placing the first deposition block on the reference surface according to the position of the second pattern in the modeling region, and placing the second deposition block on the etching block.
[0022] Preferably, the method further comprises:
[0023] when the first thickness is greater than the second thickness, constructing a bridging block which is in contact with both the first deposition block and the second deposition block.
[0024] Preferably, the height of the bridging block does not exceed the first thickness, and the projection of the bridging block on the reference surface does not exceed the range of the overlapping region.
[0025] To solve the above technical problems, the application further provides a three-dimensional modeling system of a chip layout etching structure, comprising:
[0026] a pattern acquisition module, used for determining a modeling region of a chip layout, and acquiring a first pattern located in the modeling region on the chip layout, wherein the first pattern is used to define the shape of etching;
[0027] a graphics determining module configured to determine a feature region in which the modeling region does not overlap with the first graphics;
[0028] a model constructing module configured to determine a reference surface in a three-dimensional space, and construct an etching graphics block with a first thickness on the reference surface and with the feature region as a bottom surface.
[0029] To solve the above technical problems, the application further provides a storage medium, wherein the storage medium stores a computer program, and the computer program is configured to execute the three-dimensional modeling method of the chip layout etching structure when running.
[0030] To solve the above technical problems, the application further provides an electronic device comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to execute the three-dimensional modeling method of the chip layout etching structure when running the computer program.
[0031] Different from the prior art, the three-dimensional modeling method of the chip layout etching structure provided by the application comprises the following steps: obtaining a first graphics on a chip layout in a modeling region, determining a feature region in which the modeling region does not overlap with the first graphics, and determining a reference surface in a three-dimensional space, and constructing an etching graphics block with a first thickness on the reference surface and with the feature region as a bottom surface.
[0032] The three-dimensional modeling system of the chip layout etching structure, the storage medium and the electronic device provided by the application belong to the same inventive concept as the three-dimensional modeling method of the chip layout etching structure, and thus have the same beneficial effects, which will not be described herein. BRIEF DESCRIPTION OF DRAWINGS
[0033] Figure 1 The three-dimensional modeling method of the chip layout etching structure provided by the application is shown in the flowchart.
[0034] Figure 2 The position relationship between the modeling region and the first graphics on the chip layout is shown in the schematic diagram.
[0035] Figure 3 The etching graphics block constructed on the reference surface is shown in the schematic diagram.
[0036] Figure 4 The feature bottom surface constructed on the reference surface is shown in the schematic diagram. Figure 1 The specific flowchart of step S3 in the three-dimensional modeling method is shown in the schematic diagram.
[0037] Figure 5 The feature bottom surface constructed on the reference surface is shown in the schematic diagram.
[0038] Figure 6This is a schematic diagram showing the positional relationship between the foundation block and the etched block constructed on the reference plane.
[0039] Figure 7 for Figure 1 The diagram shows the specific process flow of step S4 in the 3D modeling method.
[0040] Figure 8 A flowchart illustrating a three-dimensional modeling method for chip layout etching structure provided in another embodiment of the present invention.
[0041] Figure 9 This is a schematic diagram showing the positional relationship between the first and second graphics within the modeling area on the chip layout.
[0042] Figure 10 This is a schematic diagram showing the positional relationship between the first sedimentation patch, the second sedimentation patch, and the etched patch in three-dimensional space.
[0043] Figure 11 This is a schematic diagram showing the positional relationship between the bridging block and the first and second sedimentation blocks in three-dimensional space.
[0044] Figure 12 A schematic diagram of a three-dimensional modeling system for chip layout etching structure provided in another embodiment of the present invention. Detailed Implementation
[0045] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description and claims. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.
[0046] In the description of this invention, it should be understood that the terms "center", "upper", "lower", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.
[0047] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.
[0048] Please refer to Figure 1The embodiment of the present application provides a three-dimensional modeling method of a chip layout etching structure.
[0049] S1: determine a modeling area of a chip layout, and acquire a first graph in the modeling area on the chip layout, the first graph being used to define the shape of etching.
[0050] The modeling area is an area representing a modeling range, and the modeling area can be the entire chip layout or a part of the chip layout. Considering that the chip layout is usually drawn on a rectangular interface, the shape of the modeling area is preferably rectangular.
[0051] The modeling area can be determined according to user operation, for example, the user inputs the coordinates of four vertices, sequentially connects the four vertices to form a rectangular frame, and the area enclosed by the rectangular frame is the modeling area, or the user manually selects two vertices on the chip layout, takes the two vertices as diagonal vertices to form a rectangular frame, and the area enclosed by the rectangular frame is the modeling area, or the user performs a frame selection operation on the chip layout, forms a rectangular frame according to the frame selection operation, and the area enclosed by the rectangular frame is the modeling area.
[0052] Regardless of how the modeling area is determined, it is necessary to ensure that the first graph is located in the modeling area. The first graph represents the shape of etching, that is, the shape of the etched part on the chip, which is a specific graph on the chip layout but corresponds to an etched structure on the chip.
[0053] As shown in the figure, the rectangular frame BOX represents the modeling area, and the graph A represents the first graph. Figure 2
[0054] S2: determine a feature area which does not overlap with the first graph in the modeling area.
[0055] The modeling area is a part of the chip layout and is also a graph, and the first graph is in the modeling area, so there is an overlapping part and a non-overlapping part between the two, and the feature area is the non-overlapping part. That is, the feature area is a hollowed-out graph. As shown in the figure, the shaded part represents the feature area. Figure 2
[0056] S3: determine a reference surface in a three-dimensional space, and construct an etching block with a first thickness on the reference surface with the feature area as a bottom surface.
[0057] The three-dimensional space is a 3D display interface, and the reference plane is a plane of the three-dimensional space, which can be a plane of XY coordinate axis of the three-dimensional coordinate system XYZ, or a plane of XZ coordinate axis, or a plane of YZ coordinate axis, or a self-defined plane. After the three-dimensional space is created or called, a reference plane needs to be determined, and an etching block with a first thickness is constructed on the reference plane. The first thickness is a modeling thickness set by a user or a default modeling thickness.
[0058] The upper and lower surfaces of the etching block have the same shape as that of the feature region. Since the feature region is hollow in the middle, the etching block is also hollow in the middle, which is consistent with the physical structure of the actual chip. As shown in FIG. 6, the three-dimensional structure D in the figure represents the etching block, the etching block D is constructed on the XY plane, the top view shape of the etching block D is the same as that of the modeling region, and the etching block D directly shows the three-dimensional structure after etching. Figure 3
[0059] In the foregoing manner, the three-dimensional modeling method of the chip layout etching structure according to the embodiments of the present application converts a graphic representing an etching shape from a two-dimensional plane graphic to a three-dimensional solid graphic, and can directly show a three-dimensional structure after etching, so that the present application can convert a two-dimensional layout into a three-dimensional model, and facilitate intuitive three-dimensional scale analysis. Moreover, the present application first determines a region after the first graphic is removed as a bottom surface, then geometrically stretches the bottom surface to obtain a hollow three-dimensional solid graphic, instead of directly establishing a three-dimensional solid graphic of the modeling region, and then hollowing out the three-dimensional solid graphic, which can greatly reduce the calculation resources and improve the three-dimensional view performance.
[0060] In some embodiments of the present application, please refer to Figure 4 The step of constructing the etching block with the first thickness on the reference plane with the feature region as the bottom surface, that is, step S3, includes:
[0061] S31: constructing a feature bottom surface with the same shape as that of the feature region on the reference plane.
[0062] The feature bottom surface has the same shape as that of the feature region, and the feature bottom surface is also a two-dimensional plane graphic, but the difference is that the feature bottom surface is constructed in a three-dimensional space. As shown in FIG. 5, the feature bottom surface D1 is constructed on the XY plane of the three-dimensional coordinate system XYZ. Figure 5
[0063] S32: geometrically stretching the feature bottom surface in a direction perpendicular to the reference plane to obtain the etching block with the first thickness.
[0064] The feature bottom surface is composed of many points, and geometrically stretching each point is to transform the point into a line with a length of the first thickness, and the line transformed from each point constitutes the etching block. As shown in FIG. 6, the feature bottom surface D1 is constructed on the XY plane of the three-dimensional coordinate system XYZ.Figure 3 As shown in FIG. 3, after geometric stretching of the feature bottom surface D1, an etching block D is obtained, the upper and lower surfaces of the etching block D have the same shape as the feature bottom surface D1, and the height of the etching block D is the first thickness h1.
[0065] In some embodiments of the present application, referring again to Figure 1 , the three-dimensional modeling method of the chip layout etching structure further comprises:
[0066] S4: constructing a foundation block with a preset thickness on the reference surface and taking the modeling region as the bottom surface;
[0067] S5: aligning the bottom surface of the foundation block with the bottom surface of the etching block, and placing the etching block on the foundation block.
[0068] Since the chip layout usually does not draw the chip substrate, and in practice the etching structure is formed on the substrate, in order to more realistically display the etching structure, the embodiment constructs a foundation block to represent the substrate. The foundation block is a structure with parallel upper and lower surfaces and a height of a preset thickness, and the shapes of the upper and lower surfaces are the same as the modeling region. As shown in FIG. 3, the three-dimensional structure F in the figure represents the foundation block, the thickness of the foundation block F is h, and the etching block D is placed on the foundation block F, and the two are aligned and attached to each other. Figure 6
[0069] Further, referring to Figure 7 , the step of constructing a foundation block with a preset thickness on the reference surface and taking the modeling region as the bottom surface, i.e., step S4, comprises:
[0070] S41: constructing a basic bottom surface with the same shape as the modeling region on the reference surface;
[0071] S42: geometrically stretching the basic bottom surface in the direction perpendicular to the reference surface according to the preset thickness to obtain the foundation block.
[0072] Among them, the foundation block is obtained by geometric stretching, like the etching block described above.
[0073] Referring to Figure 8 , another embodiment of the present application provides a three-dimensional modeling method of a chip layout etching structure. The three-dimensional modeling method of the present embodiment comprises all the technical features of the three-dimensional modeling method of the foregoing embodiment, and the difference lies in that the chip layout further has a second pattern located in the modeling region and overlapping with the first pattern part, the second pattern is used to define the shape of deposition, and the etching process sequence of the first pattern is before the deposition process sequence of the second pattern. After step S3 of the three-dimensional modeling method of the foregoing embodiment, the three-dimensional modeling method of the present embodiment further comprises the following steps:
[0074] S6: Obtain a second pattern on the chip layout within the modeling region.
[0075] In the determination of the modeling region, it is necessary to ensure that the first pattern and the second pattern are located within the modeling region. The second pattern represents the shape of the deposition, representing the deposition structure that needs to be formed on the chip by the deposition process, such as a thin film. As shown in Figure 9 The first pattern A and the second pattern B partially overlap, and both are located within the modeling region BOX.
[0076] S7: Determine the overlapping region and the non-overlapping region of the second pattern and the first pattern.
[0077] In which the second pattern partially overlaps the first pattern, then there are overlapping parts and non-overlapping parts between the two, the part of the second pattern that overlaps the first pattern is the overlapping region, and the part of the second pattern that does not overlap the first pattern is the non-overlapping region. As shown in Figure 9 Pattern B1 represents the overlapping region, and pattern B2 represents the non-overlapping region.
[0078] S8: Construct a first deposition block of a second thickness with the overlapping region as the bottom surface on the reference surface, and construct a second deposition block of a second thickness with the non-overlapping region as the bottom surface.
[0079] In which the first deposition block is a structure with parallel upper and lower surfaces and a height of the second thickness, and the second deposition block is also a structure with parallel upper and lower surfaces and a height of the second thickness, the shape of the upper and lower surfaces of the first deposition block is the same as that of the overlapping region, and the shape of the upper and lower surfaces of the second deposition block is the same as that of the non-overlapping region. The second thickness is a user-set or default modeling thickness.
[0080] S9: Place the first deposition block on the reference surface and the second deposition block on the etching block according to the position of the second pattern within the modeling region.
[0081] In which the overlapping region of the second pattern is located within the first pattern, and the first pattern is the etched region, so the first deposition block is just located within the hollow range of the etching block, corresponding to the physical structure of the actual chip, the first deposition block cannot be suspended, so the first deposition block is placed on the reference surface. The non-overlapping region of the second pattern is located within the feature region, so the second deposition block just avoids the hollow range of the etching block, corresponding to the physical structure of the actual chip, the second deposition block is placed on the etching block, as shown in Figure 10As shown in the figure, the three-dimensional structure C1 represents the first deposition block, and the three-dimensional structure C2 represents the second deposition block. Both the first deposition block C1 and the second deposition block C2 are structures with parallel upper and lower surfaces and a height of the second thickness h2. The first deposition block C1 is placed on the reference surface within the hollow range of the etching block D, and the second deposition block C2 is placed on the etching block S.
[0082] In some embodiments of the present application, the three-dimensional modeling method of the present embodiment further comprises:
[0083] S9A: When the first thickness is greater than the second thickness, a bridge block that is in contact with both the first deposition block and the second deposition block is constructed.
[0084] If the first thickness is greater than the second thickness, the first deposition block and the second deposition block will be disconnected. However, in actual film deposition, the part outside the etching structure is continuous with the part inside the etching structure. In order to more realistically show the three-dimensional structure of the chip layout, the present embodiment represents the physical connection between the first deposition block and the second deposition block by constructing a bridge block. As shown in the figure, Figure 11 When the first thickness h1 is greater than the second thickness h2, the first deposition block C1 and the second deposition block C2 are disconnected, and the physical connection between the two can be achieved through the bridge block C3.
[0085] The bridge block is only used to represent the physical connection between the first deposition block and the second deposition block, which may not be consistent with the actual physical structure of the chip. In order to avoid the influence of the bridge block on the three-dimensional view of the chip layout, in the present embodiment, the height of the bridge block does not exceed the first thickness, and the projection of the bridge block on the reference surface does not exceed the range of the overlapping area. As shown in the figure, Figure 11 The height of the bridge block C3 is less than the first thickness h1, and the cross section of any part of the bridge block C3 does not exceed the range of the overlapping area B1.
[0086] Please refer to Figure 12 Another embodiment of the present application provides a three-dimensional modeling system of an etching structure of a chip layout. The system comprises:
[0087] The graphic acquisition module 1 is used to determine the modeling area of the chip layout and acquire the first graphic on the chip layout within the modeling area. The first graphic is used to define the shape of etching. The modeling area is an area representing the modeling range. The modeling area can be the entire chip layout or a part of the chip layout. Considering that the chip layout is usually drawn on a rectangular interface, the shape of the modeling area is preferably rectangular.
[0088] The modeling area can be determined according to the operation of the user, for example, the user inputs the coordinates of four vertices, sequentially connects the four vertices to form a rectangular frame according to the coordinates of the four vertices, and the area enclosed by the rectangular frame is the modeling area, or the user manually selects two vertices on the chip layout as diagonal vertices to form a rectangular frame, and the area enclosed by the rectangular frame is the modeling area, or the user performs a marquee operation on the chip layout, forms a rectangular frame according to the marquee operation, and the area enclosed by the rectangular frame is the modeling area.
[0089] Regardless of how the modeling area is determined, it is necessary to ensure that the first graph is located in the modeling area. The first graph represents the shape of etching, that is, the shape of the etched part on the chip, which is a specific graph on the chip layout, but corresponds to an etched structure that is etched on the chip
[0090] The graph determination module 2 is used to determine a feature area in which the modeling area and the first graph do not overlap. The modeling area is a part of the chip layout and is also a graph, and the first graph is in the modeling area, so there is an overlapping part and a non-overlapping part between the two, and the feature area is the non-overlapping part. That is, the feature area is a hollow graph.
[0091] The model construction module 3 is used to determine a reference surface in a three-dimensional space, and to construct an etching tile of a first thickness on the reference surface with the feature area as the bottom surface. The three-dimensional space is a 3D display interface, the reference surface is a plane in the three-dimensional space, which can be a plane in which the XY coordinate axis of the three-dimensional coordinate system is located, or a plane in which the XZ coordinate axis is located, or a plane in which the YZ coordinate axis is located, or a self-defined plane. After creating or calling the three-dimensional space, a reference surface needs to be determined, and the etching tile constructed on the reference surface is a structure with parallel upper and lower surfaces and a height of the first thickness. The first thickness is a modeling thickness set by the user or a default modeling thickness.
[0092] The upper and lower surfaces of the etching tile have the same shape as the feature area. Since the feature area is hollow in the middle, the middle of the etching tile is hollow, which is consistent with the physical structure of the actual chip.
[0093] In the above manner, the three-dimensional modeling system for the chip layout etching structure of the embodiment of the application converts the graph representing the etching range from a two-dimensional plane graph to a three-dimensional solid graph, can intuitively display the three-dimensional structure after etching, and thus the application can convert a two-dimensional layout into a three-dimensional model, facilitating intuitive three-dimensional scale analysis.
[0094] The three-dimensional modeling system of the embodiment can also include other technical features of the three-dimensional modeling method of the chip layout etching structure, implement all method steps of the three-dimensional modeling method of the aforementioned embodiments, and have the same technical effects as the three-dimensional modeling method of the aforementioned embodiments, which will not be described here.
[0095] The application also provides a storage medium, which stores a computer program, and the computer program is configured to execute the three-dimensional modeling method of the chip layout etching structure of any one of the aforementioned embodiments when running.
[0096] Specifically, in the embodiment, the storage medium can include but is not limited to a U disk, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store computer programs.
[0097] The application also provides an electronic device, which includes a memory and a processor, the memory stores a computer program, and the processor is configured to execute the three-dimensional modeling method of the chip layout etching structure of any one of the aforementioned embodiments when running the computer program.
[0098] Specifically, the memory and the processor can be connected through a data bus. In addition, the electronic device can also include a transmission device and an input / output device, wherein the transmission device is connected with the processor, and the input / output device is connected with the processor.
[0099] In the description of the present specification, the description of the terms "one embodiment", "some embodiments", "an example", or "a specific example" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in the present specification.
[0100] The above is only the preferred embodiment of the present application, and does not limit the present application in any way. Any person skilled in the art can make any form of equivalent replacement or modification of the technical solutions and technical contents disclosed in the present application without departing from the scope of the technical solutions of the present application, which still belongs to the protection scope of the present application.
Claims
1. A method for three-dimensional modeling of a chip layout etching structure, the method comprising: The method comprises the following steps: determining a modeling area of a chip layout, and obtaining a first pattern in the modeling area on the chip layout, the first pattern being used to define a shape of etching, the chip layout further having a second pattern in the modeling area and partially overlapping the first pattern, the second pattern being used to define a shape of deposition; determining a feature area where the modeling area does not overlap the first pattern; determining a reference surface in a three-dimensional space, and constructing an etching block with a first thickness on the reference surface and with the feature area as a bottom surface; obtaining a second pattern in the modeling area on the chip layout; determining an overlapping area and a non-overlapping area of the second pattern and the first pattern; constructing a first deposition block with a second thickness on the reference surface and with the overlapping area as a bottom surface, and constructing a second deposition block with the second thickness on the reference surface and with the non-overlapping area as a bottom surface; placing the first deposition block on the reference surface and the second deposition block on the etching block according to a position of the second pattern in the modeling area.
2. The method of claim 1, wherein, The step of constructing the etching block with the first thickness on the reference surface and with the feature area as a bottom surface comprises the following steps: constructing a feature bottom surface on the reference surface and with the same shape as the feature area; geometrically stretching the feature bottom surface in a direction perpendicular to the reference surface by the first thickness to obtain the etching block.
3. The method of claim 1, wherein, The method further comprises the following steps: constructing a foundation block with a preset thickness on the reference surface and with the modeling area as a bottom surface; aligning a bottom surface of the foundation block with a bottom surface of the etching block, and placing the etching block on the foundation block.
4. The method of claim 3, wherein, The step of constructing the foundation block with the preset thickness on the reference surface and with the modeling area as a bottom surface comprises the following steps: constructing a foundation bottom surface on the reference surface and with the same shape as the modeling area; geometrically stretching the foundation bottom surface in a direction perpendicular to the reference surface by the preset thickness to obtain the foundation block.
5. The method of claim 1, wherein, The method further comprises the following steps: when the first thickness is greater than the second thickness, constructing a bridge block which is in contact with both the first deposition block and the second deposition block.
6. The method of claim 5, wherein, The height of the bridge block does not exceed the first thickness, and a projection of the bridge block on the reference surface does not exceed a range of the overlapping area.
7. A three-dimensional modeling system for chip layout etching structures, characterized in that, The method comprises the following steps: a pattern obtaining module is configured to determine a modeling area of a chip layout, and obtain a first pattern in the modeling area on the chip layout, the first pattern being used to define a shape of etching, the chip layout further having a second pattern in the modeling area and partially overlapping the first pattern, the second pattern being used to define a shape of deposition; a pattern determining module is configured to determine a feature area where the modeling area does not overlap the first pattern; a model constructing module is configured to determine a reference surface in a three-dimensional space, and construct an etching block with a first thickness on the reference surface and with the feature area as a bottom surface; the pattern obtaining module is further configured to obtain a second pattern in the modeling area on the chip layout; the pattern determining module is further configured to determine an overlapping area and a non-overlapping area of the second pattern and the first pattern; the model constructing module is further configured to construct a first deposition block with a second thickness on the reference surface and with the overlapping area as a bottom surface, and construct a second deposition block with the second thickness on the reference surface and with the non-overlapping area as a bottom surface. The model constructing module is further configured to construct a first deposition patch of a second thickness on the reference surface with the overlapping area as a bottom surface, construct a second deposition patch of the second thickness on the reference surface with the non-overlapping area as a bottom surface, and place the first deposition patch on the reference surface and the second deposition patch on the etching patch according to the position of the second pattern in the modeling area.
8. A storage medium, characterized by The storage medium stores a computer program, and the computer program is configured to execute the three-dimensional modeling method of the chip layout etching structure according to any one of claims 1 to 6 when running.
9. An electronic device, comprising: The computer device comprises a memory and a processor, and the memory stores a computer program, and the processor is configured to execute the three-dimensional modeling method of the chip layout etching structure according to any one of claims 1 to 6 when running the computer program.