Self-aligned hole preparation method and semiconductor device

Abstract

The present invention relates to a method for preparing a self-aligned hole and a semiconductor device, the semiconductor device comprising: a trench sidewall gate structure, comprising a gate formed at the bottom of the sidewall of the trench, and an insulating material covering the gate in the trench; a source region, arranged below the trench; a drain region, arranged at both sides of the top of the trench; wherein the semiconductor device is further provided with a source contact hole penetrating downwardly through the insulating material to the source region, the source contact hole is filled with a conductive material so as to be electrically connected to the source region, the source contact hole passes between the gates on both sides of the trench, and an etching barrier layer is formed on the sidewall of the source contact hole. The present invention can reduce the Ron,sp of the device.

Description

Technical Field

[0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for preparing a self-aligning hole, and also to a semiconductor device. Background Art

[0002] With the rise of new technologies such as new energy vehicles and 5G transmission, the demand for power MOSFET device performance is getting higher and higher. For power DMOS, the turn-on voltage Vt, on-resistance Rdson, saturation current Idsat, off-state breakdown voltage BVoff, etc. are its key parameters. Among them, the specific on-resistance (Specific On Resistance, Ron,sp) of the drift region and the device breakdown voltage (Breakdown Voltage, BV) have a contradictory relationship: Ron,sp∝BV β . Summary of the invention

[0003] Based on this, it is necessary to provide a method for preparing a self-aligned hole, and a semiconductor device manufactured using this method can reduce the specific on-resistance.

[0004] A method for preparing a self-aligned hole comprises: obtaining a wafer with a groove sidewall gate structure; forming a groove on the wafer, forming a gate at the bottom of the sidewall of the groove, and forming an insulating material covering the gate on the sidewall of the groove; forming an etching barrier layer located inside the insulating material on the sidewall of the groove; the distance from the etching barrier layer on one side of the sidewall to the etching barrier layer on the other side is d; filling the insulating material into the groove, and adopting a filling process that cannot completely fill the groove, thereby forming a cavity inside the etching barrier layer in the groove; forming an interlayer dielectric layer on the insulating material; photolithographically forming an etching window with a width of d on the interlayer dielectric layer, and etching the interlayer dielectric layer and the insulating material downward through the etching window, the etching barrier layer forming a barrier to etching, thereby self-aligning etching to form a contact hole with a width of d.

[0005] The above-mentioned method for preparing the self-aligned hole forms an etching barrier layer on the inner side of the insulating material of the groove sidewall, which leads to a reduction in the groove width and an increase in the aspect ratio. The groove with a high aspect ratio cannot be completely filled during filling, so that a cavity is formed between the etching barrier layers on both sides of the filled groove. In this way, the thickness of the insulating material to be etched during contact hole etching is reduced (the cavity is equivalent to not etching the insulating material), so the thickness of the photoresist required for contact hole lithography can also be reduced. After the photoresist thickness is reduced, the minimum limit of the CD of the contact hole that can be obtained is correspondingly reduced, so the area of ​​the device is also reduced accordingly. Since Ron,sp is the product of area and resistance, the area is reduced and Ron,sp is also reduced accordingly. And since the etching barrier layer is formed, the contact hole is self-aligned when etching, so the alignment of the contact hole etching will not be affected by the cavity in the groove.

[0006] In one of the embodiments, before the step of forming the etch stop layer on the inner side of the insulating material on the side wall of the trench, the step also includes processing the insulating material on the top of the trench to partially remove the insulating material, so that the top opening of the trench is enlarged to form a first opening that is larger at the top and smaller at the bottom; the step of forming the etch stop layer on the inner side of the insulating material on the side wall of the trench includes: depositing the etch stop layer; and removing the etch stop layer at the bottom of the trench and outside the trench by dry etching.

[0007] In one embodiment, the material of the etch stop layer is silicon nitride, and the insulating material is silicon oxide.

[0008] In one embodiment, in the step of depositing the etch stop layer, the thickness of the deposited etch stop layer is

[0009] In one of the embodiments, d is 0.1 to 0.3 microns, the aspect ratio of the area filled in the step of filling the insulating material into the trench is 6:1 to 20:1, and the filling process is a high-density plasma chemical vapor deposition process.

[0010] In one of the embodiments, in the step of photolithographically forming an etching window with a width of d on the interlayer dielectric layer, the thickness of the photoresist on the interlayer dielectric layer during photolithographic exposure is no more than 0.7 microns, and the lithography machine is a deep ultraviolet lithography machine.

[0011] In one of the embodiments, the method further includes forming a source region in the semiconductor material at the bottom of the trench and filling the contact hole with a conductive material, wherein the conductive material is electrically connected to the source region.

[0012] In one of the embodiments, the step of forming a drain region in the semiconductor material on both sides of the top of the trench is also included, and the gate is located between the drain region and the source region, and the source region, drain region and gate are the source region, drain region and gate of the VDMOS device.

[0013] In one of the embodiments, the minimum limit value of the lateral distance from the center of the source region to the gate is 0.32 microns.

[0014] It is also necessary to provide a semiconductor device.

[0015] A semiconductor device comprises: a trench sidewall gate structure, comprising a gate formed at the bottom of the sidewall of the trench, and an insulating material in the trench covering the gate; a source region, arranged below the trench; and a drain region, arranged on both sides of the top of the trench; wherein the semiconductor device is also provided with a source contact hole penetrating downward through the insulating material to the source region, the source contact hole is filled with a conductive material so as to be electrically connected to the source region, the source contact hole passes between the gates on both sides of the trench, and an etching barrier layer is formed on the sidewalls of the source contact hole.

[0016] The semiconductor device described above can reduce the required distance margin between the source contact hole and the gate by setting an etching barrier layer so that the source contact hole is a self-aligned etching contact hole. Therefore, the lateral distance from the source region to the gate is reduced, the area of ​​the device is also reduced accordingly, and Ron,sp is reduced accordingly.

[0017] In one embodiment, the material of the etch stop layer is silicon nitride, and the insulating material is silicon oxide.

[0018] In one embodiment, the source region, the drain region and the gate are the source region, the drain region and the gate of a VDMOS device.

[0019] In one embodiment, the semiconductor device further includes: a substrate having a second conductivity type; a body region having the second conductivity type, the source region being arranged in the body region; a first conductivity type well region being arranged on the body region, the drain region being arranged in the first conductivity type well region; wherein the source contact hole penetrates the source region and the body region and extends into the substrate, the source region and the drain region have the first conductivity type, and the first conductivity type and the second conductivity type are opposite conductivity types. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more drawings. The additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the embodiments and / or examples currently described, and the best modes of these inventions currently understood.

[0021] Figure 1 is a schematic diagram of an exemplary VDMOS device architecture compatible with CMOS processes;

[0022] Figure 2 is a flow chart of a method for preparing a self-aligned hole in one embodiment;

[0023] Figure 3a to Figure 3f Is adopted Figure 2 A schematic diagram of the device structure during the preparation process of the preparation method shown;

[0024] Figure 4 It is a schematic structural diagram of a semiconductor device in one embodiment. DETAILED DESCRIPTION

[0025] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0027] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0028] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0029] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0030] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the invention. Thus, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the invention should not be limited to the specific shapes of the zones shown herein, but include shape deviations due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shape of the region of the device and are not intended to limit the scope of the invention.

[0031] The semiconductor field vocabulary used in this article is technical vocabulary commonly used by technical personnel in this field. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents P-type with heavy doping concentration, P-type represents P-type with medium doping concentration, P-type represents P-type with light doping concentration, N+ type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents N-type with light doping concentration.

[0032] Since Ron,sp∝BV β On the basis of ensuring the breakdown voltage of the device, the smaller the on-resistance, the better, that is, the β value needs to be reduced. Ron,sp is the product of area and resistance. The most direct and effective method is to reduce the area of ​​DMOS, and VDMOS has a relatively small area. However, VDMOS is generally led out from the back of the substrate, which is difficult to take into account the CMOS process, so VDMOS is generally used as a discrete device in the circuit.

[0033] In order to further reduce the chip area, the VDMOS process and the CMOS process need to be integrated into the manufacturing process of the same chip, so the source and drain ends of VMODS need to be brought out from the front side. Figure 1 An exemplary VDMOS device architecture compatible with CMOS process is shown, in which a body region 120 is formed on a substrate 110, a source region 122 is formed in the body region 120, a well region 130 is formed on the body region 120, and a trench is opened in the well region 130, the trench is filled with an insulating material 152, a gate 140 is formed at the bottom of the sidewall of the trench, and a drain region 132 is formed on the top of the well region 130. Since the source region 122 of the device structure is in the silicon body, it cannot share a hole with the drain region 132 ( Figure 1 The drain region 132 is led out through the hole 164), and another hole process is required to lead out the source region 122 ( Figure 1 The source region 122 is led out through the hole 162). The hole 162 and the hole 164 lead the source and drain terminals to the metal interconnection 172 on the front side of the device.

[0034] Exemplarily, after the trench is processed by polysilicon (poly) process to form gate 140, SACVD (sub-atmospheric pressure chemical vapor deposition) is used to deposit insulating material 152 to fill the trench completely. Since the critical dimension (CD) of the trench is large, the depth-to-width ratio is small, and the filling property is good. Therefore, the deep hole used to lead out the source region needs to be etched with a total thickness of 3.25 microns (0.75 microns thickness of interlayer dielectric 156 + 2.5 microns thickness of insulating material 152 in the trench). For the exemplary photoresist model, a photoresist thicker than 1.6 microns (selection ratio of silicon dioxide: photoresist = 2:1) is required, plus the remaining amount of glue window, a photoresist thicker than 1.7 microns is often required. If the photoresist is too thick, the following problems will arise: (1) The minimum exposure of 1.7-micron photoresist is 0.55 microns (i.e., the size of the pattern obtained by exposure and development is not less than 0.55 microns), so the size of the deep hole used to lead out the source region will be very large; (2) When the photoresist thickness reaches 1.8 microns, an I-line lithography machine is required, and the overlay accuracy (ovl) control limit of the I-line lithography machine is 90nm. Considering the process window, the distance between the deep hole used to lead out the source region and the poly needs to be increased to meet the operating requirements of the high-resolution lithography machine. Therefore, the size of the entire trench increases, resulting in an increase in the device area and an increase in the specific on-resistance.

[0035] Figure 2 1 is a flow chart of a method for preparing a self-aligned hole in one embodiment, comprising the following steps:

[0036] S210, obtaining a wafer having a trench sidewall gate structure formed thereon.

[0037] The trench sidewall gate structure can be seen in Figure 3a , including a substrate 10, a trench 11, a gate 20 and an insulating material 22. The gate 20 is formed at the bottom of the sidewall of the trench 11, and the insulating material 22 covers the gate 20 and the sidewall of the trench 11.

[0038] The base 10 includes a semiconductor substrate, and its material can be undoped single crystal silicon, single crystal silicon doped with impurities, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI).

[0039] In one embodiment of the present application, the gate 20 is made of polysilicon. In other embodiments, the gate 20 may also be made of metal, metal nitride, metal silicide or similar compounds.

[0040] In one embodiment of the present application, the insulating material 22 is silicon oxide, such as silicon dioxide.

[0041] In one embodiment of the present application, a shallow trench isolation structure is also formed on the obtained wafer having the trench sidewall gate structure formed thereon, and the shallow trench isolation structure may be a STI of a CMOS.

[0042] In one embodiment of the present application, the insulating material 22 at the top of the groove 11 can be processed to partially remove the insulating material 22, so that the top opening of the groove 11 is enlarged to form a first opening that is larger at the top and smaller at the bottom, see Figure 3b The first opening is similar to the mouth of a bell.

[0043] In one embodiment of the present application, the first opening may be formed by sputtering using a CVD (chemical vapor deposition) machine; or the first opening may be formed by bombarding the insulating material 22 at the top of the groove 11 with plasma using an etching machine.

[0044] S220 , forming an etching stop layer on the sidewall of the trench and located inside the insulating material.

[0045] When a contact hole is subsequently formed in the trench 11 by etching, the etching stop layer 34 serves as the hole wall of the contact hole to achieve self-aligned etching.

[0046] In one embodiment of the present application, the material of the etch stop layer 34 is silicon nitride, such as silicon nitride. Figure 3c , a layer of etch stop layer 34 material can be first deposited on the wafer surface, and after deposition, the etch stop layer 34 is formed on the bottom and sidewalls of the groove 11, and the wafer surface outside the groove 11, that is, covering the insulating material 22 inside and outside the groove 11. In one embodiment of the present application, the deposition of the etch stop layer 34 is to use a furnace tube to deposit a layer of silicon nitride with a thickness of See also Figure 3d ,right Figure 3c The obtained structure is etched by an anisotropic etching process (such as dry etching) to remove the etching stop layer 34 at the bottom of the groove 11 and outside the groove 11. Figure 3b As shown in the bell mouth, when the etching thickness of the etching stop layer 34 is equal to the deposition thickness, it can be obtained that Figure 3d The structure shown.

[0047] S230, filling the trench with insulating material, and incomplete filling forms a cavity in the trench inside the etch stop layer.

[0048] In one embodiment of the present application, the distance d (see Figure 3d) is only 0.1 to 0.3 microns, so the aspect ratio of the deep groove between the etching stop layers 34 on both sides will reach 6:1 to 20:1. The deep groove with a high aspect ratio cannot be filled by filling the insulating material through the ordinary high-density plasma chemical vapor deposition (HDPCVD) process, leaving a long void. In one embodiment of the present application, the insulating material filled in step S230 is silicon oxide, such as silicon dioxide.

[0049] S240, forming an interlayer dielectric layer on the insulating material.

[0050] In one embodiment of the present application, an interlayer dielectric (ILD) layer 42 may be deposited on the surface of the wafer by a deposition process. After deposition, the surface of the interlayer dielectric layer 42 may be planarized by a CMP (chemical mechanical polishing) process, such as Figure 3e shown.

[0051] In one embodiment of the present application, the interlayer dielectric layer 42 may be a silicon oxide layer, for example, a doped or undoped silicon oxide material layer formed by a thermal chemical vapor deposition (thermal CVD) manufacturing process or a high-density plasma chemical vapor deposition (HDPCVD) manufacturing process, and specifically may be undoped silicon glass (USG), phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG). In addition, the interlayer dielectric may also be spin-on-glass (SOG) doped with boron or phosphorus, tetraethoxysilane doped with phosphorus (PTEOS) or tetraethoxysilane doped with boron (BTEOS).

[0052] S250, photolithography and etching the interlayer dielectric layer and the insulating material to form a contact hole that is self-aligned through the etching barrier layer.

[0053] In one embodiment of the present application, a photoresist is coated on the interlayer dielectric layer 42, and a photomask is used to expose the photoresist and then develop it to form an etching window with a deep groove aligned with the etching stop layer 34 and a width of the same d, and then the insulating material in the interlayer dielectric layer 42 and the groove 11 is etched through the etching window to obtain a contact hole. In one embodiment of the present application, the contact hole is used for source lead-out and is a long narrow groove structure. If the contact hole adopts an intermittent contact hole structure, it is difficult to implement in terms of process because the opening of the hole is originally small and the aspect ratio of the hole is too large. The insulating material in the groove 11 and the etching stop layer 34 can have a high etching selectivity. For example, for the insulating material being silicon dioxide and the etching stop layer 34 being silicon nitride, the etching selectivity of silicon dioxide and silicon nitride can reach 10:1, so the contact hole etching can be self-aligned through the etching stop layer 34. The device structure after the contact hole etching can refer to Figure 3f , Figure 3f The photoresist is not shown.

[0054] In the above-mentioned method for preparing the self-aligned hole, an etching stop layer 34 is formed inside the insulating material 22 of the side wall of the groove 11 to reduce the width of the groove 11 and increase the aspect ratio. The groove with a high aspect ratio cannot be completely filled during filling, so that a cavity 41 is formed between the etching stop layers 34 on both sides of the filled groove. In this way, the thickness of the insulating material to be etched during contact hole etching is reduced (the cavity is equivalent to not etching the insulating material), so the thickness of the photoresist required for contact hole photolithography can also be reduced (because when using photoresist as an etching stop layer, the thicker the structure to be etched, the thicker the photoresist required). After the photoresist thickness is reduced, the minimum limit of the CD of the contact hole that can be obtained is correspondingly reduced, so the area of ​​the device is also reduced accordingly. Since Ron,sp is the product of area and resistance, the area is reduced and Ron,sp is also reduced accordingly. And since the etching stop layer 34 is formed, the contact hole is self-aligned when etching, so the alignment of the contact hole etching will not be affected by the cavity 41 in the groove. And as long as the insulating material 22 in the groove 11 obtained in step S210 is symmetrical about the perpendicular bisector of the groove 11, the self-alignment process of the above-mentioned self-alignment hole preparation method can form a contact hole in the center of the groove, which can improve the uniformity of device parameters and improve the yield.

[0055] In one embodiment of the present application, the method for preparing the self-aligned hole further includes the step of forming a source region in the semiconductor material at the bottom of the trench, and the step of filling a conductive material in the contact hole in the trench, wherein the conductive material is electrically connected to the source region to serve as a source contact hole. In one embodiment of the present application, the conductive material filled in the source contact hole is metal tungsten. In other embodiments, the conductive material may also be any suitable conductive material well known to those skilled in the art, including but not limited to metal materials; wherein the metal material may include one or more of Ag, Au, Cu, Pd, Pt, Cr, Mo, Ti, Ta, W and Al.

[0056] In one embodiment of the present application, the method for preparing the self-aligned hole further includes the step of forming a drain region in the semiconductor material on both sides of the top of the trench, and the gate is located between the drain region and the source region.

[0057] Figure 4It is a schematic diagram of a device structure obtained by applying the self-aligned hole preparation method of the present application to the preparation of VDMOS (vertical double diffused metal oxide semiconductor field effect transistor) in an embodiment. A body region 420 is formed on a substrate 410, a source region 422 is formed in the body region 420, a well region 430 is formed on the body region 420, and a groove is opened in the well region 430, and the groove is filled with an insulating material 452. A gate 440 is formed at the bottom of the sidewall of the groove, and the bottom of the groove extends into a part of the body region 420, that is, the top of the body region 420 is higher than the bottom of the insulating material 452, so that the body region 420 and the gate 440 can also partially overlap in the vertical direction, and the gate 440 can act on the body region 420 to make the body region 420 inverted to form a sufficiently long channel. However, the longer the channel region is, the better it is, so a small amount of overlap between the gate 440 and the body region 420 can achieve a better effect. A drain region 432 is formed on the top of the well region 430, and an interlayer dielectric layer 456 is formed on the drain region 432. The source region 422 is led out to the metal interconnection 472 through the source contact hole 462, and the drain region 432 is led out to the metal interconnection 472 through the drain contact hole 464. An etching stopper layer 454 is formed on the sidewall of the source contact hole 462. In one embodiment of the present application, the source region 422, the drain region 432 and the well region 430 have a first conductivity type, and the substrate 410 and the body region 420 have a second conductivity type. In one embodiment of the present application, the first conductivity type is N type, and the second conductivity type is P type. Further, the well region 430 is a high voltage N-well (HV N-well), and the source region 422 and the drain region 432 are N+ regions. In another embodiment of the present application, the first conductivity type is P type, and the second conductivity type is N type.

[0058] Since the deep trench with a high aspect ratio cannot be filled in step S230, a void 41 is formed. In one embodiment of the present application, step S250 actually only needs to etch 0.75 microns of ILD thickness + 0.5 microns of insulating material thickness in the trench = 1.25 microns of silicon dioxide. In step S250, a photoresist with a thickness of more than 0.625 microns (selection ratio is silicon dioxide: photoresist = 2:1) needs to be formed. Adding the remaining amount window, a total of 0.7 microns of photoresist is required, and the CD limit of the contact hole can reach 0.2 microns. Therefore, Figure 1Compared with the scheme shown in FIG. 1 , the size of the contact hole can be reduced from 0.55 microns to 0.2 microns. On the other hand, in the exposure process of step S250, because the thickness of the photoresist is reduced to 0.7 microns, the thickness of the photoresist can meet the operating requirements of a high-resolution lithography machine, and a DUV (deep ultraviolet) lithography machine can be used for exposure. Therefore, the overlay accuracy (ovl) card control can be further reduced to 45nm. And because an etching stop layer is set as an etching stop, when the ovl value is relatively large, self-alignment etching can still be performed to the bottom of the groove, and there will be no problem of device uniformity, which can greatly improve the yield.

[0059] Considering the windows of ovl and CD, Figure 1 The minimum design distance between the hole 162 and the poly (polycrystalline silicon) of the gate 140 in the illustrated solution is 0.345 microns (90nm+55nm+200nm), where 90nm is the overlay card control, 55nm is 10% of the CD limit of the contact hole 0.55 microns, and 200nm is the thickness of the insulating material 152 (silicon dioxide) between the hole 162 and the gate 140 calculated according to the withstand voltage thickness theory; Figure 4In the illustrated embodiment, the minimum design distance between the source contact hole 462 and the poly of the gate 440 is 0.22 microns (45nm+20nm+155nm), wherein 45nm is the overlay card control, 20nm is 10% of the CD limit of the contact hole of 0.2 microns, and 155nm is the thickness of the insulating material 452 (silicon dioxide) + etching stop layer 454 (silicon nitride) between the contact hole 462 and the gate 440 calculated according to the withstand voltage thickness theory (the dielectric constant of silicon nitride is more than twice that of silicon dioxide and can therefore be thinned). It can be seen that this minimum design distance can reduce the device size by more than 0.1 microns. Exemplarily, the poly width is 0.2 microns, the gate oxide thickness is 0.02 microns, and the gate oxide thickness is ignored here. Therefore, the distance from the center of the source region to the trench boundary decreases from 0.82 microns (0.2+0.345+0.55 / 2) to 0.52 microns (0.2+0.22+0.2 / 2), wherein 0.2 in 0.2+0.345+0.55 / 2 is the poly width, 0.345 is the sum of 10% of the CD limit value of the contact hole and the overlay card control, and 0.55 is the opening size of the contact hole; 0.2 in 0.2+0.22+0.2 / 2 is the poly width, 0.22 is the sum of 10% of the CD limit value of the contact hole and the overlay card control, and 0.2 is the opening size of the contact hole. The half-pitch (half line width) from the source region to the drain region is reduced from 1.213 microns (0.393+0.82) to 0.913 microns (0.393+0.52), which is equivalent to a 25% reduction in the area of ​​the region. Because VDMOS is a vertical withstand voltage, the BV can be guaranteed to remain unchanged when the trench depth remains unchanged. The solution proposed in this patent can reduce the device area, which is equivalent to increasing the Ron,sp of the drift region by 25% when the BV remains unchanged, which is an extremely considerable improvement.

[0060] In one embodiment of the present application, the method for preparing the self-aligned hole further includes the step of performing rapid thermal annealing (RTA). Since RTA causes the silicon nitride film layer of the etch barrier layer to obtain stress and act on the drift region of the device, the electron mobility will be improved after the drift region obtains stress, so the current capacity of the device is improved, thereby further improving the Ron,sp of the device. In one embodiment, the VDMOS is an N-type VDMOS, and the etch barrier layer formed on the inner side of the insulating material on the sidewall of the groove is a tensile stress silicon nitride film layer, and the subsequent RTA causes the silicon nitride film layer of the etch barrier layer to obtain tensile stress and act on the drift region of the device, and the electron mobility will be improved after the drift region obtains tensile stress. In other embodiments, the VDMOS is a P-type VDMOS, and the etch barrier layer formed on the inner side of the insulating material on the sidewall of the groove is a compressive stress silicon nitride film layer, and the subsequent RTA causes the silicon nitride film layer of the etch barrier layer to obtain compressive stress and act on the drift region of the device, and the electron mobility will be improved after the drift region obtains compressive stress.

[0061] The present application accordingly provides a semiconductor device, comprising:

[0062] A trench sidewall gate structure, comprising a gate formed at the bottom of the sidewall of the trench, and an insulating material covering the gate in the trench;

[0063] A source region, disposed below the trench;

[0064] A drain region, disposed on both sides of the top of the trench;

[0065] Among them, the semiconductor device is also provided with a source contact hole that penetrates downward through the insulating material to the source region, the source contact hole is filled with conductive material so as to be electrically connected to the source region, the source contact hole passes between the gates on both sides of the trench, and an etching barrier layer is formed on the sidewalls of the source contact hole.

[0066] The semiconductor device described above can reduce the required distance margin between the source contact hole and the gate by setting an etching barrier layer so that the source contact hole is a self-aligned etching contact hole. Therefore, the lateral distance from the source region to the gate is reduced, the area of ​​the device is also reduced accordingly, and Ron,sp is reduced accordingly.

[0067] In one embodiment of the present application, the material of the etching stop layer is silicon nitride, such as silicon nitride; the insulating material is silicon oxide, such as silicon dioxide. Since RTA causes the silicon nitride film layer of the etching stop layer to obtain stress and act on the drift region of the device, the electron mobility will be improved after the drift region obtains stress, so the current capacity of the device is improved, thereby further improving the Ron,sp of the device.

[0068] In one embodiment of the present application, the source region, the drain region and the gate are the source region, the drain region and the gate of a VDMOS device.

[0069] In one embodiment of the present application, the semiconductor device further includes:

[0070] a substrate having a second conductivity type;

[0071] a body region having a second conductivity type, wherein the source region is disposed in the body region;

[0072] A first conductive type well region is disposed on the body region, and the drain region is disposed in the first conductive type well region;

[0073] The source contact hole penetrates the source region and the body region and extends into the substrate, the source region and the drain region have a first conductivity type, and the first conductivity type and the second conductivity type are opposite conductivity types.

[0074] In one embodiment of the present application, the gate is made of polysilicon.

[0075] In one embodiment of the present application, the semiconductor device further includes an interlayer dielectric layer disposed on the trench and the drain region.

[0076] The structure of the semiconductor device provided in this application can refer to Figure 4 In one embodiment of the present application, the minimum limit value of the lateral distance from the center of the source region 422 to the gate 440 is 0.32 microns.

[0077] It should be understood that, although the various steps in the flowchart of the present application are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowchart of the present application may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0078] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0079] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0080] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A method for preparing a self-aligned hole, comprising: Obtaining a wafer having a trench sidewall gate structure formed thereon; The wafer is formed with a groove, a gate is formed at the bottom of the sidewall of the groove, and an insulating material covering the gate is formed on the sidewall of the groove; An etch stop layer is formed on the sidewall of the trench and is located inside the insulating material; the distance from the etch stop layer on one side of the sidewall to the etch stop layer on the other side is d; Filling the insulating material into the trench, and using a filling process that cannot completely fill the trench, thereby forming a cavity inside the etch stop layer in the trench; forming an interlayer dielectric layer on the insulating material; Photolithographically forming an etching window with a width of d on the interlayer dielectric layer, and etching downward the interlayer dielectric layer and the insulating material through the etching window, wherein the etching barrier layer forms a barrier for etching so as to form a contact hole with a width of d by self-aligned etching; Wherein, d is 0.1-0.3 micrometers, and the aspect ratio of the area filled in the step of filling the insulating material into the trench is 6:1-20:

1.

2. The method for preparing a self-aligning hole according to claim 1, characterized in that: Before the step of forming an etching stop layer on the sidewall of the trench and located inside the insulating material, the step also includes processing the insulating material on the top of the trench to partially remove the insulating material, thereby expanding the top opening of the trench to form a first opening that is larger at the top and smaller at the bottom; The step of forming an etching stop layer on the sidewall of the trench and located inside the insulating material comprises: depositing the etch stop layer; The bottom of the trench and the etching stopper layer outside the trench are removed by dry etching.

3. The method for preparing a self-aligning hole according to claim 2, characterized in that: The material of the etching stop layer is silicon nitride, and the insulating material is silicon oxide.

4. The method for preparing a self-aligned hole according to claim 3, characterized in that: In the step of depositing the etch stop layer, the thickness of the deposited etch stop layer is 450-600Å.

5. The method for preparing a self-aligned hole according to claim 1, characterized in that: The filling process is a high-density plasma chemical vapor deposition process.

6. The method for preparing a self-aligned hole according to claim 1, characterized in that: In the step of photolithographically forming an etching window with a width of d on the interlayer dielectric layer, the thickness of the photoresist on the interlayer dielectric layer during photolithographic exposure is not greater than 0.7 microns, and the photolithography machine is a deep ultraviolet lithography machine.

7. The method for preparing a self-aligned hole according to claim 1, characterized in that: The method also includes the steps of forming a source region in the semiconductor material at the bottom of the trench and filling the contact hole with a conductive material, wherein the conductive material is electrically connected to the source region.

8. The method for preparing a self-aligned hole according to claim 7, characterized in that: It also includes the step of forming a drain region in the semiconductor material on both sides of the top of the trench, the gate is located between the drain region and the source region, and the source region, drain region and gate are the source region, drain region and gate of the VDMOS device.

9. The method for preparing a self-aligned hole according to claim 8, characterized in that: The minimum limit value of the lateral distance from the center of the source region to the gate is 0.32 microns.

10. A semiconductor device, characterized in that: include: A trench sidewall gate structure, comprising a gate formed at the bottom of the sidewall of the trench, and an insulating material covering the gate in the trench; A source region, disposed below the trench; A drain region, disposed on both sides of the top of the trench; The semiconductor device is further provided with a source contact hole penetrating downwardly through the insulating material to the source region, the source contact hole is filled with a conductive material so as to be electrically connected to the source region, the source contact hole passes between the gates on both sides of the groove, an etch barrier layer is formed on the sidewall of the source contact hole, and the insulating material is also provided between the etch barrier layer and the adjacent gate; the distance d from the etch barrier layer on one side of the sidewall to the etch barrier layer on the other side is 0.1 to 0.3 microns, and the aspect ratio of the area between the etch barrier layer on one side of the sidewall and the etch barrier layer on the other side is 6:1 to 20:

1.

11. The semiconductor device according to claim 10, characterized in that The material of the etching stop layer is silicon nitride, and the insulating material is silicon oxide.

12. The semiconductor device according to claim 10, characterized in that The source region, the drain region and the gate are the source region, the drain region and the gate of a VDMOS device.

13. The semiconductor device according to claim 10, characterized in that Also includes: a substrate having a second conductivity type; a body region having a second conductivity type, wherein the source region is disposed in the body region; A first conductive type well region is disposed on the body region, and the drain region is disposed in the first conductive type well region; The source contact hole penetrates the source region and the body region and extends into the substrate, the source region and the drain region have a first conductivity type, and the first conductivity type and the second conductivity type are opposite conductivity types.

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