Verification method and related equipment for FPGA network card

Abstract

The embodiment of the present application discloses a verification method and related equipment for an FPGA network card, the method comprising: performing PCAP packet capture through a PCAP packet capture component to obtain a first network data message, and when an abnormality exists in the first network data message, restoring the first network data message to a second network data message; importing the second network data message into an Ethernet interface in a verification environment through a UVM verification platform to send it to an FPGA network card for simulation; reading the configuration data of the FPGA network card through a configuration script, importing the configuration data into the verification environment, analyzing the configuration data, and obtaining a first analysis result; and distributing the configuration data to each module of the FPGA network card for simulation based on the first analysis result. The embodiment of the present application can improve the verification efficiency in the process of verifying the FPGA network card.

Description

Technical Field

[0001] The present application relates to the fields of communication technology and Internet technology, and specifically to a verification method and related equipment for an FPGA network card. Background Art

[0002] In the verification of field-programmable gate array (FPGA) network cards, the verification personnel need to construct the stimulus of the network protocol message and input it into the Ethernet port of the FPGA network card, and also construct the FPGA configuration stimulus and input it into the PCIE (PCI-Express) interface. These two parts require the verification personnel to constrain the stimulus according to different functional scenarios. The real network protocol message and the stimulus constructed by the verification personnel themselves will have a large gap, and cannot simulate the real network environment well. At the same time, it will also take a lot of time to maintain the stimulus constraint conflict in the environment. In the later FPGA board verification process, if problems that were not found in the simulation verification link are found, when the problems that occurred in the board need to be reproduced, the same protocol message and configuration stimulus as in the board process need to be input to approach the real board environment. The existing methods often construct similar message stimuli, and then the verification personnel construct the configuration stimulus according to the relevant scenarios and input it into the verification environment for simulation analysis. The verification effect often cannot reproduce the problems that occurred in the board process, and it also takes a lot of time and energy. Therefore, how to improve the verification efficiency in the process of verifying FPGA network cards needs to be solved urgently. Summary of the invention

[0003] The embodiment of the present application provides a verification method and related equipment for an FPGA network card, which can improve the verification efficiency during the verification of the FPGA network card.

[0004] In a first aspect, an embodiment of the present application provides a verification method for an FPGA network card, the method is applied to a verification system, the verification system comprising: a tester, an FPGA network card, and a UVM verification platform, the tester is communicatively connected with the FPGA network card and the UVM verification platform, wherein the UVM verification platform comprises: a PCAP packet capture component and a protocol analysis component;

[0005] Performing PCAP packet capture through the PCAP packet capture component to obtain a first network data message, and analyzing the first network data message to obtain target attribute information of the first network data message;

[0006] Detecting whether the target attribute information meets a preset condition through the protocol analysis component, and determining that the first network data message is abnormal when the target attribute information meets the preset condition; restoring the first network data message to obtain a normal second network data message;

[0007] The second network data message is imported into the Ethernet interface in the verification environment through the UVM verification platform to be sent to the FPGA network card for simulation; the configuration data of the FPGA network card is read through a configuration script, the configuration data is imported into the verification environment, the configuration data is analyzed to obtain a first analysis result; based on the first analysis result, the configuration data is distributed to each module of the FPGA network card for simulation.

[0008] In a second aspect, an embodiment of the present application provides a verification device for an FPGA network card, which is applied to a verification system, wherein the verification system includes: a tester, an FPGA network card, and a UVM verification platform, wherein the tester is communicatively connected with the FPGA network card and the UVM verification platform, wherein the UVM verification platform includes: a PCAP packet capture component and a protocol analysis component; the device includes: a data analysis unit, a data recovery unit and a verification unit, wherein,

[0009] The data analysis unit is used to perform PCAP packet capture through the PCAP packet capture component to obtain a first network data message, analyze the first network data message, and obtain target attribute information of the first network data message;

[0010] The data recovery unit is used to detect whether the target attribute information meets the preset condition through the protocol analysis component, and when the target attribute information meets the preset condition, determine that the first network data message is abnormal; recover the first network data message to obtain a normal second network data message;

[0011] The verification unit is used to import the second network data message into the Ethernet interface in the verification environment through the UVM verification platform to send it to the FPGA network card for simulation; read the configuration data of the FPGA network card through a configuration script, import the configuration data into the verification environment, analyze the configuration data, and obtain a first analysis result; based on the first analysis result, distribute the configuration data to each module of the FPGA network card for simulation.

[0012] In a third aspect, an embodiment of the present application provides an electronic device, comprising a processor, a memory, a communication interface, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the processor, and the program includes instructions for executing the steps in the first aspect of the embodiment of the present application.

[0013] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program for electronic data exchange, wherein the computer program enables a computer to execute part or all of the steps described in the first aspect of the embodiment of the present application.

[0014] In a fifth aspect, an embodiment of the present application provides a computer program product, wherein the computer program product includes a non-transitory computer-readable storage medium storing a computer program, and the computer program is operable to cause a computer to execute some or all of the steps described in the first aspect of the embodiment of the present application. The computer program product may be a software installation package.

[0015] The implementation of the embodiments of the present application has the following beneficial effects:

[0016] It can be seen that the verification method and related equipment for FPGA network cards described in the embodiments of the present application are applied to a verification system, which includes: a tester, an FPGA network card, and a UVM verification platform. The tester is communicated with the FPGA network card and the UVM verification platform, wherein the UVM verification platform includes: a PCAP packet capture component and a protocol analysis component. The PCAP packet capture component is used to perform PCAP packet capture to obtain a first network data message, the first network data message is analyzed to obtain target attribute information of the first network data message, and the protocol analysis component is used to detect whether the target attribute information meets a preset condition. When the target attribute information meets the preset condition, it is determined that the first network data message is abnormal; the first network data message is analyzed. Recover and obtain a normal second network data message, import the second network data message into the Ethernet interface in the verification environment through the UVM verification platform to send it to the FPGA network card for simulation; read the configuration data of the FPGA network card through the configuration script, import the configuration data into the verification environment, analyze the configuration data, and obtain the first analysis result; based on the first analysis result, distribute the configuration data to each module of the FPGA network card for simulation, analyze the network protocol message based on the PCAP packet capture component, completely replicate the protocol message on the board, and read the configuration stimulus in the boarding process through the boarding configuration script, input it into the verification environment for automatic simulation analysis, without the need for personnel to constrain and manage the stimulus, thereby realizing an automated simulation process and helping to improve verification efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 It is a schematic diagram of the architecture of a verification system for a verification method for an FPGA network card provided in an embodiment of the present application;

[0019] Figure 2 It is a flowchart of a verification method for an FPGA network card provided in an embodiment of the present application;

[0020] Figure 3 It is a structural schematic diagram of an electronic device provided in an embodiment of the present application;

[0021] Figure 4 This is a block diagram of the functional units of a verification device for an FPGA network card provided in an embodiment of the present application. DETAILED DESCRIPTION

[0022] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0023] The terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices.

[0024] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0025] In a specific implementation, the electronic device involved in the embodiments of the present application may be any electronic device that includes a universal verification methodology (UVM) verification platform, and the electronic device may include but is not limited to: smart phones, tablet computers, smart robots, smart projectors, conference equipment, vehicle-mounted equipment, wearable devices, servers, network equipment, computing devices or other processing devices connected to a wireless modem, as well as various forms of user equipment (UE), mobile stations (MS), terminal devices, etc., which are not limited here.

[0026] See also Figure 1 , Figure 1 The present invention is a schematic diagram of the architecture of a verification system for a verification method for an FPGA network card provided in an embodiment of the present application. The verification system includes: a tester, an FPGA network card UVM verification platform, and the tester is communicatively connected with the FPGA network card and the UVM verification platform, wherein the UVM verification platform includes: a PCAP packet capture component and a protocol analysis component.

[0027] Among them, the tester and FPGA network card are located in the upper board environment, the FPGA network card includes an eth interface and a host interface (Host), the UVM verification platform includes an Ethernet interface, a configuration script and an upper board configuration, and the configuration script and the upper board configuration can be used to obtain the configuration data of the FPGA network card.

[0028] Among them, the UVM verification platform belongs to the verification environment, the tester can be used to input test cases, and real Ethernet data is transmitted between the tester and the FPGA network card, and real Ethernet data is also transmitted between the UVM verification platform and the FPGA network card.

[0029] Based on the above verification system, the following functions can be realized:

[0030] Performing PCAP packet capture through the PCAP packet capture component to obtain a first network data message, and analyzing the first network data message to obtain target attribute information of the first network data message;

[0031] Detecting whether the target attribute information meets a preset condition through the protocol analysis component, and determining that the first network data message is abnormal when the target attribute information meets the preset condition; restoring the first network data message to obtain a normal second network data message;

[0032] The second network data message is imported into the Ethernet interface in the verification environment through the UVM verification platform to be sent to the FPGA network card for simulation; the configuration data of the FPGA network card is read through a configuration script, the configuration data is imported into the verification environment, the configuration data is analyzed to obtain a first analysis result; based on the first analysis result, the configuration data is distributed to each module of the FPGA network card for simulation.

[0033] In an embodiment of the present application, in order to solve the problem that the boarding process cannot be efficiently reproduced during the FPGA verification process, a tester is used in the board to send messages at the Ethernet entrance. By capturing packets through PCAP, the data can be saved as a file in the PCAP format. The protocol type of the message can be analyzed by importing the PCAP packet capture component, and then the message data is driven to the Ethernet interface and sent to the FPGA network card for simulation. At the same time, the configuration data of the FPGA is read through the configuration script, converted into a driving stimulus for the verification platform, and written into the FPGA network card through the backdoor method to simulate the real boarding scenario. The whole process can be executed automatically without the need for manual stimulus construction, which greatly simplifies the reproduction link of the boarding problem.

[0034] That is, in the embodiment of the present application, the PCAP-based packet capture component analyzes the network protocol messages and completely replicates the protocol messages on the board. At the same time, the configuration stimuli in the boarding process are read through the board configuration script and input into the verification environment for automatic simulation analysis. There is no need for personnel to constrain and manage the stimuli, thereby realizing an automated simulation process.

[0035] See also Figure 2 , Figure 2 : is a flow chart of a verification method for an FPGA network card provided in an embodiment of the present application. As shown in the figure, the method is applied to Figure 1 The verification system shown in the figure comprises: a tester, an FPGA network card, and a UVM verification platform, wherein the tester is communicatively connected with the FPGA network card and the UVM verification platform, wherein the UVM verification platform comprises: a PCAP packet capture component and a protocol analysis component; the verification method for the FPGA network card comprises:

[0036] 201. Perform PCAP packet capture through the PCAP packet capture component to obtain a first network data packet, analyze the first network data packet, and obtain target attribute information of the first network data packet.

[0037] In an embodiment of the present application, a test case can be input through a tester. During the test, PCAP packet capture can be performed through a PCAP packet capture component to obtain a first network data packet. The first network data packet can include data in a PCAP data format. The first network data packet can also be analyzed to obtain target attribute information of the first network data packet. The target attribute information can be represented by binary data.

[0038] In an embodiment of the present application, a PCAP packet capture component can be constructed, and the PCAP packet capture component can be used to analyze messages in the PCAP data format to obtain binary data.

[0039] Optionally, the target attribute information includes at least one of the following: message format and message length.

[0040] In an embodiment of the present application, the target attribute information may include a message format, or the target attribute information may include a message length, or the target attribute information may include a message format and a message length.

[0041] 202. Detect, through the protocol analysis component, whether the target attribute information satisfies a preset condition. When the target attribute information satisfies the preset condition, determine that an abnormality exists in the first network data packet; and restore the first network data packet to obtain a normal second network data packet.

[0042] In a specific implementation, the preset conditions can be preset or system defaulted, for example, the message length is not within a preset range, the message format is not a preset message format, etc. The preset range and preset message format can be preset or system defaulted.

[0043] In an embodiment of the present application, a protocol analysis component can be used to detect whether the target attribute information meets the preset conditions. When the target attribute information meets the preset conditions, it indicates that there is an abnormality in the first network data packet, and the first network data packet needs to be restored to obtain a normal second network data packet, thereby ensuring that the test can proceed smoothly.

[0044] In an embodiment of the present application, a protocol parsing component can be constructed to parse the data obtained by the PCAP packet capture component to determine whether there is a packet body error in the message. Since the captured message lengths may be unequal in the packet capture environment of the tester, it is necessary to parse the message, analyze the protocol header length and data length of the message, and then perform data recovery.

[0045] 203. Import the second network data message into the Ethernet interface in the verification environment through the UVM verification platform to send it to the FPGA network card for simulation; read the configuration data of the FPGA network card through a configuration script, import the configuration data into the verification environment, analyze the configuration data, and obtain a first analysis result; based on the first analysis result, distribute the configuration data to each module of the FPGA network card for simulation.

[0046] In an embodiment of the present application, the second network data message can be imported into the Ethernet interface in the verification environment through the UVM verification platform to be sent to the FPGA network card for simulation, and then the configuration data of the FPGA network card is read through the configuration script, and the configuration data is imported into the verification environment, and the configuration data is analyzed to obtain a first analysis result, which may include a mapping relationship between each data fragment and an address segment in the configuration data, and then the configuration data is distributed to each module of the FPGA network card for simulation based on the first analysis result to accelerate the simulation process. In a specific implementation, the analysis result can be imported into the platform in the form of a log, and the platform reads the log and enters the configuration table item and the register.

[0047] In the specific implementation, during the FPGA network card on-board process, the configuration data can be generated by a python script, and the software performs a data write operation based on the data generated by the script. The data can be printed to form a log log, and the simulation component of the UVM platform can analyze the log log and sample the data format, which is given in another file. Then, the configuration component of the UVM platform can be configured according to the data format, which can be specifically in the form of a backdoor, that is, the path of the backdoor is well associated during the simulation process. Among them, the configuration data can include at least one of the following: flow table, mac table, write address, etc., which are not limited here.

[0048] In the embodiment of the present application, the configuration stimulus of the FPGA network card can be captured into a file through a configuration script.

[0049] In the embodiment of the present application, a pcap packet capture and analysis component method is used to reproduce Ethernet network data, and a configuration analysis script is combined to achieve accurate configuration sampling and distribution. This method can efficiently and quickly reproduce problems in the FPGA network card boarding process, reduce manpower investment, and also obtain more accurate simulation results, effectively improving the efficiency of simulation problem discovery.

[0050] Optionally, the above step 203, analyzing the configuration data to obtain a first analysis result; and distributing the configuration data to each module of the FPGA network card for simulation based on the first analysis result, can be implemented as follows:

[0051] 31. Perform address and data analysis on the configuration data to obtain multiple data slices, each data slice corresponding to an address segment;

[0052] 32. Send the multiple data fragments to each module of the FPGA network card according to their corresponding address segments through backdoor configuration.

[0053] In an embodiment of the present application, address and data analysis can be performed on the configuration data to obtain multiple data slices, each data slice corresponding to an address segment, and then the multiple data slices can be sent to each module of the FPGA network card according to their respective corresponding address segments through backdoor configuration to accelerate the simulation process.

[0054] Specifically, the configuration parsing script can be used to parse the address and data of the captured configuration data, and then sent to each module of the FPGA network card through the backdoor configuration according to each address segment to speed up the simulation.

[0055] Optionally, the following steps may also be included:

[0056] A1. Obtain target test cases;

[0057] A2. Configure the PCAP data path of the target test case and the configuration data acquisition path;

[0058] A3. Simulate the target test case based on the configured PCAP data path and the configured configuration data acquisition path.

[0059] In the embodiment of the present application, the target test case can be any test case that needs to be tested. In the specific implementation, the target test case can be obtained, and then the PCAP data path and configuration data acquisition path of the target test case are configured. Then, the target test case is simulated based on the configured PCAP data path and the configured configuration data acquisition path, that is, the entire simulation process can be started as long as the PCAP data path and configuration acquisition path in the test case are rewritten. The automatic and rapid reproduction of the board problem is realized.

[0060] Optionally, the following steps may also be included:

[0061] B1. When the target attribute information does not meet the preset condition, determining that there is no abnormality in the first network data message;

[0062] B2. Importing the first network data message into the Ethernet interface in the verification environment through the UVM verification platform to send it to the FPGA network card for simulation; reading the configuration data of the FPGA network card through the configuration script, importing the configuration data into the verification environment, analyzing the configuration data, and obtaining a second analysis result; and distributing the configuration data to each module of the FPGA network card for simulation based on the second analysis result.

[0063] In an embodiment of the present application, when the target attribute information does not meet the preset conditions, it is determined that there is no abnormality in the first network data message, that is, the first network data message is normal, and then it can be directly simulated, that is, the first network data message is imported into the Ethernet interface in the verification environment through the UVM verification platform to send it to the FPGA network card for simulation; the configuration data of the FPGA network card is read through the configuration script, the configuration data is imported into the verification environment, the configuration data is analyzed, and a second analysis result is obtained. The second analysis result may include a mapping relationship between each data fragment and the address segment in the configuration data, and the configuration data is distributed to each module of the FPGA network card for simulation based on the second analysis result.

[0064] In a specific implementation, in an embodiment of the present application, address and data analysis can be performed on the configuration data to obtain multiple data slices, each data slice corresponding to an address segment, and then the multiple data slices can be sent to each module of the FPGA network card according to their respective corresponding address segments through backdoor configuration to accelerate the simulation process.

[0065] For example, in actual applications, in order to reproduce the problems that occur during the boarding process, the verification personnel need to construct similar message incentives and related scenario configuration incentives, and input them into the verification environment for simulation analysis; or, by PCAP packet capture to parse the network protocol message, manually operate the stimulus data to input the same message, for complex messages or when the number of messages is large, it will consume a lot of manpower. In the embodiment of the present application, in order to solve the problem that the boarding process cannot be efficiently reproduced during the FPGA verification process, a technical solution as shown in the figure below is proposed, the board uses a tester to send messages at the Ethernet entrance, and through PACP packet capture, the data can be saved as a file in PACP format, and the PCAP packet capture component can be imported to analyze the protocol type of the message, and then the message data is driven to the Ethernet interface and sent to the FPGA network card for simulation; at the same time, the configuration data of the FPGA network card is read through the configuration script, converted into the driving incentive of the verification platform, and written into the FPGA network card through the backdoor method to simulate the real boarding scenario. The whole process can be automatically executed, and there is no need for manual incentive construction, which greatly simplifies the reproduction link of the boarding problem.

[0066] In the specific implementation, when reproducing the board problem, in the embodiment of the present application, firstly, PCAP is used to capture packets to obtain network data packets, and then the captured PCAP data is analyzed by the PCAP packet capture component, and then the data format of PCAP is analyzed by the Ethernet message analysis component to see if it is wrong. If the packet length captured by PCAP is incorrect or the message format is incorrect, the message can be restored to normal message data through the Ethernet message analysis component and imported into the Ethernet interface in the verification environment, so as not to affect the test results; again, the configuration data in the FPGA network card is read through the configuration script, imported into the verification environment, the verification environment analyzes the configuration data, and then the configuration is sent to each module of the FPGA network card through the backdoor method to accelerate the simulation process; subsequently, as long as the PCAP data path and configuration acquisition path in the test case are rewritten, the entire simulation process can be started. The automatic and rapid reproduction of the board problem is realized, and then, the Ethernet data and chip configuration can be reproduced efficiently and accurately, and the automatic operation of the board problem reproduction is realized, the risk of human configuration is reduced, and a fast and efficient verification effect is obtained.

[0067] It can be seen that the verification method for FPGA network card described in the embodiment of the present application is applied to a verification system, which includes: a tester, an FPGA network card, and a UVM verification platform. The tester is communicatively connected with the FPGA network card and the UVM verification platform, wherein the UVM verification platform includes: a PCAP packet capture component and a protocol analysis component. The PCAP packet capture component is used to perform PCAP packet capture to obtain a first network data message, the first network data message is analyzed to obtain target attribute information of the first network data message, and the protocol analysis component is used to detect whether the target attribute information meets a preset condition. When the target attribute information meets the preset condition, it is determined that the first network data message is abnormal; the first network data message is restored, A normal second network data message is obtained, and the second network data message is imported into the Ethernet interface in the verification environment through the UVM verification platform to be sent to the FPGA network card for simulation; the configuration data of the FPGA network card is read through the configuration script, the configuration data is imported into the verification environment, the configuration data is analyzed, and a first analysis result is obtained; based on the first analysis result, the configuration data is distributed to each module of the FPGA network card for simulation, the network protocol message is analyzed based on the PCAP packet capture component, the protocol message of the board is completely reproduced, and at the same time, the configuration stimulus in the boarding process is read through the boarding configuration script, and the stimulus is input into the verification environment for automatic simulation analysis, without the need for personnel to constrain and manage the stimulus, so as to realize the automated simulation process and help improve the verification efficiency.

[0068] In accordance with the above embodiment, please refer to Figure 3 , Figure 3It is a structural schematic diagram of an electronic device provided by an embodiment of the present application. As shown in the figure, the electronic device includes a processor, a memory, a communication interface and one or more programs. The one or more programs are stored in the memory and are configured to be executed by the processor. The electronic device includes multiple network visualization ports. In the embodiment of the present application, the electronic device includes a UVM verification platform. The electronic device is applied to a verification system. The verification system includes: a tester, an FPGA network card, and a UVM verification platform. The tester is communicatively connected with the FPGA network card and the UVM verification platform. The UVM verification platform includes: a PCAP packet capture component and a protocol analysis component. The program includes instructions for executing the following steps:

[0069] Performing PCAP packet capture through the PCAP packet capture component to obtain a first network data message, and analyzing the first network data message to obtain target attribute information of the first network data message;

[0070] Detecting whether the target attribute information meets a preset condition through the protocol analysis component, and determining that the first network data message is abnormal when the target attribute information meets the preset condition; restoring the first network data message to obtain a normal second network data message;

[0071] The second network data message is imported into the Ethernet interface in the verification environment through the UVM verification platform to be sent to the FPGA network card for simulation; the configuration data of the FPGA network card is read through a configuration script, the configuration data is imported into the verification environment, the configuration data is analyzed to obtain a first analysis result; based on the first analysis result, the configuration data is distributed to each module of the FPGA network card for simulation.

[0072] Optionally, in the step of analyzing the configuration data to obtain a first analysis result; and distributing the configuration data to various modules of the FPGA network card for simulation based on the first analysis result, the program includes instructions for executing the following steps:

[0073] Performing address and data analysis on the configuration data to obtain a plurality of data slices, each data slice corresponding to an address segment;

[0074] The multiple data fragments are sent to each module of the FPGA network card according to their corresponding address segments by means of backdoor configuration.

[0075] Optionally, the target attribute information includes at least one of the following: message format and message length.

[0076] Optionally, the program further includes instructions for executing the following steps:

[0077] Get the target test case;

[0078] Configure the PCAP data path of the target test case and the configuration data acquisition path;

[0079] The target test case is simulated based on the configured PCAP data path and the configured configuration data acquisition path.

[0080] Optionally, the program further includes instructions for executing the following steps:

[0081] When the target attribute information does not meet the preset condition, determining that there is no abnormality in the first network data message;

[0082] The first network data message is imported into the Ethernet interface in the verification environment through the UVM verification platform to be sent to the FPGA network card for simulation; the configuration data of the FPGA network card is read through the configuration script, the configuration data is imported into the verification environment, the configuration data is analyzed to obtain a second analysis result; based on the second analysis result, the configuration data is distributed to each module of the FPGA network card for simulation.

[0083] It can be seen that the electronic device described in the embodiment of the present application is applied to a verification system, which includes: a tester, an FPGA network card, and a UVM verification platform. The tester is communicatively connected with the FPGA network card and the UVM verification platform, wherein the UVM verification platform includes: a PCAP packet capture component and a protocol analysis component. The PCAP packet capture component is used to perform PCAP packet capture to obtain a first network data message, the first network data message is analyzed to obtain target attribute information of the first network data message, and the protocol analysis component is used to detect whether the target attribute information meets a preset condition. When the target attribute information meets the preset condition, it is determined that the first network data message is abnormal; the first network data message is restored to obtain a normal The second network data message is imported into the Ethernet interface in the verification environment through the UVM verification platform to send it to the FPGA network card for simulation; the configuration data of the FPGA network card is read through the configuration script, the configuration data is imported into the verification environment, the configuration data is analyzed, and the first analysis result is obtained; based on the first analysis result, the configuration data is distributed to each module of the FPGA network card for simulation, the network protocol message is analyzed based on the PCAP packet capture component, the protocol message of the board is completely reproduced, and the configuration stimulus in the boarding process is read through the boarding configuration script, and the stimulus is input into the verification environment for automatic simulation analysis, without the need for personnel to constrain and manage the stimulus, so as to realize the automated simulation process and help improve the verification efficiency.

[0084] Figure 4 This is a functional unit block diagram of a verification device 400 for an FPGA network card involved in an embodiment of the present application. The device 400 is applied to a verification system, and the verification system includes: a tester, an FPGA network card, and a UVM verification platform. The tester is in communication connection with the FPGA network card and the UVM verification platform, wherein the UVM verification platform includes: a PCAP packet capture component and a protocol analysis component; the device 400 includes: a data analysis unit 401, a data recovery unit 402, and a verification unit 403, wherein:

[0085] The data analysis unit 401 is used to perform PCAP packet capture through the PCAP packet capture component to obtain a first network data message, analyze the first network data message, and obtain target attribute information of the first network data message;

[0086] The data recovery unit 402 is used to detect whether the target attribute information meets the preset condition through the protocol analysis component, and when the target attribute information meets the preset condition, determine that the first network data message is abnormal; recover the first network data message to obtain a normal second network data message;

[0087] The verification unit 403 is used to import the second network data message into the Ethernet interface in the verification environment through the UVM verification platform to send it to the FPGA network card for simulation; read the configuration data of the FPGA network card through a configuration script, import the configuration data into the verification environment, analyze the configuration data, and obtain a first analysis result; based on the first analysis result, distribute the configuration data to each module of the FPGA network card for simulation.

[0088] Optionally, in the step of analyzing the configuration data to obtain a first analysis result; and distributing the configuration data to various modules of the FPGA network card for simulation based on the first analysis result, the verification unit 403 is specifically used to:

[0089] Performing address and data analysis on the configuration data to obtain a plurality of data slices, each data slice corresponding to an address segment;

[0090] The multiple data fragments are sent to each module of the FPGA network card according to their corresponding address segments by means of backdoor configuration.

[0091] Optionally, the target attribute information includes at least one of the following: message format and message length.

[0092] Optionally, the device 400 is further specifically used for:

[0093] Get the target test case;

[0094] Configure the PCAP data path of the target test case and the configuration data acquisition path;

[0095] The target test case is simulated based on the configured PCAP data path and the configured configuration data acquisition path.

[0096] Optionally, the device 400 is further specifically used for:

[0097] When the target attribute information does not meet the preset condition, determining that there is no abnormality in the first network data message;

[0098] The first network data message is imported into the Ethernet interface in the verification environment through the UVM verification platform to be sent to the FPGA network card for simulation; the configuration data of the FPGA network card is read through the configuration script, the configuration data is imported into the verification environment, the configuration data is analyzed to obtain a second analysis result; based on the second analysis result, the configuration data is distributed to each module of the FPGA network card for simulation.

[0099] It can be seen that the verification device for FPGA network card described in the embodiment of the present application is applied to the verification system, which includes: a tester, an FPGA network card, and a UVM verification platform. The tester is communicatively connected with the FPGA network card and the UVM verification platform, wherein the UVM verification platform includes: a PCAP packet capture component and a protocol analysis component. The PCAP packet capture component is used to perform PCAP packet capture to obtain a first network data message, the first network data message is analyzed to obtain target attribute information of the first network data message, and the protocol analysis component is used to detect whether the target attribute information meets a preset condition. When the target attribute information meets the preset condition, it is determined that the first network data message is abnormal; the first network data message is restored, A normal second network data message is obtained, and the second network data message is imported into the Ethernet interface in the verification environment through the UVM verification platform to be sent to the FPGA network card for simulation; the configuration data of the FPGA network card is read through the configuration script, the configuration data is imported into the verification environment, the configuration data is analyzed, and a first analysis result is obtained; based on the first analysis result, the configuration data is distributed to each module of the FPGA network card for simulation, the network protocol message is analyzed based on the PCAP packet capture component, the protocol message of the board is completely reproduced, and at the same time, the configuration stimulus in the boarding process is read through the boarding configuration script, and the stimulus is input into the verification environment for automatic simulation analysis, without the need for personnel to constrain and manage the stimulus, so as to realize the automated simulation process and help improve the verification efficiency.

[0100] It can be understood that the functions of each program module of the verification device for FPGA network card in this embodiment can be specifically implemented according to the method in the above method embodiment, and its specific implementation process can refer to the relevant description of the above method embodiment, which will not be repeated here.

[0101] An embodiment of the present application also provides a computer storage medium, wherein the computer storage medium stores a computer program for electronic data exchange, wherein the computer program enables a computer to execute part or all of the steps of any method recorded in the above method embodiments, and the above computer includes an electronic device.

[0102] The embodiment of the present application also provides a computer program product, the computer program product includes a non-transitory computer-readable storage medium storing a computer program, the computer program is operable to cause a computer to execute some or all of the steps of any method described in the method embodiment. The computer program product may be a software installation package, and the computer includes an electronic device.

[0103] It should be noted that, for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the described order of actions, because according to the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present application.

[0104] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0105] In the several embodiments provided in the present application, it should be understood that the disclosed device can be implemented in other ways. For example, the device embodiments described above are only schematic, such as the division of the above-mentioned units, which is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, and the indirect coupling or communication connection of devices or units can be electrical or other forms.

[0106] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0107] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0108] If the above-mentioned integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a memory, including a number of instructions to enable a computer device (which can be a personal computer, server or electronic device, etc.) to perform all or part of the steps of the above-mentioned methods of each embodiment of the present application. The aforementioned memory includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, disk or optical disk and other media that can store program codes.

[0109] A person skilled in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable memory, and the memory can include: a flash drive, a read-only memory (English: Read-Only Memory, abbreviated as: ROM), a random access memory (English: Random Access Memory, abbreviated as: RAM), a magnetic disk or an optical disk, etc.

[0110] The embodiments of the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. At the same time, for general technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A verification method for an FPGA network card, characterized in that: The method is applied to a verification system, which includes: a tester, an FPGA network card, and a UVM verification platform, wherein the tester is communicatively connected with the FPGA network card and the UVM verification platform, wherein the UVM verification platform includes: a PCAP packet capture component and a protocol analysis component; Performing PCAP packet capture through the PCAP packet capture component to obtain a first network data message, analyzing the first network data message to obtain target attribute information of the first network data message; the target attribute information is represented by binary data; the target attribute information includes at least one of the following: message format, message length; Detecting whether the target attribute information meets a preset condition through the protocol analysis component, and determining that the first network data message is abnormal when the target attribute information meets the preset condition; restoring the first network data message to obtain a normal second network data message; The second network data message is imported into the Ethernet interface in the verification environment through the UVM verification platform to be sent to the FPGA network card for simulation; the configuration data of the FPGA network card is read through a configuration script, the configuration data is imported into the verification environment, the configuration data is analyzed to obtain a first analysis result; based on the first analysis result, the configuration data is distributed to each module of the FPGA network card for simulation.

2. The method according to claim 1, characterized in that The step of analyzing the configuration data to obtain a first analysis result; and distributing the configuration data to various modules of the FPGA network card for simulation based on the first analysis result, includes: Performing address and data analysis on the configuration data to obtain a plurality of data slices, each data slice corresponding to an address segment; The multiple data fragments are sent to each module of the FPGA network card according to their corresponding address segments by means of backdoor configuration.

3. The method according to claim 1 or 2, characterized in that: The target attribute information includes at least one of the following: message format and message length.

4. The method according to claim 1 or 2, characterized in that: The method further comprises: Get the target test case; Configure the PCAP data path of the target test case and the configuration data acquisition path; The target test case is simulated based on the configured PCAP data path and the configured configuration data acquisition path.

5. The method according to claim 1 or 2, characterized in that: The method further comprises: When the target attribute information does not meet the preset condition, determining that there is no abnormality in the first network data message; The first network data message is imported into the Ethernet interface in the verification environment through the UVM verification platform to be sent to the FPGA network card for simulation; the configuration data of the FPGA network card is read through the configuration script, the configuration data is imported into the verification environment, the configuration data is analyzed to obtain a second analysis result; based on the second analysis result, the configuration data is distributed to each module of the FPGA network card for simulation.

6. A verification device for an FPGA network card, characterized in that: The device is applied to a verification system, which includes: a tester, an FPGA network card, and a UVM verification platform. The tester is in communication connection with the FPGA network card and the UVM verification platform, wherein the UVM verification platform includes: a PCAP packet capture component and a protocol analysis component; the device includes: a data analysis unit, a data recovery unit and a verification unit, wherein: The data analysis unit is used to perform PCAP packet capture through the PCAP packet capture component to obtain a first network data message, analyze the first network data message, and obtain target attribute information of the first network data message; the target attribute information is represented by binary data; the target attribute information includes at least one of the following: message format, message length; The data recovery unit is used to detect whether the target attribute information meets the preset condition through the protocol analysis component, and when the target attribute information meets the preset condition, determine that the first network data message is abnormal; recover the first network data message to obtain a normal second network data message; The verification unit is used to import the second network data message into the Ethernet interface in the verification environment through the UVM verification platform to send it to the FPGA network card for simulation; read the configuration data of the FPGA network card through a configuration script, import the configuration data into the verification environment, analyze the configuration data, and obtain a first analysis result; based on the first analysis result, distribute the configuration data to each module of the FPGA network card for simulation.

7. The device according to claim 6, characterized in that In the aspect of analyzing the configuration data to obtain a first analysis result; and distributing the configuration data to various modules of the FPGA network card for simulation based on the first analysis result, the verification unit is specifically used for: Performing address and data analysis on the configuration data to obtain a plurality of data slices, each data slice corresponding to an address segment; The multiple data fragments are sent to each module of the FPGA network card according to their corresponding address segments by means of backdoor configuration.

8. The device according to claim 6 or 7, characterized in that The target attribute information includes at least one of the following: message format and message length.

9. An electronic device, characterized in that: The method comprises a processor and a memory, wherein the memory is used to store one or more programs and is configured to be executed by the processor, wherein the program comprises instructions for executing the steps in the method according to any one of claims 1 to 5.

10. A computer-readable storage medium, characterized in that: A computer program for electronic data exchange is stored, wherein the computer program enables a computer to execute the method according to any one of claims 1 to 5.

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