An on-chip integrated transient-enhanced LED driving circuit

Abstract

The application discloses a kind of on-chip integrated transient enhanced LED drive circuit, belong to power supply technical field.The circuit is applied to optical isolation system, optical isolation system utilizes light emitting diode (LED) and photodiode (PD) to realize electrical isolation, control end generates signal control LED light emitting, receiving end utilizes PD and converts optical signal into current signal, and voltage signal is amplified by transimpedance amplifier (TIA), and subsequent module processing.Due to the existence of large parasitic junction capacitor of LED, in the process of controlling switch LED, the charge and discharge of parasitic junction can affect the opening speed of LED, and further affect the overall transmission delay of optical isolation system.A kind of transient enhanced LED drive circuit proposed in this paper provides transient current in the moment of opening LED, accelerates the opening of LED.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of power supply, and particularly relates to an on-chip integrated transient enhancement type LED driving circuit. BACKGROUND

[0002] The optical isolation system is widely applied in the gate driving circuit, electrical isolation is realized by using a light emitting diode (LED) and a photodiode (PD), a signal is generated at the control end to control the LED to emit light, the receiving end converts the optical signal into a current signal by using the PD, the current signal is amplified into a voltage signal by a transimpedance amplifier (TIA), and the voltage signal is processed by a subsequent module. Since the LED has a large parasitic junction capacitor, during the process of controlling the switch LED, the charging and discharging of the parasitic junction will affect the opening speed of the LED, and further affect the overall transmission delay of the gate driving. SUMMARY

[0003] The application aims at the characteristics that the external LED has a large parasitic junction capacitor, and provides an on-chip integrated transient enhancement type LED driving circuit, which is suitable for the transmitting end of an optical isolation chip. The circuit has a stable output current, and has a large driving current at the moment of opening, so that the LED can be quickly opened, and the transmission delay of the whole system is reduced.

[0004] The technical scheme of the application is as follows:

[0005] An LED driving circuit with transient enhancement, as shown in FIG. 1, comprises a first capacitor, a first inverter, a second inverter, a first NOR gate, a first comparator, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a first bias current source and a second bias current source. Figure 2 The input of the first inverter is the input CTL of the driving circuit, and the output of the first inverter is connected to the gate of the first PMOS transistor, the gate of the first NMOS transistor and the gate of the sixth PMOS transistor.

[0006] One input end of the first NOR gate is the input of the driving circuit, and the other input end is connected to the output of the first comparator, and the output end of the first NOR gate is connected to the input end of the second inverter; the positive input end of the first comparator is connected to one end of the first capacitor, the drain of the second PMOS transistor and the source of the first PMOS transistor, and the negative input end of the first comparator is connected to a reference voltage; the output end of the second inverter is connected to the gate of the second PMOS transistor; and the other end of the first capacitor is connected to the ground.

[0007]

[0008] ​The source of the second PMOS tube is connected to the drain of the third PMOS tube, the source of the third PMOS tube is connected to a power supply, and the gate of the third PMOS tube is connected to the gate of the fourth PMOS tube, the gate and the drain of the fifth PMOS tube, and the drain of the fourth NMOS tube;

[0009] The source of the fourth PMOS tube is connected to a power supply, and the drain of the fourth PMOS tube is connected to the source of the sixth PMOS tube; the drain of the sixth PMOS tube is connected to the drain of the first PMOS tube and the drain of the first NMOS tube, and serves as an output terminal of the driving circuit; and the source of the first NMOS tube is connected to ground;

[0010] The gate of the fourth NMOS tube is connected to the gate of the third NMOS tube, the gate and the drain of the second NMOS tube, and one end of the second bias current source; and the source of the fourth NMOS tube is connected to the drain of the sixth NMOS tube;

[0011] The gate of the sixth NMOS tube is connected to the gate of the fifth NMOS tube, one end of the first bias current source, and the drain of the third NMOS tube;

[0012] The other end of the first bias current source and the other end of the second bias current source are connected to a power supply;

[0013] The drain of the fifth NMOS tube is connected to the source of the third NMOS tube; and the source of the fifth NMOS tube, the source of the sixth NMOS tube, and the source of the second NMOS tube are connected to ground.

[0014] The beneficial effects of the present application are as follows: when the LED is turned off, the capacitor is charged to store electric charge, and when the voltage on the capacitor reaches a set value, the charging is stopped. When the LED is turned on, the electric charge on the capacitor is quickly discharged to provide a large instantaneous current to charge the parasitic capacitor of the LED, so that the LED can quickly reach the turn-on voltage. Through the improvement, the turn-on speed of the LED is improved, and the transmission delay of the entire system is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 The schematic diagram of the logic block diagram for the on-chip integrated LED driving circuit is shown.

[0016] Figure 2 The circuit structure diagram of the on-chip integrated transient enhancement type LED driving circuit is shown.

[0017] Figure 3 The current path diagram of the on-chip integrated transient enhancement type LED driving circuit in different working states is shown.

[0018] Figure 4 The working waveform diagram of the transient simulation of the on-chip integrated transient enhancement type LED driving circuit is shown.

[0019] Figure 5 Fig. 1 is a waveform diagram of the LED start-up delay simulation waveform with transient enhancement function, and Fig. 2 is a waveform diagram of the LED start-up delay simulation waveform without transient enhancement function. DETAILED DESCRIPTION

[0020] The technical solutions of the present application will be described in detail below with reference to the accompanying drawings:

[0021] Figure 2 Fig. 1 is a circuit structure of the on-chip integrated transient enhancement type LED driving circuit of the present application. The second NMOS, the third NMOS, the fourth NMOS, the fifth NMOS and the sixth NMOS constitute a wide-swing cascode current mirror, and the first bias current source and the second bias current source are derived from a reference current source inside the system. The second NMOS is diode-connected to provide a bias voltage for the third NMOS and the fourth NMOS. The current flowing through the second NMOS can be described as:

[0022]

[0023] The current flowing through the fifth NMOS can be described as:

[0024]

[0025] In the present application, I MN2 =I MN5 , the second NMOS, the third NMOS and the fourth NMOS are completely matched, and the fifth NMOS and the sixth NMOS are completely matched, so the width-length ratio of the fifth NMOS is required to be 4 times that of the second NMOS to meet the normal working state of the current mirror. The minimum voltage at the drain of the fourth NMOS is twice the overdrive voltage for the normal working of the fifth NMOS.

[0026] At the same time, the cascode structure improves the output impedance of the current mirror, and the equivalent impedance at the drain of the fourth NMOS is:

[0027]

[0028] Improving the output impedance of the current mirror can reduce the influence of the switching process of the LED driving part on the current of the sixth NMOS, ensure the stability of the output current of the current mirror, and further ensure the accuracy and stability of the output current of the LED driving.

[0029] In the present application, there are two current paths for driving the LED, one of which is composed of the fourth PMOS and the sixth PMOS, and the other of which is composed of the first PMOS, the second PMOS, the third PMOS and the first capacitor C1. Now, the working principle of the LED driving circuit will be described in detail with reference to the accompanying drawings: Figure 3It is explained that the first input is the reference voltage VREF generated inside the system, the second input is the control signal CTL, CTL is an external input, and the PWM signal obtained by internal shaping is output. When CTL is low, the output of the first inverter is high, and the first PMOS and the sixth PMOS are controlled to be in the off state, at this time the LED is off, recorded as LED OFF state. At this time, the voltage at the first end of the first capacitor is lower than VREF, and the output of the first comparator is low. The output of the first comparator and the CTL signal are output to the low level through the first NOR gate and the second inverter, and the second PMOS is controlled to be in the on state. The current flows through the third PMOS and the second PMOS to charge the first capacitor. When the voltage at the first end of the first capacitor exceeds the reference voltage VREF, the output of the first comparator is high, and the output of the first comparator is high through the first NOR gate and the second inverter, and the second PMOS is controlled to be in the off state. When CTL changes from low to high, the output of the first inverter is low, and the first PMOS and the sixth PMOS are controlled to be in the on state. At the moment of opening, the charge stored in the first capacitor charges the parasitic capacitor of the LED quickly through the first PMOS, and at the same time the stable output current path of the fourth PMOS and the sixth PMOS is established. When the voltage of the first capacitor and the parasitic capacitor of the LED reaches balance, the first capacitor no longer continues to discharge, and at this time the driving current of the LED is provided by the current path of the fourth PMOS and the sixth PMOS. After the first capacitor is discharged, the voltage at the first end of the first capacitor is lower than the reference voltage VREF, and the output of the first comparator changes from high to low. When CTL changes from high to low, the first NMOS is turned on and the sixth PMOS is turned off, and the point between the two ends of the LED is pulled to the ground, completing the closing of the LED and entering the next cycle.

[0030] As Figure 4 shown, it is a waveform diagram in the process of LED switching, wherein C_charge is the current waveform for charging the first capacitor, V_C is the voltage waveform at the first end of the first capacitor, and after the LED is turned on, the voltage at the first end of the first capacitor decreases from 2.6V to 1.8V. The instantaneous current for charging the first capacitor is 22.8mA after the LED is turned off, and the current decreases to 0 after the charging is completed. I_LED_DRIVER is the output current of the LED driver, and V_LED_PLUS is the terminal voltage of the LED. At the moment of turning on the LED, the LED driver module provides an output current of 35mA, and after the first capacitor is discharged, the current decreases to a stable output value of 12mA.

[0031] As Figure 5As shown, the delay waveform chart of adding LED drive transient enhancement function and not adding transient enhancement function, in the LED drive circuit adding transient enhancement function, the opening delay of LED is 3.6ns, in the LED drive circuit not adding transient enhancement function, the opening delay of LED is 4.6ns, the delay promotion effect is 21.74%.

[0032] In conclusion, the on-chip integrated transient enhancement type LED drive circuit can effectively reduce the transmission delay of opening LED in the optical isolation system. By storing charges and releasing the charges after opening, the LED drive is quickly driven into the opening state, which effectively reduces the opening delay of LED. At the same time, the reference voltage VREF can be flexibly adjusted according to different models of LED to achieve the function of quickly opening LED while extending the service life of LED as much as possible within the range that LED can tolerate.

Claims

1. A transient enhancement LED driving circuit, characterized in that, It includes a first capacitor, a first inverter, a second inverter, a first NOR gate, a first comparator, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a first bias current source, and a second bias current source; wherein, The input of the first inverter is the input of the drive circuit, and the output of the first inverter is connected to the gate of the first PMOS transistor, the gate of the first NMOS transistor, and the gate of the sixth PMOS transistor. One input of the first NOR gate is connected to the input of the first inverter, and the other input of the first NOR gate is connected to the output of the first comparator. The output of the first NOR gate is connected to the input of the second inverter. The positive input of the first comparator is connected to one end of the first capacitor, the drain of the second PMOS transistor, and the source of the first PMOS transistor. The negative input of the first comparator is connected to the reference voltage. The output of the second inverter is connected to the gate of the second PMOS transistor. The other end of the first capacitor is grounded. The source of the second PMOS transistor is connected to the drain of the third PMOS transistor, the source of the third PMOS transistor is connected to the power supply, and the gate of the third PMOS transistor is connected to the gate of the fourth PMOS transistor, the gate and drain of the fifth PMOS transistor, and the drain of the fourth NMOS transistor. The source of the fourth PMOS transistor is connected to the power supply, and its drain is connected to the source of the sixth PMOS transistor; the drain of the sixth PMOS transistor is connected to the drain of the first PMOS transistor and the drain of the first NMOS transistor, and serves as the output terminal of the drive circuit; the source of the first NMOS transistor is grounded. The gate of the fourth NMOS transistor is connected to the gate of the third NMOS transistor, the gate and drain of the second NMOS transistor, and one end of the second bias current source; the source of the fourth NMOS transistor is connected to the drain of the sixth NMOS transistor. The gate of the sixth NMOS transistor is connected to the gate of the fifth NMOS transistor, one end of the first bias current source, and the drain of the third NMOS transistor; The other end of the first bias current source and the other end of the second bias current source are connected to the power supply. The drain of the fifth NMOS transistor is connected to the source of the third NMOS transistor, and the sources of the fifth NMOS transistor, the sixth NMOS transistor, and the second NMOS transistor are grounded.

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