Method for controlling microsecond level latency of interface conversion between reflection memory network node and electrical signal

Abstract

The application provides a microsecond-level time delay control method for converting the interface between a reflective memory network node and an electrical signal, which comprises the following steps: step one: taking FPGA as a control core platform to build a hardware system combined with a motherboard and multiple daughter boards; step two: each channel of the motherboard enters an initial state of a finite state machine, each daughter board completes basic configuration and opens a data receiving and transmitting channel, and starts waiting for data; step three: when the length of the data received by the channel of the daughter board meets a preset value, the received data is converted into a GTX frame, the data is sent to the FPGA of the motherboard through the GTX, the data is encoded into reflective memory network data, and then the data is sent to the reflective memory network through an optical fiber interface; step four: the reflective memory network sends data to a specified channel of the daughter board, and the FPGA of the motherboard writes the data into a sending FIFO of the corresponding channel of the FPGA of the motherboard after judging the data. The application can solve the problems of long-distance data transmission and real-time performance of a comprehensive multiple electrical signal interface in a semi-physical simulation system.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of reflective memory network, in particular to a microsecond-level delay control method for interface conversion between a reflective memory network node and an electrical signal. BACKGROUND

[0002] With the development of computer technology, the scale and complexity of computer simulation models are becoming larger and larger. In the case of limited cost, using the traditional centralized architecture system for simulation, the resources are scarce, the response speed is slow, and the service is imperfect. Especially in the simulation task of time and space inconsistency, the single node communication and limited computing capacity of the centralized architecture system make it difficult to achieve high real-time simulation effect, and it cannot well complete complex simulation tasks. In order to solve the above problems, the distributed simulation technology architecture emerges as the times require. It divides the computing and communication tasks of the centralized architecture into independent modules interconnected with each other. Each simulation node can be distributed in different locations and can run interactively or independently. It reduces the cost while meeting the need for high real-time performance of complex simulation tasks, and also has high flexibility and concurrency. Each simulation node can freely participate in system work and exit the system.

[0003] Reflective memory network is widely used in semi-physical distributed simulation technology. After years of development, it has become mature and has many advantages: the entire transmission mechanism is automatically implemented by hardware, software developers do not need to understand the complex data transmission process, and only need to read and write operations on the local memory; it is independent of the operating system and processor of the device; it has stable data transmission and high real-time performance.

[0004] However, with the wide application of simulation technology, the semi-physical distributed simulation system also encounters two significant problems in practical application:

[0005] They are often distributed in different spatial locations, and even the simulation nodes can be up to 10 kilometers apart. At this time, the data transmission delay will seriously affect the performance of the simulation system; the communication interfaces of semi-physical simulation models and simulation node devices are various, such as digital IO, LVDS, ARINC429, RS422, RS232, etc. The traditional method of integrating multiple communication interfaces is to use a computer to receive data from each communication interface, and then write the data into the memory through software scheduling, or send the data in the reflective memory network to each communication interface through computer software scheduling. Based on the existing computer performance, the traditional communication interface integration method has high delay, the system real-time performance decreases, and it cannot meet the demand for strong real-time performance. Moreover, the running status of the node device system directly affects the stability of the entire simulation system, which has high risk.

[0006] The above two problems seriously affect the development of the reflective memory network in the semi-physical simulation system, and in order to further adapt to new needs, a new method needs to be designed to solve the above problems. SUMMARY

[0007] In order to solve the problems of long-distance data transmission and real-time of multiple electrical signal interfaces in the semi-physical simulation system, the application provides a microsecond-level time delay control method for converting the reflective memory network node and the electrical signal interface.

[0008] The microsecond-level time delay control method for converting the reflective memory network node and the electrical signal interface provided by the application is as follows:

[0009] (S1) Taking FPGA as a control core platform, a hardware system composed of a mother board and multiple daughter boards is constructed; wherein the whole system is a node of the reflective memory network, the mother board is responsible for analyzing the reflective memory network protocol, processing the local data frame and communicating with the daughter boards; the daughter boards include LVDS daughter boards, ARINC429 daughter boards, RS422 daughter boards, RS232 daughter boards, 1553B daughter boards, A / D acquisition and D\A output daughter boards, and digital IO daughter boards, which are used for realizing the transceiving control of each electrical signal channel and the communication with the mother board, the daughter boards and the mother board are physically connected through an XMC interface, and an Aurora high-speed serial bus based on GTX is selected for communication.

[0010] (S2) After the system is powered on, initialization is completed: each channel of the mother board enters the initial state of the finite state machine, each daughter board completes the basic configuration and opens the data transceiving channel, and starts to wait for data.

[0011] (S3) Data receiving: after the data length received by the channel of the daughter board meets the preset value, the received data is converted into a GTX frame, the data is sent to the FPGA of the mother board through GTX, the data is encoded into reflective memory network data, and then the data is sent to the reflective memory network through the optical fiber interface.

[0012] (S4) Data sending: the reflective memory network sends data to the specified channel of the daughter board, the mother board FPGA judges the data and writes the data into the sending FIFO of the corresponding channel of the mother board FPGA, when the data length reaches the preset value, the mother board FPGA converts the data into a GTX frame, sends the data to the corresponding daughter board through the GTX channel, and then the daughter board processes and sends out the data.

[0013] Preferably, the multiple channels refer to multiple electrical signal channels, including digital IO, LVDS, ARINC429, RS422, RS232, 1553B, A / D acquisition interface and D\A output interface, each daughter board selects an FPGA chip as an operation processing platform of the data transceiving interface, and Verilog HDL is selected as a programming language.

[0014] Preferably, the physical channel between the mother board and the daughter board adopts 1 pair of GTX signal lines, 2 pairs of standby LVDS signal lines and 9 single-ended signal lines, the 9 single-ended signal lines including 2 status indication signal lines, 1 reset signal line and 6 standby single-ended signal lines. When the mother-daughter board communicates, the status signal line is read first to check the status of the other party, and when it is idle, the communication is carried out; otherwise, it waits.

[0015] Preferably, the running state of the mother board is realized based on a finite state machine. When there is no data transmission and reception, the whole hardware system is in an initial state, waiting for data to arrive; when there is data transmission and reception, the mother board enters a data receiving state or a data sending state according to the demand and the priority level; when the data receiving or data sending is completed, it returns to the initial state and continues to wait for data.

[0016] Preferably, the GTX frame for the communication between the mother board and the daughter board is of a fixed format, and when the format does not conform, the frame is discarded; every time the mother board sends a GTX frame to the daughter board, the daughter board returns a GTX return frame.

[0017] Preferably, the time delay of the computing system is from the complete reception of a data packet from a daughter board through the electrical signal channel to the complete sending through the reflective memory network interface.

[0018] Preferably, when a certain channel has data receiving and data sending at the same time, the mother board enters a state with a higher priority according to the priority set in advance according to the demand, that is, if the data receiving priority is higher than the data sending priority, it enters the data receiving state first, and then enters the data sending state after completion; otherwise, it enters the data sending state first, and then enters the data receiving state after completion.

[0019] Preferably, the first bit of the GTX frame of the fixed format is a fixed 32-bit frame header; the second bit is a 16-bit CMD command word; the third bit is a 16-bit data length frame; the fourth bit is a Data frame with a length determined by the data length frame; the fifth bit is a 32-bit check bit; and the sixth bit is a fixed 32-bit frame tail.

[0020] Preferably, the CMD command word of the GTX return frame includes an operation command and an operation register address.

[0021] Preferably, the CMD command word of the GTX frame includes a read-write command, a number of invalid data bits and a register address for command operation.

[0022] Compared with the prior art, the present application has the beneficial effects that: the reflective memory network and the electrical signal interface conversion system are embedded in the reflective memory network node, optical fiber is directly used for data transmission, and the transmission distance can reach 10 km; the communication between the reflective memory network node and the electrical signal interface is realized in the hardware mode, and has strong real-time performance, and the minimum time delay is in the microsecond level; the FPGA is programmed through the Verilog HDL language, and has high flexibility: on the basis of meeting strong real-time performance, the protocol of the electrical signal interface of each sub-board can be customized according to different application occasions and different requirements; the self-defined GTX frame protocol realizes high reliability of the communication between the sub-board and the mother board on the basis of reducing the time delay as much as possible; the entire hardware architecture is formed in the sub-board splicing mode, and has high expandability in the physical structure. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 is a reflective memory network environment schematic diagram of the embodiment of the present application.

[0024] Figure 2 is a reflective memory network node and electrical signal interface conversion system hardware schematic diagram of the embodiment of the present application.

[0025] Figure 3 is a mother board program block diagram.

[0026] Figure 4 is a finite state machine schematic diagram of the mother board program running.

[0027] Figure 5 is a sub-board program block diagram.

[0028] Figure 6 is a GTX frame format schematic diagram of the communication between the mother board and the sub-board.

[0029] Figure 7 is a 16-bit CMD command word component in the GTX frame.

[0030] Figure 8 is a 16-bit CMD command word component in the GTX return frame.

[0031] Figure 9 is a screen shot of the system transmission time delay tested by using an oscilloscope. DETAILED DESCRIPTION

[0032] In order to make the purposes, technical solutions and advantages of the present application more clear, the present application is further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, and are not used to limit the present application.

[0033] A reflective memory network node and electrical signal interface conversion microsecond level time delay control method is as follows:

[0034] (S1) Using FPGA as the core control platform, a hardware system combining a motherboard and various daughterboards is constructed.

[0035] Please see Figure 1 This embodiment operates in the following environment: Figure 1 The ring-shaped reflective memory network for the hardware-in-the-loop simulation system shown has a total of k+3 devices (k is a positive integer, theoretically no greater than 253) as reflective memory network nodes. "Node 2" in the figure is the "combination system of the motherboard and daughterboard," which is the system for converting reflective memory network nodes into electrical signal interfaces. The other nodes are also devices used in hardware-in-the-loop simulation systems and are irrelevant to this invention, therefore they will not be described in detail.

[0036] Please see Figure 2 This embodiment provides a hardware platform for a reflective memory network node and electrical signal interface conversion system. The left side of the dashed line represents the main components of the motherboard, and the right side represents the four daughter boards and their main components. The motherboard uses a Xilinx FPGA (model SPARTAN6 XC7K325T-FFG900C) as its control core platform, while the daughter boards use a Xilinx FPGA chip (model SPARTAN6 XC6SLX45T-2CSG324I) as their control core platform, constructing a hardware system combining the motherboard and the four daughter boards. The entire system is a node in the reflective memory network. The motherboard is responsible for parsing the reflective memory network protocol, processing local data frames, and communicating with the daughter boards. The daughter boards are responsible for controlling the transmission and reception of each electrical signal channel and communicating with the motherboard. The daughter boards and motherboard are physically connected via an XMC interface, using a GTX-based Aurora high-speed serial bus for communication.

[0037] The SFP conversion circuit and high-speed SFP interface together form a fiber optic access channel. This channel connects the reflective memory network node and the electrical signal interface conversion system to the reflective memory network, making it a node within the network. The motherboard integrates one electrical signal channel, a 1553B channel, consisting of a 1553B conversion circuit and an interface to the simulation node. Crystal oscillator A is a 156.25MHz active crystal oscillator, and crystal oscillator B is a 100MHz active crystal oscillator, providing external clocks for the FPGA chip. External RAM provides storage space for the motherboard FPGA program execution; the FPGA writes or reads data from it. The power module provides a reliable power supply for the entire system. The daughterboard power supply is connected to the motherboard via the XMC interface; the power cable connection diagram is omitted in the figure.

[0038] The hardware structure of each sub-board is similar, and each sub-board adopts the same XMC interface, FPGA chip and simulation node interface. The difference between the sub-boards is the conversion circuit of each sub-board, but the function thereof is to convert the corresponding electrical signal channel into an electrical signal that can be processed by the FPGA chip. The four sub-boards provide six electrical signal channels, which are as follows: the sub-board 1 is an LVDS and digital IO sub-board, and provides two electrical signal channels of LVDS and digital IO; the sub-board 2 is an ARINC429 sub-board, and provides an ARINC429 electrical signal channel; the sub-board 3 is an RS422 sub-board, and provides an RS422 electrical signal channel; and the sub-board 4 is an A / D acquisition and D / A output sub-board, and provides two electrical signal channels of A / D acquisition and D / A output. The physical channels of the mother board and each sub-board adopt one pair of GTX signal lines, two pairs of standby LVDS signal lines and nine single-ended signal lines. The nine single-ended signal lines include two state indication signal lines, one reset signal line and six standby single-ended signal lines. Therefore, the communication between the four sub-boards and the mother board has four pairs of GTX signal lines, eight pairs of LVDS signal lines and thirty-six single-ended signal lines.

[0039] (S2) completing initialization after the system is powered on: the channels of the mother board enter the initial state of the finite state machine, each sub-board completes basic configuration and opens the data transceiving channel, and starts to wait for data. The basic configuration parameters of each sub-board are mainly stored in the Flash of the FPGA minimum system of the sub-board, including the program loading of the FPGA after power-on and the parameter configuration of the communication protocols of various electrical signal channels, such as the baud rate and other parameters of RS232 communication, which are not described herein.

[0040] Please refer to Figure 3 The program block diagram of the mother board FPGA is provided in the embodiment, and the program is input by using the Verilog HDL language. The communication with the four sub-boards is performed through the GTX interfaces 1 to 4, and the communication process includes two operations of sending data from the mother board to the sub-boards and receiving data from the sub-boards to the mother board. The GTX frame needs to be decoded and translated, that is, the effective information is extracted through the communication protocol conversion in the figure, and the information is judged by the finite state machine to determine whether the data is forwarded to the reflective memory network (the principle of the finite state machine is described in Figure 4 and the next paragraph herein). The sending to the reflective memory network also needs to be communicated protocol conversion, that is, the local frame of the FPGA is encoded and packaged, that is, converted into a data frame of the reflective memory network through the communication protocol conversion in the figure, and sent to the reflective memory network through the reflective memory network interface.

[0041] Please refer to Figure 4The embodiment provides a principle block diagram of a finite state machine. After system power-on initialization, an initial state is entered, data arrival is waited, when there is daughterboard data arrival, a data receiving state is entered, after data receiving is completed, when there is no data sending task, the initial state is returned; when there is a data sending task, a data sending state is entered, after sending is completed, the initial state is returned. When there is daughterboard data to be sent and there is no daughterboard data arrival, the system enters the data sending state from the initial state, after data sending is completed, the initial state is returned. From the above, when daughterboard data needs to be received and sent simultaneously, the daughterboard data receiving task is performed first, and then the data sending task is performed.

[0042] Please refer to Figure 5 The embodiment provides a program block diagram of a daughterboard FPGA, and a Verilog HDL language is used for program input. The daughterboard buffers data from a motherboard through a GTX data receiving FIFO, and a GTX data sending FIFO is used to buffer data sent to the motherboard. When the data amount of the GTX data receiving FIFO reaches a set threshold, that is, 1 GTX frame is met, the frame receiving is completed, and the next frame is prepared to be received. The received frame is subjected to data checking, if the frame checking fails, a wrong GTX return frame is sent; if the frame checking succeeds, data classification is performed. When the frame is a read operation, the daughterboard sends a corresponding GTX return frame and a GTX frame containing register data to the motherboard; when the frame is a write operation, a corresponding GTX return frame is sent. When the write operation succeeds, command decoding is performed; after decoding, the command is divided into two IO instructions of receiving and sending, and both are used for the simulation node interface FIFO. When it is an IO instruction receiving, the simulation node interface FIFO1 starts to wait for data; when it is an IO instruction sending, the simulation node interface FIFO2 sends out data in the GTX frame.

[0043] Please refer to Figure 6 The embodiment provides a fixed format GTX frame for communication between a motherboard and a daughterboard. The first bit of the fixed format GTX frame is a fixed 32bit frame header, which is 0xAAFF0055 in the embodiment; the second bit is a 16bit CMD command word; the third bit is a 16bit data length frame, which can be any one of 0x0000-0xffff; the fourth bit is a Data frame with a length determined by the data length frame, and the value of the third bit is the bit number of the frame, for example, when the third bit is 0x00ff (255 in decimal), the length of the fourth bit is 255 bits; the fifth bit is a 32bit check bit, which is calculated by performing XOR on all bits except the frame header and the frame tail; and the sixth bit is a fixed 32bit frame tail, which is 0x55FF00AA in the embodiment.

[0044] Please refer to Figure 7The 16-bit CMD command word of the GTX frame of the present example includes read-write command, data invalid bit number and register address of command operation. The highest bit

[15] is a read-write flag bit. When it is 1, it indicates that the frame requests to perform write operation on the register. When it is 0, it indicates that the frame requests to perform read operation on the register. [14:10] is a reserved word. If more types of command requests are needed in special engineering practice, the reserved word is set with corresponding meaning. The reserved word in the present embodiment has no special meaning and is generally 0. [9:8] indicates the number of invalid bytes in the Data frame in the GTX frame. 0x0-0x3 respectively indicate that 1, 2, 3 and 4 bytes in the Data frame are invalid. [7:0] indicates the register address of the frame requested operation.

[0045] The GTX frame for communication between the mother board and the daughter board is a fixed format. When the format does not conform, the frame is discarded. The daughter board returns a GTX return frame every time the mother board sends a GTX frame. When the GTX return frame is returned, it is confirmed that the GTX frame is sent successfully.

[0046] Please refer to Figure 8 The CMD command word of the GTX return frame of the present example includes operation command and register address of operation. The frame header and the frame tail of the GTX return frame are the same as the frame header and the frame tail of the GTX frame. The data length is 0x0 and there is no Data frame. [15:8] of the CMD command word indicates state information. When the operation of the frame is write register value, the correct execution is 0x0 and the operation error is 0x1. When the frame is read register value, it is 0x2. [7:0] is the register address.

[0047] (S3) When the system has data 0xFFDEFA123456789 from the RS422 electrical signal channel of the daughter board 3 to receive (i.e. the value stored in the simulation node interface FIFO1 at this moment is 0xFFDEFA123456789, and the length meets 60 bits), the mother board sends an instruction to the daughter board - sends the GTX frame 0xAAFF0055+0x80FF+0x0000+0xc0808000+0x55FF00AA. The daughter board receives the frame, stores it in the GTX data receiving FIFO, performs data check, data classification and command decoding, and sends the operation success GTX return frame 0xAAFF0055+0x0000+0x0000+0x00000000+0x55FF00AA, judges as IO instruction receiving, activates the simulation node interface FIFO1, and the simulation node interface FIFO1 sends the received data to the GTX data sending FIFO, and then sends the GTX frame 0xAAFF0055+0x00FF+0x003C+0xFFDEFA123456789+0xC8031871B+0x55FF00AA to the mother board, and the mother board converts the data frame to the reflective memory network data frame through communication protocol conversion and finite state machine scheduling, and then sends it to the reflective memory network through the reflective memory network interface.

[0048] (S4) When the system has data 0xEEEFFF987654321 to send to the daughter board 3, the mother board receives the data from the reflective memory network, and when the length meets 60 bits, the mother board packs the data into the GTX frame 0xAAFF0055+0x0000+0x003C+0xEEEFFF987654321+0xC8C4D7E2B1+0x55FF00AA, and then sends the GTX frame to the daughter board 3 through the GTX interface. The daughter board 3 receives the frame, stores it in the GTX data receiving FIFO, performs data check, data classification and command decoding, and sends the operation success GTX return frame 0xAAFF0055+0x0000+0x0000+0x00000000+0x55FF00AA, judges as IO instruction sending, sends the data to the simulation node FIFO2, converts it into the simulation node data frame 0xAA+0xEEEFFF987654321+0xBB, and then sends it to the corresponding device through the simulation node interface of the daughter board.

[0049] Please refer to Figure 9The oscilloscope is used to test the time delay of the system. The system time delay is calculated from the start of completely receiving a data packet in the simulation node FIFO1 of the subboard 3 (i.e. the data length is 60 bits) to the end of completely sending through the reflective memory network interface. After 100 measurements of the RS422 channel of the subboard 3, the delay is stabilized at 850-1000 ns.

[0050] Compared with the prior art, the microsecond-level time delay control method for converting the reflective memory network node and the electrical signal interface does not increase the cost, applies the conversion system to one node of the reflective memory network, and has a longer transmission distance. The network protocol conversion is realized by using a hardware architecture, real-time performance is stronger, the transmission time delay can be controlled at the microsecond level, and the method can better adapt to the needs of a complex simulation system.

[0051] The above only describes the preferred examples of the present application and is not used to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement and improvement within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for controlling the microsecond-level delay of the conversion between a reflective memory network node and an electrical signal interface, characterized in that, Includes the following steps: Step 1: Using FPGA as the core control platform, construct a hardware system consisting of a motherboard and various daughterboards. The entire system is a node in the reflective memory network. The motherboard is responsible for parsing the reflective memory network protocol, processing local data frames, and communicating with the daughterboards. The daughterboards include LVDS, ARINC429, RS422, RS232, 1553B, A / D acquisition and D / A output daughterboards, and digital I / O daughterboards, which are used to implement the transmit and receive control of various electrical signal channels and communicate with the motherboard. The daughterboards and the motherboard are physically connected through the XMC interface, and the Aurora high-speed serial bus based on GTX is used for communication. Step 2: After the system is powered on, initialization is completed: each channel of the motherboard enters the initial state of the finite state machine, each daughterboard completes basic configuration and opens the data transmission and reception channels, and begins to wait for data; Step 3: Data Reception: When the data length received by the daughterboard channel meets the preset value, the received data is converted into GTX frames and sent to the FPGA of the motherboard via GTX. After being encoded into reflective memory network data, it is sent to the reflective memory network via the fiber optic interface. Step 4: Data Transmission: The reflective memory network sends data to the designated channel of the daughter board. After the mother FPGA judges the data, it writes it into the transmit FIFO of the corresponding channel of the mother FPGA. When the data length reaches the preset value, the mother FPGA converts the data into a GTX frame and sends the data to the corresponding daughter board through the GTX channel. The daughter board then processes the data and sends it out.

2. The method for controlling the microsecond-level delay of the conversion between a reflective memory network node and an electrical signal interface according to claim 1, characterized in that: Multi-channel refers to multiple electrical signal channels, including digital IO, LVDS, ARINC429, RS422, RS232, 1553B, A / D acquisition interface and D / A output interface. Each daughterboard selects an FPGA chip as the computing platform for the data transceiver interface, and Verilog HDL is used as the programming language.

3. The method for controlling the microsecond-level delay of the conversion between a reflective memory network node and an electrical signal interface according to claim 1, characterized in that: The physical channel between the motherboard and the daughterboard uses 1 pair of GTX signal lines, 2 pairs of spare LVDS signal lines, and 9 single-ended signal lines. The 9 single-ended signal lines include 2 status indicator signal lines, 1 reset signal line, and 6 spare single-ended signal lines. When the motherboard and daughterboard communicate, they first read the other party's status through the status signal lines. If the status is idle, communication will proceed; otherwise, they will wait.

4. A method for controlling the microsecond-level delay of a reflective memory network node and an electrical signal interface according to claim 1 or 3, characterized in that: The motherboard's operating state is implemented based on a finite state machine. When there is no data to be received or transmitted, the entire hardware system is in the initial state, waiting for data to arrive. When data is to be received or transmitted, the motherboard enters the data receiving state or the data sending state according to the demand and priority. When data reception or data sending is completed, it returns to the initial state and continues to wait for data.

5. The method for controlling the microsecond-level delay of the conversion between a reflective memory network node and an electrical signal interface according to claim 4, characterized in that: The GTX frames used for communication between the motherboard and the daughterboard are in a fixed format. If the format does not conform, the frame is discarded. When the motherboard sends a GTX frame to the daughterboard, the daughterboard must return a GTX return frame.

6. A method for controlling the microsecond-level delay of a reflective memory network node and electrical signal interface conversion according to claim 1 or 5, characterized in that: The calculation system latency begins when a data packet is fully received from the electrical signal channel of a sub-board and ends when it is fully transmitted through the reflected memory network interface.

7. The method for controlling the microsecond-level delay of the conversion between a reflective memory network node and an electrical signal interface according to claim 6, characterized in that: When a channel is simultaneously receiving and transmitting data, the motherboard enters the higher priority state according to the pre-set priority. That is, if the data receiving priority is higher than the data transmitting priority, it enters the data receiving state first, and then enters the data transmitting state after completion; otherwise, it enters the data transmitting state first, and then enters the data receiving state after completion.

8. The method for controlling the microsecond-level delay of the conversion between a reflective memory network node and an electrical signal interface according to claim 1, characterized in that: The first bit of a fixed-format GTX frame is a fixed 32-bit frame header; the second bit is a 16-bit CMD command word; the third bit is a 16-bit data length frame; the fourth bit is a Data frame whose length is determined by the data length frame; the fifth bit is a 32-bit check bit; and the sixth bit is a fixed 32-bit frame trailer.

9. The method for controlling the microsecond-level delay of the conversion between a reflective memory network node and an electrical signal interface according to claim 5, characterized in that: The CMD command word of the GTX return frame consists of two parts: the operation command and the register address of the operation.

10. A method for controlling the microsecond-level delay of a reflective memory network node and an electrical signal interface according to claim 1 or 8, characterized in that: The CMD command word of a GTX frame contains three parts: the read / write command, the number of invalid data bits, and the register address of the command operation.

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