A vertical fin-shaped power device and its preparation method and chip

Abstract

The present application belongs to the field of semiconductor technology and provides a vertical fin-shaped power device, a preparation method thereof, and a chip. An N-type drift layer and a P-type switch isolation layer are epitaxially grown in sequence on the front surface of a semiconductor substrate, and then a specified area of ​​the P-type switch isolation layer is N-doped to form a voltage channel layer, so as to divide the P-type switch isolation layer into a first switch isolation area and a second switch isolation area. An N-type connection area is formed on the voltage channel layer, and a first source doping layer, a second source doping layer, and a plurality of alternating P-type doping structures and N-type channel structures are formed on both sides of the N-type connection area. A gate metal layer is formed on the P-type doping structure, and multiple current channels are induced by the gate metal layer and the P-type doping structure of the fin structure to reach the source. The device can be turned on by inducing the current channel by the gate metal layer on the P-type doping structure, thereby achieving both low cost and device performance.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular relates to a vertical fin-shaped power device, a preparation method thereof, and a chip. Background Art

[0002] The breakdown voltage (BV) of power transistors is a crucial parameter. To increase BV while saving chip area, power transistors have transitioned from a planar to a vertical structure. The pursuit of high breakdown voltage, high current density, and a smaller device area remains the future development direction for power transistors.

[0003] However, in the fiercely competitive power device market, existing power transistors have the problem of being unable to simultaneously achieve both low cost and device performance. Summary of the Invention

[0004] In order to solve the above technical problems, the embodiments of the present application provide a vertical fin-shaped power device and a preparation method and chip thereof, aiming to simultaneously take into account low cost and device efficiency.

[0005] A first aspect of an embodiment of the present application provides a method for manufacturing a vertical fin-shaped power device, the method comprising:

[0006] Epitaxially growing an N-type drift layer and a P-type switch isolation layer in sequence on the front surface of the semiconductor substrate;

[0007] Performing N-type doping on a designated area of ​​the P-type switch isolation layer to form a voltage channel layer, so as to divide the P-type switch isolation layer into a first switch isolation region and a second switch isolation region;

[0008] An N-type connection region is formed on the voltage channel layer, and a first source doping layer, a second source doping layer, and a plurality of alternating P-type doping structures and N-type channel structures are formed on both sides of the N-type connection region; wherein the first source doping layer is located on the first switch isolation region and is connected to the N-type connection region through the N-type channel structure, and the second source doping layer is located on the second switch isolation region and is connected to the N-type connection region through the N-type channel structure;

[0009] forming a gate metal layer on the P-type doped structure; wherein the gate metal layer is insulated from the N-type channel structure;

[0010] A drain metal layer is formed on the back side of the semiconductor substrate.

[0011] In one embodiment, the forming of an N-type connection region on the voltage channel layer, and forming a first source doping layer, a second source doping layer, and a plurality of alternating P-type doping structures and N-type channel structures on both sides of the N-type connection region include:

[0012] Epitaxially growing an N-type epitaxial layer on the voltage channel layer and the P-type switch isolation layer;

[0013] Etching a first predetermined etched area on the N-type epitaxial layer to form a plurality of first etched deep grooves and a plurality of first N-type channel structures, and etching a second predetermined etched area on the N-type epitaxial layer to form a plurality of second etched deep grooves and a plurality of second N-type channel structures, so as to form the N-type connection region, the first source doping layer, and the second source doping layer on the voltage channel layer; wherein the first source doping layer and the N-type connection region are located on both sides of the first N-type channel structure, and the second source doping layer and the N-type connection region are located on both sides of the second N-type channel structure;

[0014] A first P-type doping structure in contact with the first switch isolation region is formed in the first etched deep trench, and a second P-type doping structure in contact with the second switch isolation region is formed in the second etched deep trench.

[0015] In one embodiment, the first preset etching region is located above the first P-type doped structure, the second preset etching region is located above the second P-type doped structure, and the N-type connection region is located between the first preset etching region and the second preset etching region.

[0016] In one embodiment, forming a first P-type doped structure in contact with the first switch isolation region in the first etched deep trench includes:

[0017] A P-type semiconductor material is deposited in the first etched deep trench to form a first P-type doped structure; wherein the first source doped layer and the N-type connection region are located on both sides of the first P-type doped structure and are both in contact with the first P-type doped structure.

[0018] In one embodiment, forming a second P-type doped structure in contact with the second switch isolation region in the second etched deep trench includes:

[0019] A P-type semiconductor material is deposited in the second etched deep groove to form a second P-type doped structure; wherein the second source doped layer and the N-type connection region are located on both sides of the second P-type doped structure and are in contact with the second P-type doped structure.

[0020] In one embodiment, the forming of an N-type connection region on the voltage channel layer, and forming a first source doping layer, a second source doping layer, and a plurality of alternating P-type doping structures and N-type channel structures on both sides of the N-type connection region include:

[0021] epitaxially growing an N-type semiconductor material on the voltage channel layer and the P-type switch isolation layer under the cover of the first photomask to form an N-type connection region, a first N-type channel structure, a second N-type channel structure, a first source doping layer, and a second source doping layer; wherein the first source doping layer and the N-type connection region are located on both sides of the first N-type channel structure, and the second source doping layer and the N-type connection region are located on both sides of the second N-type channel structure;

[0022] Under the cover of the second mask, a first P-type doping structure contacting the first switch isolation region is formed between adjacent first N-type channel structures, and a second P-type doping structure contacting the second switch isolation region is formed between adjacent second N-type channel structures.

[0023] In one embodiment, the preparation method further comprises:

[0024] N-type semiconductor material and P-type semiconductor material are alternately epitaxially grown using a first mask and a second mask to increase the thickness of the N-type connection area, the first N-type channel structure, the second N-type channel structure, the first source doping layer, the second source doping layer, the first P-type doping structure, and the second P-type doping structure.

[0025] In one embodiment, the N-type connection region, the first source doping layer, and the second source doping layer are arranged in parallel.

[0026] A second aspect of the embodiments of the present application further provides a vertical fin-shaped power device, which is manufactured using any of the manufacturing methods described above.

[0027] A third aspect of the embodiments of the present application further provides a chip, in which a vertical transistor prepared by any of the preparation methods described above is integrated.

[0028] Compared with the prior art, the embodiments of the present application have the following beneficial effects: an N-type drift layer and a P-type switch isolation layer are epitaxially grown in sequence on the front surface of a semiconductor substrate, and then a specified area of ​​the P-type switch isolation layer is N-doped to form a voltage channel layer, so as to divide the P-type switch isolation layer into a first switch isolation area and a second switch isolation area, an N-type connection area is formed on the voltage channel layer, and a first source doping layer, a second source doping layer and a plurality of alternating P-type doping structures and N-type channel structures are formed on both sides of the N-type connection area, a gate metal layer is formed on the P-type doping structure, and a plurality of current channels are induced to reach the source through the gate metal layer and the P-type doping structure of the fin structure, and the device can be turned on by inducing the current channel by the gate metal layer on the P-type doping structure, thereby achieving both low cost and device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 1 is a flow chart of a method for manufacturing a vertical transistor provided in one embodiment of the present application;

[0030] Figure 2 1 is a schematic diagram of forming an N-type drift layer 200 and a P-type switch isolation layer 300 according to an embodiment of the present application;

[0031] Figure 3 2 is a schematic diagram of forming a voltage channel layer 210 according to an embodiment of the present application;

[0032] Figure 4 is a schematic diagram of forming an N-type connection region 830 provided in one embodiment of the present application;

[0033] Figure 5 is a flow chart of step S30;

[0034] Figure 6 This is a schematic diagram of an epitaxial growth process provided by one embodiment of the present application on a voltage channel layer 210 and a P-type switch isolation layer;

[0035] Figure 7 3 is a schematic diagram of forming a first P-type doping structure 312 and a second P-type doping structure 322 according to an embodiment of the present application;

[0036] Figure 8 is another flowchart of step S30;

[0037] Figure 9 This is a schematic diagram of the operation of a vertical transistor provided by one embodiment of the present application. DETAILED DESCRIPTION

[0038] In order to make the technical problems, technical solutions and beneficial effects to be solved by this application more clearly understood, this application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0039] It should be noted that when an element is referred to as being “fixed on” or “disposed on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0040] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0041] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the description of this application, "plurality" means one or more, unless otherwise specifically defined.

[0042] References to "one embodiment," "some embodiments," or "an embodiment" in this specification mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in one or more embodiments of the present application. Thus, phrases such as "in one embodiment," "in some embodiments," "in some other embodiments," "in some other embodiments," "in a specific embodiment," and "in a specific application" appearing in various places in this specification do not necessarily refer to the same embodiment, but rather mean "one or more but not all embodiments," unless otherwise specifically emphasized. Furthermore, in one or more embodiments, particular features, structures, or characteristics may be combined in any suitable manner.

[0043] The battery voltage (BV) of power transistors is a crucial parameter. To increase BV while saving chip area, power transistors have transitioned from a planar to a vertical structure. Since the invention of the fin transistor (FINFET), it has successfully demonstrated the feasibility of CMOS processes at 14nm and even 3-5nm processes.

[0044] In order to balance low cost and device performance, the present invention provides a method for preparing a vertical fin-shaped power device. Figure 1 As shown, the preparation method includes steps S10 to S50.

[0045] Combine Figure 2 As shown, in step S10 , an N-type drift layer 200 and a P-type switch isolation layer 300 are epitaxially grown in sequence on the front surface of the semiconductor substrate 100 .

[0046] In this embodiment, the N-type drift layer 200 is formed on the front surface of the semiconductor substrate 100 , the P-type switch isolation layer 300 is formed on the surface of the N-type drift layer 200 , and the semiconductor substrate 100 is an N-type semiconductor.

[0047] In one embodiment, the semiconductor substrate 100 may be silicon carbide, silicon, or gallium nitride.

[0048] Combine Figure 3 As shown, in step S20 , N-type doping is performed on a designated area of ​​the P-type switch isolation layer 300 to form a voltage channel layer 210 , so as to divide the P-type switch isolation layer 300 into a first switch isolation region 311 and a second switch isolation region 321 .

[0049] N-type doping is performed on a designated area of ​​the P-type switch isolation layer 300 to form a voltage channel layer 210 , and the P-type switch isolation layer 300 is divided into a first switch isolation region 311 and a second switch isolation region 321 by the voltage channel layer 210 .

[0050] In one embodiment, by injecting N-type dopant ions into the central area of ​​the P-type switch isolation layer 300, a voltage channel layer 210 can be formed in the P-type switch isolation layer 300, and the first switch isolation region 311 and the second switch isolation region 321 are respectively located on both sides of the voltage channel layer 210, and the first switch isolation region 311 and the second switch isolation region 321 do not contact each other.

[0051] In one embodiment, the first switch isolation region 311 and the second switch isolation region 321 are symmetrically arranged with the voltage channel layer 210 as a symmetry axis.

[0052] Combine Figure 4 As shown, in step S30, an N-type connection region 830 is formed on the voltage channel layer 210, and a first source doping layer 810, a second source doping layer 820 and a plurality of alternating P-type doping structures and N-type channel structures are formed on both sides of the N-type connection region 830.

[0053] In this embodiment, the N-type connection region 830 is located on the voltage channel layer 210, the first source doping layer 810 is located on the first switch isolation region 311, and the first source doping layer 810 is connected to the N-type connection region 830 through an N-type channel structure, and the second source doping layer 820 is located on the second switch isolation region 321, and the second source doping layer 820 is connected to the N-type connection region 830 through an N-type channel structure.

[0054] In one embodiment, the first source doping layer 810 is connected to the N-type connection region 830 via a plurality of first N-type channel structures 410 , and the second source doping layer 820 is connected to the N-type connection region 830 via a plurality of second N-type channel structures 420 .

[0055] In one embodiment, see Figure 5 As shown, in step S30, an N-type connection region 830 is formed on the voltage channel layer 210, and a first source doping layer 810, a second source doping layer 820 and a plurality of alternating P-type doping structures and N-type channel structures are formed on both sides of the N-type connection region 830, including steps S311 to S313.

[0056] In step S311 , an N-type epitaxial layer 400 is epitaxially grown on the voltage channel layer 210 and the P-type switch isolation layer 300 .

[0057] In this embodiment, see Figure 6 As shown, an N-type epitaxial layer 400 is epitaxially grown on the voltage channel layer 210 and the P-type switch isolation layer (ie, the first switch isolation region 311 and the second switch isolation region 321 ) using an N-type semiconductor material epitaxial growth process.

[0058] In step S312, the first preset etching area on the N-type epitaxial layer 400 is etched to form a plurality of first etched deep grooves 301 and a plurality of first N-type channel structures 410, and the second preset etching area on the N-type epitaxial layer 400 is etched to form a plurality of second etched deep grooves 302 and a plurality of second N-type channel structures 420, so as to form an N-type connection region 830, a first source doping layer 810 and a second source doping layer 820 on the voltage channel layer 210.

[0059] In this embodiment, combined with Figure 4As shown, a first predetermined etching area on the N-type epitaxial layer 400 is etched to form a plurality of first etched deep grooves 301, and the first etched deep grooves 301 penetrate into the first switch isolation region 311, thereby dividing the N-type epitaxial layer 400 on the first switch isolation region 311 into a plurality of first N-type channel structures 410, a first source doping layer 810, and an N-type connection region 830. The first source doping layer 810 and the N-type connection region 830 are located in the plurality of first N-type channel structures 410. On both sides, the second preset etching area on the N-type epitaxial layer 400 is etched to form a plurality of second etched deep grooves 302, and the second etched deep grooves 302 penetrate into the second switch isolation area 321, thereby dividing the N-type epitaxial layer 400 on the second switch isolation area 321 into a second N-type channel structure 420, a second source doping layer 820, and an N-type connection area 830. The second source doping layer 820 and the N-type connection area 830 are located on both sides of the second N-type channel structure 420.

[0060] In one embodiment, the first etched deep trench 301 extends deep into the first switch isolation region 311 so that adjacent first N-type channel structures 410 do not contact each other, and the second etched deep trench 302 extends deep into the second switch isolation region 321 so that adjacent second N-type channel structures 420 do not contact each other.

[0061] In step S313 , a first P-type doping structure 312 contacting the first switch isolation region 311 is formed in the first etched trench 301 , and a second P-type doping structure 322 contacting the second switch isolation region 321 is formed in the second etched trench 302 .

[0062] In this embodiment, combined with Figure 7 As shown, the first etched deep trench 301 penetrates into the first switch isolation region 311 , and the first P-type doped structure 312 contacts the first switch isolation region 311 ; the second etched deep trench 302 penetrates into the second switch isolation region 321 , and the second P-type doped structure 322 contacts the second switch isolation region 321 .

[0063] In one embodiment, combined Figure 7 As shown, there may be multiple first P-type doping structures 312 , which are arranged in parallel and formed by filling the P-type doping material with multiple first etched deep trenches 301 .

[0064] In one embodiment, combined Figure 7As shown, the first preset etching area is used to determine the position of the first P-type doping structure 312 in the N-type epitaxial layer 400, and the second preset etching area is used to determine the position of the second P-type doping structure 322 in the N-type epitaxial layer 400. By determining the positions of the first P-type doping structure 312 and the second P-type doping structure 322, the structure between the first P-type doping structure 312 and the second P-type doping structure 322 is used as the N-type connection area 830. Therefore, the first preset etching area is located above the first P-type doping structure 312, the second preset etching area is located above the second P-type doping structure 322, and the N-type connection area 830 is located between the first preset etching area and the second preset etching area.

[0065] In one embodiment, a plurality of first P-type doping structures 312 are arranged in parallel.

[0066] In one embodiment, the widths of the plurality of first P-type doping structures 312 are equal.

[0067] In one embodiment, a plurality of second P-type doping structures 322 are arranged in parallel.

[0068] In one embodiment, the widths of the plurality of second P-type doping structures 322 are equal.

[0069] In one embodiment, in step S313 , forming a first P-type doped structure 312 in contact with the first switch isolation region 311 in the first etched deep trench 301 includes depositing a P-type semiconductor material in the first etched deep trench 301 to form the first P-type doped structure 312 .

[0070] In this embodiment, a first P-type doping structure 312 is formed by filling the first etched deep groove 301 with P-type doping material under the cover of a P-type doping mask. The first source doping layer 312 and the N-type connection region 830 are located on both sides of the first P-type doping structure 312, and the first source doping layer 312 and the N-type connection region 830 are both in contact with the first P-type doping structure 312.

[0071] In one embodiment, in step S313 , forming a second P-type doped structure in contact with the second switch isolation region 321 in the second etched deep trench 302 includes depositing a P-type semiconductor material in the second etched deep trench 302 to form the second P-type doped structure 322 .

[0072] In this embodiment, a second P-type doping structure 322 is formed by filling the second etched deep groove 302 with P-type doping material under the cover of a P-type doping mask. Since the second etched deep groove 302 penetrates into the second switch isolation area 321, the N-type epitaxial layer 400 at the position of the second source doping layer 322 and the N-type connection area 830 is not etched, so that the second source doping layer 322 and the N-type connection area 830 are located on both sides of the second P-type doping structure 322, and the second source doping layer 322 and the N-type connection area 830 are both in contact with the second P-type doping structure 322.

[0073] In one embodiment, in step S30, an N-type connection region is formed on the voltage channel layer, and a first source doping layer, a second source doping layer, and a plurality of alternating P-type doping structures and N-type channel structures are formed on both sides of the N-type connection region, including step S321 and step S322.

[0074] In step S321 , N-type semiconductor material is epitaxially grown on the voltage channel layer 210 and the P-type switch isolation layer 300 under the cover of a first photomask to form an N-type connection region 830 , a first N-type channel structure 410 , a second N-type channel structure 420 , a first source doping layer 810 , and a second source doping layer 820 .

[0075] In this embodiment, the positions of the N-type connection region 830, the first N-type channel structure 410, the second N-type channel structure 420, the first source doping layer 810 and the second source doping layer 820 are defined by a first mask, and then an N-type semiconductor material is deposited or epitaxially grown under the cover of the first mask, thereby forming an N-type connection region 830 on the voltage channel layer 210, forming a plurality of first N-type channel structures 410 and a first source doping layer 810 on the first switch isolation region 311, and forming a plurality of second N-type channel structures 420 and a second source doping layer 820 on the second switch isolation region 321.

[0076] In this embodiment, the first source doping layer 810 and the N-type connection region 830 are located on both sides of the first N-type channel structure 410 , and the second source doping layer 820 and the N-type connection region 830 are located on both sides of the second N-type channel structure 420 .

[0077] In one embodiment, the N-type semiconductor material may be N-type silicon carbide, N-type silicon, or N-type gallium nitride.

[0078] In step S322 , under the cover of a second mask, a first P-type doping structure contacting the first switch isolation region is formed between adjacent first N-type channel structures 410 , and a second P-type doping structure contacting the second switch isolation region 321 is formed between adjacent second N-type channel structures 420 .

[0079] In this embodiment, the second mask is used to cover the positions of the N-type connection area 830, the first N-type channel structure 410, the second N-type channel structure 420, the first source doping layer 810 and the second source doping layer 820. By depositing P-type semiconductor material under the cover of the second mask, a first P-type doping structure 312 in contact with the first switch isolation area 311 is formed between adjacent first N-type channel structures 410, and a second P-type doping structure 322 in contact with the second switch isolation area 321 is formed between adjacent second N-type channel structures 420.

[0080] In one embodiment, the P-type semiconductor material may be P-type silicon carbide, P-type silicon, or P-type gallium nitride.

[0081] In one embodiment, in order to increase the thickness of the N-type connection region 830, the first N-type channel structure 410, the second N-type channel structure 420, the first source doping layer 810, and the second source doping layer 820, the above-mentioned step S321 and step S322 can be performed alternately, and the first mask and the second mask are used to alternately epitaxially grow N-type semiconductor material and P-type semiconductor material, thereby increasing the thickness of the N-type connection region 830, the first N-type channel structure 410, the second N-type channel structure 420, the first source doping layer 810, the second source doping layer 820, the first P-type doping structure 312, and the second P-type doping structure 322 through multiple epitaxial preparation processes.

[0082] In one embodiment, the first N-type channel structure 410 is located on both sides of the first P-type doping structure 312 , and the second N-type channel structure 420 is located on both sides of the second P-type doping structure 322 .

[0083] In one embodiment, the plurality of first N-type channel structures 410 and the plurality of second N-type channel structures 420 are disposed in a one-to-one correspondence.

[0084] In one embodiment, the first N-type channel structure 410 and the second N-type channel structure 420 have the same width.

[0085] In one embodiment, the device's withstand voltage can be increased by designing the wafer thickness, thereby increasing the width of the device to accommodate the switching of the vertical transistor, thereby achieving high current density and high breakdown voltage within the same chip area. Although the connection region 830 is added compared to conventional device designs, as process evolution allows for the introduction of more high aspect ratio technologies, the vertical transistor in this embodiment has significant development potential.

[0086] In step S40 , a gate metal layer is formed on the P-type doped structure.

[0087] In this embodiment, the gate metal layer is formed on the first P-type doping structure 312 and the second P-type doping structure 322 , and the gate metal layer is insulated from the first N-type channel structure 410 and the second N-type channel structure 420 .

[0088] In one embodiment, a first gate metal layer is formed on the first P-type doping structure 312 , and a second gate metal layer is formed on the second P-type doping structure 322 .

[0089] In step S50 , a drain metal layer 850 is formed on the back surface of the semiconductor substrate 100 .

[0090] In this embodiment, see Figure 9 As shown, the drain metal layer 850 can be formed in a partial area of ​​the back side of the semiconductor substrate 100 or cover the entire back side of the semiconductor substrate 100 .

[0091] In one embodiment, the N-type connection region 830 , the first source doping layer 810 , and the second source doping layer 820 are disposed in parallel.

[0092] In one embodiment, the first P-type doped structure 312 and the first switch isolation region 311 are both P-type doped semiconductors, and the first N-type channel structure 410 and the first P-type doped structure 312 are alternately arranged to form a fin-shaped JFET structure. The first switch isolation region 311 is also used to isolate the first N-type channel structure 410 and the N-type drift layer 200. Taking the enhancement-type vertical transistor device as an example, a high voltage is connected to the first gate metal layer, which can reduce the depletion region of the JFET structure under the fin gate, thereby turning on the device. If the voltage connected to the first gate metal layer is less than the turn-off threshold voltage, the depletion region of the JFET structure under the fin gate can be kept unchanged, thereby turning off the device.

[0093] In practical applications, if the transistor device is a depletion-type normally-on device, a negative voltage needs to be connected to the first gate metal layer to turn off the transistor.

[0094] Similarly, the fin-shaped JFET structure formed by the second switch isolation region 321 , the second source doping layer 820 , the N-type connection region 830 , the second P-type doping structure 322 and the second N-type channel structure 420 has the same working mechanism.

[0095] An embodiment of the present application further provides a vertical fin-shaped power device, which is manufactured using the manufacturing method described in any of the above embodiments.

[0096] An embodiment of the present application further provides a chip, in which a vertical transistor prepared by any of the preparation methods described above is integrated.

[0097] In one embodiment, the chip integrates a vertical transistor manufactured by the manufacturing method described in the above embodiment.

[0098] In this embodiment, the chip includes a chip substrate, on which one or more vertical transistors are arranged. The vertical transistor can be prepared by the preparation method in any of the above embodiments, or the vertical transistor in any of the above embodiments can be arranged on the chip substrate.

[0099] In a specific application embodiment, other related semiconductor devices may be integrated on the chip substrate to form an integrated circuit with the vertical transistor.

[0100] In a specific application embodiment, the chip may be a switch chip or a driver chip.

[0101] Compared with the prior art, the embodiments of the present application have the following beneficial effects: an N-type drift layer and a P-type switch isolation layer are epitaxially grown in sequence on the front surface of a semiconductor substrate, and then a specified area of ​​the P-type switch isolation layer is N-doped to form a voltage channel layer, so as to divide the P-type switch isolation layer into a first switch isolation area and a second switch isolation area, an N-type connection area is formed on the voltage channel layer, and a first source doping layer, a second source doping layer and a plurality of alternating P-type doping structures and N-type channel structures are formed on both sides of the N-type connection area, a gate metal layer is formed on the P-type doping structure, and a plurality of current channels are induced to reach the source through the gate metal layer and the P-type doping structure of the fin structure, and the device can be turned on by inducing the current channel by the gate metal layer on the P-type doping structure, thereby achieving both low cost and device performance.

[0102] Those skilled in the art will clearly understand that for the sake of convenience and brevity in description, only the division of the above-mentioned doping regions is used as an example. In actual applications, the above-mentioned functional areas can be allocated to different doping regions as needed, that is, the internal structure of the device can be divided into different doping regions to complete all or part of the functions described above.

[0103] The doping regions in the embodiment can be integrated into one functional region, or each doping region can exist physically separately, or two or more doping regions can be integrated into one functional region. The above-mentioned integrated functional regions can be implemented by using the same doping ion or by using multiple doping ions. In addition, the specific names of the doping regions are only for the convenience of distinguishing each other and are not used to limit the scope of protection of this application. The specific working process of the doping region in the preparation method of the above-mentioned device can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0104] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A method for preparing a vertical fin-shaped power device, characterized in that: The preparation method comprises: Epitaxially growing an N-type drift layer and a P-type switch isolation layer in sequence on the front surface of the semiconductor substrate; Performing N-type doping on a designated area of ​​the P-type switch isolation layer to form a voltage channel layer, so as to divide the P-type switch isolation layer into a first switch isolation region and a second switch isolation region; An N-type connection region is formed on the voltage channel layer, and a first source doping layer, a second source doping layer, and a plurality of alternating P-type doping structures and N-type channel structures are formed on both sides of the N-type connection region; wherein the first source doping layer is located on the first switch isolation region and is connected to the N-type connection region through the N-type channel structure, and the second source doping layer is located on the second switch isolation region and is connected to the N-type connection region through the N-type channel structure; forming a gate metal layer on the P-type doped structure; wherein the gate metal layer is insulated from the N-type channel structure; A drain metal layer is formed on the back side of the semiconductor substrate.

2. The preparation method according to claim 1, wherein The method comprises forming an N-type connection region on the voltage channel layer, and forming a first source doping layer, a second source doping layer, and a plurality of alternating P-type doping structures and N-type channel structures on both sides of the N-type connection region, including: Epitaxially growing an N-type epitaxial layer on the voltage channel layer and the P-type switch isolation layer; Etching a first predetermined etched area on the N-type epitaxial layer to form a plurality of first etched deep grooves and a plurality of first N-type channel structures, and etching a second predetermined etched area on the N-type epitaxial layer to form a plurality of second etched deep grooves and a plurality of second N-type channel structures, so as to form the N-type connection region, the first source doping layer, and the second source doping layer on the voltage channel layer; wherein the first source doping layer and the N-type connection region are located on both sides of the first N-type channel structure, and the second source doping layer and the N-type connection region are located on both sides of the second N-type channel structure; A first P-type doping structure in contact with the first switch isolation region is formed in the first etched deep trench, and a second P-type doping structure in contact with the second switch isolation region is formed in the second etched deep trench.

3. The preparation method according to claim 2, wherein The first preset etching region is located above the first P-type doping structure, the second preset etching region is located above the second P-type doping structure, and the N-type connection region is located between the first preset etching region and the second preset etching region.

4. The preparation method according to claim 2, wherein The forming of a first P-type doped structure in contact with the first switch isolation region in the first etched deep trench includes: A P-type semiconductor material is deposited in the first etched deep trench to form a first P-type doped structure; wherein the first source doped layer and the N-type connection region are located on both sides of the first P-type doped structure and are both in contact with the first P-type doped structure.

5. The preparation method according to claim 2, wherein The forming of a second P-type doped structure in contact with the second switch isolation region in the second etched deep trench includes: A P-type semiconductor material is deposited in the second etched deep groove to form a second P-type doped structure; wherein the second source doped layer and the N-type connection region are located on both sides of the second P-type doped structure and are in contact with the second P-type doped structure.

6. The preparation method according to claim 1, wherein The method comprises forming an N-type connection region on the voltage channel layer, and forming a first source doping layer, a second source doping layer, and a plurality of alternating P-type doping structures and N-type channel structures on both sides of the N-type connection region, including: Epitaxially growing an N-type semiconductor material on the voltage channel layer and the P-type switch isolation layer under the cover of a first photomask to form an N-type connection region, a first N-type channel structure, a second N-type channel structure, a first source doping layer, and a second source doping layer; wherein the first source doping layer and the N-type connection region are located on both sides of the first N-type channel structure, and the second source doping layer and the N-type connection region are located on both sides of the second N-type channel structure; Under the cover of the second mask, a first P-type doping structure contacting the first switch isolation region is formed between adjacent first N-type channel structures, and a second P-type doping structure contacting the second switch isolation region is formed between adjacent second N-type channel structures.

7. The preparation method according to claim 6, wherein The preparation method further comprises: N-type semiconductor material and P-type semiconductor material are alternately epitaxially grown using a first mask and a second mask to increase the thickness of the N-type connection area, the first N-type channel structure, the second N-type channel structure, the first source doping layer, the second source doping layer, the first P-type doping structure, and the second P-type doping structure.

8. The preparation method according to any one of claims 2 to 7, wherein The N-type connection region, the first source doping layer, and the second source doping layer are arranged in parallel.

9. A vertical fin-shaped power device, characterized in that: The vertical fin-shaped power device is manufactured using the manufacturing method according to any one of claims 1 to 8.

10. A chip, characterized in that: The chip integrates a vertical transistor prepared by the preparation method according to any one of claims 1 to 8.

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