Nitride-based semiconductor device and method of manufacturing the same

Abstract

A nitrogen-based semiconductor device is characterized by comprising a first nitride semiconductor layer, a second nitride semiconductor layer, a first source electrode, a first gate electrode, and a first drain electrode. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer, and the band gap of the second nitride semiconductor layer is larger than that of the first nitride semiconductor layer. The first source electrode is strip-shaped and disposed above the second nitride semiconductor layer. The first gate electrode is disposed above the second nitride semiconductor layer and has a closed-loop profile to surround the first source electrode. The first drain electrode is disposed above the second nitride semiconductor layer and has a closed-loop profile to surround the first gate electrode.

Description

Technical Field

[0001] This disclosure generally relates to a nitride-based semiconductor device. More specifically, this disclosure relates to a nitride-based semiconductor device having a ring electrode. Background Technology

[0002] In recent years, in-depth research on high electron mobility transistors (HEMTs) has become widespread, especially for high-power switching and high-frequency applications. Group III nitride-based HEMTs utilize heterojunction interfaces between two materials with different band gaps to form quantum well-like structures that accommodate two-dimensional electron gas (2DEG) regions, thus meeting the requirements of high-power / frequency devices. Besides HEMTs, examples of devices with heterostructures further include heterojunction bipolar transistors (HBTs), heterojunction field-effect transistors (HFETs), and modulation-doped FETs (MODFETs). To meet increasingly demanding design requirements, HEMT devices need to be miniaturized. Therefore, maintaining the reliability of HEMT devices is crucial for miniaturization. Summary of the Invention

[0003] According to one aspect of this disclosure, a nitrogen-based semiconductor device is provided, comprising a first nitride semiconductor layer, a second nitride semiconductor layer, a first source electrode, a first gate electrode, and a first drain electrode. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer, and the band gap of the second nitride semiconductor layer is larger than the band gap of the first nitride semiconductor layer. The first source electrode is strip-shaped and disposed above the second nitride semiconductor layer. The first gate electrode is disposed above the second nitride semiconductor layer and has a closed-loop profile to surround the first source electrode. The first drain electrode is disposed above the second nitride semiconductor layer and has a closed-loop profile to surround the first gate electrode.

[0004] According to one aspect of this disclosure, a method for manufacturing a semiconductor device is provided. The method includes the steps of: forming a second nitride semiconductor layer on a first nitride semiconductor layer; forming a first conductive layer on the second nitride semiconductor layer; patterning the first conductive layer to form a gate electrode; forming a second conductive layer on the second nitride semiconductor layer; and patterning the second conductive layer to form a source electrode and a drain electrode, wherein the gate electrode and the drain electrode have at least an annular contour.

[0005] According to one aspect of this disclosure, a nitrogen-based semiconductor device is provided, comprising a first nitride semiconductor layer, a second nitride semiconductor layer, a source electrode, a gate electrode, and a drain electrode. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer, and the band gap of the second nitride semiconductor layer is larger than the band gap of the first nitride semiconductor layer. The source electrode is strip-shaped and disposed above the second nitride semiconductor layer. The gate electrode is ring-shaped and disposed above the second nitride semiconductor layer. The drain electrode is ring-shaped and disposed above the second nitride semiconductor layer, wherein the gate electrode is located between the source electrode and the drain electrode.

[0006] By using the above configuration, the ring-shaped electrode avoids weakening of the gate control capability, thereby reducing the possibility of leakage. Specifically, the ring-shaped electrode avoids the creation of exposed end faces outside the active region. Since processing such exposed end faces would have additional adverse effects on the structure, avoiding the processing of exposed end faces can also prevent leakage. Attached Figure Description

[0007] Various aspects of this disclosure will be readily understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that the various features may not be drawn to scale. That is, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased. Embodiments of this disclosure are described in more detail below with reference to the drawings, in which: Figure 1A This is a top view of a nitride-based semiconductor device according to some embodiments of the present disclosure; Figure 1B Following some embodiments of this disclosure Figure 1A A cross-sectional view of a nitride-based semiconductor device with line segment I-I'.

[0008] Figure 2 This is a top view of a nitride-based semiconductor device according to some embodiments of the present disclosure; Figure 3 This is a top view of a nitride-based semiconductor device according to some embodiments of the present disclosure; Figure 4 This is a cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure; and Figure 5 This is a cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present disclosure. Detailed Implementation

[0009] Common reference numerals are used throughout the accompanying drawings and detailed description to indicate the same or similar components. Embodiments of this disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.

[0010] A spatial description is given for the orientation of a component shown in the associated diagram relative to a particular component or group of components, or a plane of a component or group of components. Examples of such descriptions include "up," "above," "below," "upward," "left," "right," "downward," "top," "bottom," "vertical," "horizontal," "side," "higher," "lower," "upper," "above," "below," etc. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and actual embodiments of the structures described herein may be arranged in space in any orientation or manner, provided that the advantages of the embodiments of this disclosure are not deviated from by such arrangements.

[0011] Furthermore, it should be noted that in actual devices, due to manufacturing conditions, the actual shapes of various structures depicted as approximately rectangular may be curved, have rounded edges, have slightly uneven thickness, etc. The use of straight lines and right angles is merely for convenience in representing layers and features.

[0012] In the following description, semiconductor devices / dies / packages, methods of their manufacture, etc., are set forth as preferred examples. It will be apparent to those skilled in the art that modifications, including additions and / or substitutions, can be made without departing from the scope and spirit of this disclosure. Certain details may be omitted to avoid obscuring this disclosure; however, this disclosure is prepared to enable those skilled in the art to practice the teachings herein without undue experimentation.

[0013] Figure 1A This is a top view of a nitride-based semiconductor device 1A according to some embodiments of the present disclosure. Figure 1B It is according to some embodiments of this disclosure along Figure 1A A cross-sectional view of the nitride-based semiconductor device 1A along line segment I-I'. The nitride-based semiconductor device 1A includes a substrate 10, nitride semiconductor layers 12 and 14, electrodes 20, 24, 28, 32, 36, 40, 44, and gate electrodes 22, 26, 30, 34, 38, 42.

[0014] Substrate 10 may be a semiconductor substrate. Exemplary materials of substrate 10 may include, for example, but not limited to, Si, SiGe, SiC, gallium arsenide, p-doped Si, n-doped Si, sapphire, semiconductor-on-insulator (e.g., silicon-on-insulator (SOI)), or other suitable substrate materials. In some embodiments, substrate 10 may include, for example, but not limited to, group III elements, group IV elements, group V elements, or combinations thereof (e.g., III-V compounds). In other embodiments, substrate 10 may include, for example, but not limited to, one or more other features, such as doped regions, buried layers, epitaxial (epi) layers, or combinations thereof. In some embodiments, the material of substrate 10 may contain, for example, elements with… <111> Oriented silicon substrate.

[0015] In some embodiments, substrate 10 may include a buffer layer (not shown). The buffer layer may be in contact with nitride semiconductor layer 12. The buffer layer may be configured to reduce lattice and thermal mismatch between substrate 10 and nitride semiconductor layer 12, thereby addressing defects caused by mismatch / difference. The buffer layer may contain a III-V compound. The III-V compound may contain, for example, but not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof. Therefore, exemplary materials of the buffer layer may also contain, for example, but not limited to, GaN, AlN, AlGaN, InAlGaN, or combinations thereof.

[0016] In some embodiments, substrate 10 may further include a nucleation layer (not shown). The nucleation layer may be formed beneath the buffer layer. The nucleation layer may be configured to provide a transition to accommodate mismatch / difference between substrate 10 and the III-nitride layer of the buffer layer. Exemplary materials for the nucleation layer may include, for example, but not limited to, any of AlN or alloys thereof.

[0017] A nitride semiconductor layer 12 is disposed on / above / over the buffer layer. A nitride semiconductor layer 14 is disposed on / above / over the nitride semiconductor layer 12. Exemplary materials of the nitride semiconductor layer 12 may include, for example, but not limited to, nitrides or III-V compounds, such as GaN, AlN, InN, In... x Al y Ga (1-x-y) N (where x+y≤1), Al x Ga (1-x) N (where x ≤ 1). Exemplary materials for the nitride semiconductor layer 14 may include, for example, but not limited to, nitrides or III-V compounds, such as GaN, AlN, InN, In... x Al y Ga (1-x-y) N (where x+y≤1), Al x Ga (1-x) N (where x≤1).

[0018] The exemplary materials of nitride semiconductor layers 12 and 14 are chosen such that the band gap (i.e., bandgap width) of nitride semiconductor layer 14 is greater than / higher than the band gap of nitride semiconductor layer 12, which makes their electron affinity potentials different from each other and forms a heterojunction therebetween. For example, when nitride semiconductor layer 12 is an undoped GaN layer with a band gap of about 3.4 eV, nitride semiconductor layer 14 can be selected as an AlGaN layer with a band gap of about 4.0 eV. Thus, nitride semiconductor layers 12 and 14 can serve as a channel layer and a barrier layer, respectively. A triangular well potential is generated at the junction interface between the channel layer and the barrier layer, causing electrons to accumulate in the triangular well, thereby creating a two-dimensional electron gas (2DEG) region adjacent to the heterojunction. Therefore, semiconductor device 1A may include at least one GaN-based high electron mobility transistor (HEMT).

[0019] Electrodes 20, 24, 28, 32, 36, 40, and 44 may be disposed on / above / over the nitride semiconductor layer 14. In some embodiments, electrodes 20, 24, 28, 32, 36, 40, and 44 may be in contact with the nitride semiconductor layer 14. In some embodiments, the entirety of electrodes 20, 24, 28, 32, 36, 40, and 44 may be located within the active region of the nitride semiconductor layer 14. In some embodiments, electrodes 20, 24, 28, 32, 36, 40, and 44 may serve as either drain electrodes or source electrodes. The function of electrodes 20 and 22 depends on the device design. In some embodiments, electrodes 20, 28, 36, and 44 serve as source electrodes, and electrodes 24, 32, and 40 serve as drain electrodes.

[0020] Gate electrodes 22, 26, 30, 34, 38, and 42 may be disposed on / above / over the nitride semiconductor layer 14. In some embodiments, gate electrodes 22, 26, 30, 34, 38, and 42 may be in contact with the nitride semiconductor layer 14. In some embodiments, the entirety of gate electrodes 22, 26, 30, 34, 38, and 42 may be located within the active region of the nitride semiconductor layer 14. In some embodiments, the nitride-based semiconductor device 1A further includes a gate insulating layer disposed between the gate electrodes 22, 26, 30, 34, 38, and 42 and the nitride semiconductor layer 14. In some embodiments, the nitride-based semiconductor device 1A further includes a P-type doped nitride semiconductor layer disposed between the gate electrodes 22, 26, 30, 34, 38, and 42 and the nitride semiconductor layer 14.

[0021] Electrode 20 is strip-shaped. Electrodes 24, 28, 32, 36, 40, 44 and gate electrodes 22, 26, 30, 34, 38, 42 are each annular; as shown in Figure 1A, in addition to being annular, each of electrodes 24, 28, 32, 36, 40, 44 and gate electrodes 22, 26, 30, 34, 38, 42 is also rectangular. The annular electrodes 24, 28, 32, 36, 40, 44 and gate electrodes 22, 26, 30, 34, 38, 42 may have a closed loop profile to surround or enclose the corresponding electrode. For example, gate electrode 22 may surround or enclose electrode 20, while electrode 24 may surround or enclose gate electrode 22. Specifically, the electrode assembly arranged sequentially from electrode 20 outwards is: gate electrode 22, electrode 24, gate electrode 26, electrode 28, gate electrode 30, electrode 32, gate electrode 34, electrode 36, gate electrode 38, electrode 40, gate electrode 42, and electrode 44. These electrodes extend from the inside out and surround or enclose the electrodes within them. During device operation, charge carriers can move outwards from electrode 20 to the outermost electrode 44 and be extracted through electrode 44, and vice versa.

[0022] Annular electrodes can replace the configuration of full-strip electrodes. When using a full-strip electrode configuration, leakage current can occur at the opposite end faces of the strip electrode. Therefore, ion implantation is needed to break the 2DEG at the corresponding edge end faces to prevent leakage. However, this approach may damage the opposite end faces of the gate, thereby weakening the gate's control capability at the end faces and causing off-state leakage. Therefore, using annular electrodes avoids the above-mentioned defects, thus preventing the weakening of gate control capability and reducing the possibility of leakage. To ensure the smooth operation of the nitride-based semiconductor device 1A and to meet different electrical requirements, such as configuring it as a high-voltage device, the relative positional relationship between the electrodes can be further established.

[0023] In some embodiments, in the relationship between electrode 20, gate electrode 22, and electrode 24, the average distance between electrode 20 and gate electrode 22 is less than the average distance between gate electrode 22 and electrode 24. This relative positional relationship can also be applied to other outward electrodes. In some embodiments, the average distance between electrode 20 and gate electrode 22 is less than the average distance between electrode 24 and gate electrode 26. In some embodiments, the average distance between electrode 24 and gate electrode 26 is greater than the average distance between electrode 28 and gate electrode 26, and also greater than the average distance between electrode 28 and gate electrode 30. Here, average distance refers to the average distance value in both the length and width directions.

[0024] The standard deviation of the distance between the strip electrode 20 and the gate electrode 22 can be designed to be a low value. Specifically, the distance from the left and right end faces of electrode 20 to the gate electrode 22 can be equal to the distance from the upper and lower sides of electrode 20 to the gate electrode 22, thereby reducing the standard deviation of the distance between electrode 20 and the gate electrode 22 and improving the uniformity of the carrier current. The uniformity of the carrier current can also be achieved by adjusting the physical properties of the electrodes themselves. In some embodiments, the width of electrode 20 can be the same as the width of gate electrode 22. In some embodiments, the width of electrode 20 can be the same as the width of electrode 24. In some embodiments, the widths of electrodes 24, 28, 32, 36, 40, 44 and gate electrodes 22, 26, 30, 34, 38, 42 are all the same. In some embodiments, considering the final carrier current extraction capability, the width of electrode 44 can be designed to be greater than the widths of electrodes 24, 28, 32, 36, 40 and gate electrodes 22, 26, 30, 34, 38, 42.

[0025] In some embodiments, electrodes 20, 24, 28, 32, 36, 40, and 44 may comprise, for example, but not limited to, metals, alloys, doped semiconductor materials (e.g., doped crystalline silicon), compounds such as silicides and nitrides, other conductive materials, or combinations thereof. Exemplary materials for electrodes 20, 24, 28, 32, 36, 40, and 44 may comprise, for example, but not limited to, Ti, AlSi, TiN, or combinations thereof. Electrodes 20, 24, 28, 32, 36, 40, and 44 may be a single layer or multiple layers having the same or different compositions. In some embodiments, electrodes 20, 24, 28, 32, 36, 40, and 44 form an ohmic contact with the nitride semiconductor layer 14. The ohmic contact may be achieved by applying Ti, Al, or other suitable materials to electrodes 20 and 22. In some embodiments, each of electrodes 20, 24, 28, 32, 36, 40, and 44 is formed by at least one conformal layer and a conductive filler. The conformal layer may cover the conductive filler. Exemplary materials for the conformal layer may include, for example, but not limited to, Ti, Ta, TiN, Al, Au, AlSi, Ni, Pt, or combinations thereof. Exemplary materials for the conductive filler may include, for example, but not limited to, AlSi, AlCu, or combinations thereof.

[0026] In some embodiments, exemplary materials for the gate electrodes 22, 26, 30, 34, 38, and 42 may be metals or metal compounds, including but not limited to tungsten (W), gold (Au), palladium (Pd), titanium (Ti), tantalum (Ta), cobalt (Co), nickel (Ni), platinum (Pt), molybdenum (Mo), titanium nitride (TiN), tantalum nitride (TaN), other metal compounds, nitrides, oxides, silicides, doped semiconductors, metal alloys, or combinations thereof.

[0027] The method for manufacturing the nitride-based semiconductor device 1A can be a gate-first process. For example, a nitride semiconductor layer 12 can be formed on a substrate 10 first, and then a nitride semiconductor layer 14 can be formed on the nitride semiconductor layer 12. A conductive layer can be formed on the nitride semiconductor layer 14, and then a patterned conductive layer can be formed to form gate electrodes 22, 26, 30, 34, 38, 42 with annular contours. After the gate-first process is completed, another conductive layer can be formed, and then a patterned conductive layer can be formed to form electrodes 20, 24, 28, 32, 36, 40, 44 with annular contours. In some embodiments, after the gate-first process is completed and before the formation of another conductive layer, a protective layer can be formed to cover the gate electrodes 22, 26, 30, 34, 38, 42 to facilitate the formation of electrodes 20, 24, 28, 32, 36, 40, 44.

[0028] The aforementioned processes may include, for example, but not limited to, atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), metal-organic CVD (MOCVD), plasma-enhanced CVD (PECVD), low-pressure CVD (LPCVD), plasma-assisted vapor deposition, epitaxial growth, or other suitable processes.

[0029] Figure 2 This is a top view of a nitride-based semiconductor device 1B according to some embodiments of the present disclosure. The nitride-based semiconductor device 1B is similar to that shown in reference [reference needed] Figure 1A and Figure 1B The nitride-based semiconductor device 1A described and illustrated differs in that the electrodes and gate electrodes of the nitride-based semiconductor device 1B are designed with rounded corners. Specifically, the left and right end faces of electrode 20B may have rounded corners. Gate electrode 22B is annular; however, gate electrode 22B has rounded corners at the bends and is curved at the short side of its profile. Electrode 24B is annular; however, electrode 24B has rounded corners at the bends and is curved at the short side of its profile. This configuration reduces the standard deviation of the distance between electrodes, allowing the bent carrier flow to be more uniformly outward or inward. Furthermore, considering that the carrier flow is outward or inward, the curved profile balances the resistance between the electrodes, further achieving a uniform carrier flow.

[0030] Figure 3 This is a top view of a nitride-based semiconductor device 1C according to some embodiments of the present disclosure. The nitride-based semiconductor device 1C is similar to that shown in reference [reference needed] Figure 1A and Figure 1BThe nitride-based semiconductor device 1A described and illustrated differs in that the electrodes and gate electrodes of the nitride-based semiconductor device 1C are designed with different profiles. Specifically, for electrode components that are far apart, the width can be increased at the turning points of the electrode components to allow these far apart electrode components to have a smaller standard deviation of distance.

[0031] Taking electrode 20C, gate electrode 22C, and electrode 24C as examples, since the average distance between electrode 20C and gate electrode 22C is smaller than the average distance between gate electrode 22C and electrode 24C, the outermost electrode 24C can be designed with a different profile. Therefore, the profile of gate electrode 22C will differ from the profile of drain electrode 24C. Furthermore, since electrode 24C and gate electrode 26C also have a relatively large average distance, gate electrode 26C can also be designed with a different profile. Here, the different profile refers to a shape that, based on a ring and rectangle, has a wider width at the four corner bends than at other locations. In this way, although the distance at the diagonal positions of the rectangle will be longer, by making the width at the corner bends greater than at other locations, the standard deviation of the distance between electrodes can be effectively reduced, allowing the carrier flow to bend more uniformly outward or inward.

[0032] Figure 4 This is a cross-sectional view of a nitride-based semiconductor device 1D according to some embodiments of the present disclosure. The nitride-based semiconductor device 1D is similar to that shown in reference [reference needed] Figure 1A and Figure 1B The nitride-based semiconductor device 1A described and illustrated differs in that the nitride-based semiconductor device 1D further includes doped nitride semiconductor layers 50D, 52D, and 54D.

[0033] A doped nitride semiconductor layer 50D can be disposed between the nitride semiconductor layer 14 and the gate electrode 22D. A doped nitride semiconductor layer 52D can be disposed between the nitride semiconductor layer 14 and the gate electrode 26D. A doped nitride semiconductor layer 54D can be disposed between the nitride semiconductor layer 14 and the gate electrode 30D. The doped nitride semiconductor layers 50D, 52D, and 54D can be designed with the same annular contour as the gate electrodes 22D, 26D, and 30D.

[0034] By doping nitride semiconductor layers 50D, 52D, and 54D, semiconductor device 1D can be an enhancement-mode device, which is normally-off when the gate electrode is approximately at zero bias. Exemplary materials for doping nitride semiconductor layers 50D, 52D, and 54D may include, but are not limited to, p-type doped group III-V nitride semiconductor materials, such as p-type gallium nitride (GaN), p-type aluminum gallium nitride (AlGaN), p-type indium nitride (InN), p-type aluminum indium nitride (AlInN), p-type indium gallium nitride (InGaN), p-type aluminum indium gallium nitride (AlInGaN), or combinations thereof. In some embodiments, p-type doped materials can be achieved by using p-type impurities such as beryllium (Be), magnesium (Mg), zinc (Zn), and cadmium (Cd).

[0035] Figure 5 This is a cross-sectional view of a nitride-based semiconductor device 1E according to some embodiments of the present disclosure. The nitride-based semiconductor device 1E is similar to that shown in reference [reference needed] Figure 4 The nitride-based semiconductor device 1D described and illustrated differs in that the nitride-based semiconductor device 1D further includes doped nitride semiconductor layers 50D, 52D, and 54D, which are replaced by doped nitride semiconductor layers 50E, 52E, and 54E.

[0036] A doped nitride semiconductor layer 50E can be disposed between the nitride semiconductor layer 14 and the gate electrode 22E. The width of the doped nitride semiconductor layer 50E is greater than the width of the gate electrode 22E. A doped nitride semiconductor layer 52E can be disposed between the nitride semiconductor layer 14 and the gate electrode 26E. The width of the doped nitride semiconductor layer 52E is greater than the width of the gate electrode 26E. A doped nitride semiconductor layer 54E can be disposed between the nitride semiconductor layer 14 and the gate electrode 30E. The width of the doped nitride semiconductor layer 54E is greater than the width of the gate electrode 30E. The doped nitride semiconductor layers 50E, 52E, and 54E can be designed with the same annular contour as the gate electrodes 22E, 26E, and 30E.

[0037] The embodiments were chosen and described in order to best explain the principles of this disclosure and its practical application, so that others skilled in the art can understand the disclosure of the various embodiments and make various modifications suitable for the intended particular purpose.

[0038] As used herein and unless otherwise defined, the terms “substantially,” “largely,” “approximately,” and “about” are used to describe and account for minor variations. When used in conjunction with an event or situation, the terms may cover situations where the event or situation has clearly occurred and situations where the event or situation is approximately likely to occur. For example, when used in conjunction with numerical values, the terms may cover a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term “largely coplanar” may refer to two surfaces located within a few micrometers along the same plane, such as two surfaces located within 40 μm, 30 μm, 20 μm, 10 μm, or 1 μm along the same plane.

[0039] As used herein, unless the context clearly indicates otherwise, the singular terms “a / an” and “the” may include multiple references. In the description of some embodiments, a component provided “on” or “above” another component may cover the case where the preceding component is directly on the following component (e.g., in physical contact with the following component), and the case where one or more intermediate components are located between the preceding and following components.

[0040] While this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting. Those skilled in the art will understand that various changes and alternatives may be made without departing from the true spirit and scope of this disclosure as defined by the appended claims. The illustrations may not be drawn to scale. Due to manufacturing processes and tolerances, there may be differences between the process reproduction in this disclosure and actual equipment. Furthermore, it should be understood that actual apparatus and layers may deviate from the rectangular layer depicted in the drawings and may include corner surfaces or edges, rounded corners, etc., due to manufacturing processes such as conformal deposition, etching, etc. Other embodiments of this disclosure may exist that are not specifically described. This specification and the drawings should be considered illustrative rather than limiting. Modifications may be made to adapt particular circumstances, materials, compositions, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations are not restrictive.

Claims

1. A nitride-based semiconductor device, characterized by, include: First nitride semiconductor layer; A second nitride semiconductor layer is disposed on the first nitride semiconductor layer, and the band gap of the second nitride semiconductor layer is greater than the band gap of the first nitride semiconductor layer; The first source electrode is strip-shaped and disposed above the second nitride semiconductor layer; The first gate electrode is disposed above the second nitride semiconductor layer and has a closed loop profile to surround the first source electrode; and The first drain electrode is disposed above the second nitride semiconductor layer and has a closed loop profile to surround the first gate electrode; The second gate electrode is disposed above the second nitride semiconductor layer and has a closed loop profile to surround the first drain electrode; The second source electrode is disposed above the second nitride semiconductor layer and has a closed loop profile to surround the second gate electrode; The average distance between the first source electrode and the first gate electrode is less than the average distance between the first gate electrode and the first drain electrode; the average distance between the first source electrode and the first gate electrode is less than the average distance between the first drain electrode and the second gate electrode; all corners of the inner contour of the first drain electrode are chamfered, and all corners of the inner contour of the second gate electrode are chamfered.

2. The nitride-based semiconductor device according to Claim 1, wherein The average distance between the first drain electrode and the second gate electrode is greater than the average distance between the second gate electrode and the second source electrode.

3. The nitride-based semiconductor device according to Claim 1, wherein Also includes: The third gate electrode is disposed above the second nitride semiconductor layer and has a closed loop profile to surround the second source electrode.

4. The nitride-based semiconductor device according to claim 3, characterized in that, The average distance between the first drain electrode and the second gate electrode is greater than the average distance between the second source electrode and the third gate electrode.

5. The nitride-based semiconductor device according to claim 1, characterized in that, The first gate electrode and the first drain electrode are each rectangular.

6. The nitride-based semiconductor device according to claim 1, characterized in that, The distance from each end face of the first source electrode to the first gate electrode is equal to the distance from each side face of the first source electrode to the first gate electrode.

7. The nitride-based semiconductor device according to claim 1, characterized in that, The profile of the first gate electrode is different from the profile of the first drain electrode.

8. The nitride-based semiconductor device according to claim 1, characterized in that, The width of the first source electrode is the same as the width of the first gate electrode.

9. The nitride-based semiconductor device according to claim 8, characterized in that, The width of the first source electrode is the same as the width of the first drain electrode.

10. The nitride-based semiconductor device according to claim 1, characterized in that, The entire first source electrode, the entire first gate electrode, and the entire first drain electrode are all located within the active region of the second nitride semiconductor layer.

11. A method for manufacturing a nitride-based semiconductor device, characterized in that, include: A second nitride semiconductor layer is formed on the first nitride semiconductor layer; A first conductive layer is formed on the second nitride semiconductor layer; The first conductive layer is patterned to form a gate electrode; A second conductive layer is formed on the second nitride semiconductor layer; and The second conductive layer is patterned to form a source electrode and a drain electrode, wherein the gate electrode and the drain electrode have at least an annular profile; The gate electrode includes a first gate electrode and a second gate electrode, the source electrode includes a first source electrode and a second source electrode, and the drain electrode includes a first drain electrode. The first gate electrode surrounds the first source electrode, the first drain electrode surrounds the first gate electrode, the second gate electrode surrounds the first drain electrode, and the second source electrode surrounds the second gate electrode. The average distance between the first source electrode and the first gate electrode is less than the average distance between the first gate electrode and the first drain electrode. The average distance between the first source electrode and the first gate electrode is less than the average distance between the first drain electrode and the second gate electrode. All corners of the inner contour of the first drain electrode are chamfered, and all corners of the inner contour of the second gate electrode are chamfered.

12. The manufacturing method according to claim 11, characterized in that, The first source electrode has an elongated profile.

13. The manufacturing method according to claim 11, characterized in that, The annular profile of the gate electrode is a closed annular profile.

14. The manufacturing method according to claim 11, characterized in that, The annular profile of the drain electrode is a closed annular profile.

15. A nitride-based semiconductor device, characterized in that, include: First nitride semiconductor layer; A second nitride semiconductor layer is disposed on the first nitride semiconductor layer, and the band gap of the second nitride semiconductor layer is greater than the band gap of the first nitride semiconductor layer; The source electrode is disposed above the second nitride semiconductor layer; The gate electrode is ring-shaped and disposed above the second nitride semiconductor layer; and A drain electrode, which is ring-shaped, is disposed above the second nitride semiconductor layer, wherein the gate electrode is located between the source electrode and the drain electrode; The gate electrode includes a first gate electrode and a second gate electrode; the source electrode includes a strip-shaped first source electrode and a ring-shaped second source electrode; the drain electrode includes a first drain electrode; the first gate electrode surrounds the first source electrode; the first drain electrode surrounds the first gate electrode; the second gate electrode surrounds the first drain electrode; and the second source electrode surrounds the second gate electrode. The average distance between the first source electrode and the first gate electrode is less than the average distance between the first gate electrode and the first drain electrode. The average distance between the first source electrode and the first gate electrode is less than the average distance between the first drain electrode and the second gate electrode. The inner contour corners of the first drain electrode are all chamfered, and the inner contour corners of the second gate electrode are all chamfered.

16. The nitride-based semiconductor device according to claim 15, characterized in that, The annular profile of the gate electrode is a closed annular profile.

17. The nitride-based semiconductor device according to claim 15, characterized in that, The annular profile of the drain electrode is a closed annular profile.

18. The nitride-based semiconductor device according to claim 15, characterized in that, The gate electrode and the drain electrode are each rectangular.

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