Trench power semiconductor devices and their manufacturing methods

Abstract

This invention provides a trench-type power semiconductor device and a method for manufacturing the same. The semiconductor device includes an epitaxial layer, a bottom insulating layer, a gate insulating layer, a shielding electrode, a gate, and an isolation structure. The epitaxial layer has at least one trench, and the bottom insulating layer and the gate insulating layer respectively cover the lower inner wall surface and the upper inner wall surface of the trench. The shielding electrode is disposed in at least one trench, and the bottom insulating layer surrounds the shielding electrode. The gate is disposed on the shielding electrode and is isolated from the epitaxial layer by the gate insulating layer. The isolation structure is located between the gate and the shielding electrode and includes a covering portion and a spacer portion. The covering portion covers the top of the shielding electrode and the bottom insulating layer, defining at least one recessed region, and the spacer portion is located within the at least one recessed region. The spacer portion includes a first blocking portion and a filling body portion. The first blocking portion is sandwiched between the filling body portion and the covering portion. The filling body portion closes at least one recessed region, and the filling body portion and the first blocking portion are respectively made of different materials.

Description

Technical Field

[0001] This invention relates to a power semiconductor device and a method for manufacturing the same, and more particularly to a trench-type power semiconductor device with shielding electrodes and a method for manufacturing the same. Background Technology

[0002] First, the operating losses of existing trench power metal-oxide-semiconductor field transistors (Power MOSFETs) can be divided into two main categories: switching loss and conducting loss. To reduce the gate / drain capacitance (Cgd) and thus the switching loss, existing trench power MOSFETs have a shielding electrode located in the lower half of the gate trench.

[0003] In the existing manufacturing process of trench power metal-oxide-semiconductor field-effect transistors (MOSFETs), the gate is directly formed after thermal oxidation, which forms both the gate oxide layer and the inter-electrode dielectric layer used to isolate the shielding electrode from the gate. However, the inter-electrode dielectric layer formed by thermal oxidation has a relatively low thickness in some areas. Furthermore, sharp corners are formed at the top of the shielding electrode and the bottom of the gate, making it easier for charge to accumulate and increasing the electric field. This can lead to insufficient breakdown voltage between the gate and the shielding electrode or leakage current, affecting device reliability. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a trench power semiconductor device and its manufacturing method to address the shortcomings of the prior art, which can avoid the formation of sharp corners at the top of the shielding electrode and the bottom of the gate, thereby improving the device reliability.

[0005] To address the aforementioned technical problems, another technical solution adopted by the present invention is to provide a trench-type power semiconductor device, comprising an epitaxial layer, a bottom insulating layer, a gate insulating layer, a shielding electrode, a gate, and an isolation structure. The epitaxial layer has at least one trench, and the bottom insulating layer and the gate insulating layer respectively cover the lower inner wall surface and the upper inner wall surface of the trench. The shielding electrode is disposed within at least one trench, and the bottom insulating layer surrounds the shielding electrode. The gate is disposed on the shielding electrode and is isolated from the epitaxial layer by the gate insulating layer. The isolation structure is located between the gate and the shielding electrode and includes a covering portion and a spacer portion. The covering portion covers the top and bottom insulating layers of the shielding electrode and is connected to the gate insulating layer. The covering portion defines at least one recessed region, and the spacer portion is located within the at least one recessed region. The spacer portion includes a first blocking portion and a filling body portion. The first blocking portion is sandwiched between the filling body portion and the covering portion. The filling body portion closes at least one recessed region, and the filling body portion and the first blocking portion are respectively made of different materials.

[0006] Furthermore, the materials constituting the covering portion and the filling body portion are both silicon oxide, and the material constituting the first barrier portion is a nitride or a nitrogen oxide.

[0007] Furthermore, the materials constituting the filling body include silicon oxide and polysilicon, with the polysilicon embedded within the silicon oxide and isolated from the gate.

[0008] Furthermore, the gate insulation layer includes a sidewall portion, which is connected to the cover portion and is made of the same material.

[0009] Furthermore, the gate insulation layer further includes a second barrier portion, with a sidewall portion located between the second barrier portion and the upper inner wall surface of the trench, and the second barrier portion is connected to the first barrier portion and is made of the same material.

[0010] Furthermore, the gate insulation layer further includes: a repair layer covering the surfaces of the sidewall portion, the cover portion, and the filling body portion, and the repair layer and the sidewall portion are made of the same material.

[0011] To address the aforementioned technical problems, another technical solution adopted by the present invention is to provide a method for manufacturing a trench-type power semiconductor device, comprising the following steps: forming a trench in an epitaxial layer; forming a bottom insulating layer and a shielding electrode in the trench, wherein the bottom insulating layer covers a lower inner wall surface of the trench, and a top of the shielding electrode protrudes from a top surface of the bottom insulating layer; forming an isolation structure on the shielding electrode; and forming a gate in the trench. The step of forming the isolation structure includes at least: forming a cover portion, wherein the cover portion covers the shielding electrode and the bottom insulating layer, and defines at least one recessed region; and forming a spacer portion in the at least one recessed region, wherein the spacer portion includes a first blocking portion and a filling body portion, the filling body portion closes the recessed region, the first blocking portion is sandwiched between the cover portion and the filling body portion, and the filling body portion and the blocking layer are respectively made of different materials.

[0012] Further, the step of forming the spacer portion includes: forming a barrier layer covering the cover portion and the upper inner wall surface of the trench, the barrier layer including a first barrier portion and a second barrier portion covering the upper inner wall surface of the trench; forming a polysilicon layer to completely cover the barrier layer, wherein a portion of the polysilicon layer is located in at least one recessed region, but does not close the at least one recessed region, and defines an opening in the at least one recessed region; and performing a thermal oxidation process on the polysilicon layer to oxidize the polysilicon layer to form a thermal oxide layer, a portion of the thermal oxide layer filling the at least one recessed region to form a filling body portion.

[0013] Furthermore, the sum of the thickness of the barrier layer and the thickness of the polysilicon layer is less than the maximum width of at least one recessed region in a horizontal direction.

[0014] Furthermore, after performing thermal oxidation on the polysilicon layer, the thermal oxide layer covers the second barrier portion, and before the step of forming the gate, a portion of the thermal oxide layer covering the second barrier portion is removed, while the filling body portion located in at least one recessed region is retained.

[0015] Furthermore, the method for manufacturing a trench power semiconductor device further includes: removing a second barrier portion located on the upper inner wall surface of the trench and removing a portion of the thermal oxide layer before forming the gate, while retaining the first barrier portion and the filling body portion.

[0016] Furthermore, in the step of forming the cover portion, a side wall portion of the upper inner wall surface of the cover trench is also formed, and the manufacturing method further includes: after removing the second barrier portion, forming a repair layer to cover the inner surface of the side wall portion and the top surface of the isolation structure, and surrounding the gate.

[0017] Furthermore, the materials constituting the covering part and the filling body part are both silicon oxide, and the materials constituting the barrier layer are nitrides or oxynitrides.

[0018] One of the beneficial effects of the present invention is that the trench power semiconductor device and its manufacturing method provided by the present invention can reduce the leakage current between the gate and the shielding electrode and improve the device reliability by means of the technical solutions of "the spacer portion of the isolation structure between the gate and the shielding electrode is located in the recessed region and includes a first barrier portion and a filling body portion" and "the first barrier portion is located between the filling body portion and the cover portion, the filling body portion closes at least one recessed region, and the filling body portion and the first barrier portion are respectively made of different materials".

[0019] To further understand the features and technical content of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings provided are for reference and illustration only and are not intended to limit the present invention. Attached Figure Description

[0020] Figure 1 This is a flowchart illustrating a method for manufacturing a trench-type power semiconductor device according to an embodiment of the present invention.

[0021] Figure 2 This is a schematic diagram of the trench power semiconductor device according to the first embodiment of the present invention in step S100.

[0022] Figure 3 This is a schematic diagram of the trench power semiconductor device according to the first embodiment of the present invention during the step of forming the initial bottom insulating layer.

[0023] Figure 4 This is a schematic diagram of the trench power semiconductor device of the first embodiment of the present invention during the step of forming a shielding electrode.

[0024] Figure 5 This is a schematic diagram of step S110 of the manufacturing method according to an embodiment of the present invention.

[0025] Figure 6 This is a schematic diagram of step S121 of the manufacturing method according to an embodiment of the present invention.

[0026] Figure 7 This is a schematic diagram of the trench power semiconductor device of the first embodiment of the present invention during the steps of forming a barrier layer and a polysilicon layer.

[0027] Figure 8 This is a schematic diagram of a trench-type power semiconductor device in the thermal oxidation process according to the first embodiment of the present invention.

[0028] Figure 9This is a schematic diagram of the trench power semiconductor device according to the first embodiment of the present invention during the step of removing a portion of the thermal oxide layer.

[0029] Figure 10 This is a cross-sectional schematic diagram of a trench power semiconductor device according to the first embodiment of the present invention.

[0030] Figure 11 This is a schematic diagram of the trench power semiconductor device according to the second embodiment of the present invention during the step of removing a portion of the barrier layer.

[0031] Figure 12 This is a cross-sectional schematic diagram of a trench power semiconductor device according to a second embodiment of the present invention.

[0032] Figure 13 This is a schematic diagram of the trench power semiconductor device of the third embodiment of the present invention during the step of forming an insulating layer.

[0033] Figure 14 This is a cross-sectional schematic diagram of a trench power semiconductor device according to a third embodiment of the present invention. Detailed Implementation

[0034] The following specific examples illustrate the embodiments of the "trench-type power semiconductor device and its manufacturing method" disclosed in this invention. Those skilled in the art can understand the advantages and effects of this invention from the content disclosed in this specification. This invention can be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of this invention. Furthermore, the accompanying drawings of this invention are for simple illustrative purposes only and are not depictions of actual dimensions; this is stated beforehand. The following embodiments will further describe the relevant technical content of this invention in detail, but the disclosed content is not intended to limit the scope of protection of this invention.

[0035] It should be understood that while terms such as "first," "second," and "third" may be used in this document to describe various components or signals, these components or signals should not be limited by these terms. These terms are primarily used to distinguish one component from another, or one signal from another. Furthermore, the term "or" as used herein should, as appropriate, include any combination of one or more of the associated listed items.

[0036] [First Embodiment]

[0037] Reference Figure 1 The first embodiment of the present invention provides a method for manufacturing a trench-type power semiconductor device, which can be used to manufacture at least one trench-type power semiconductor device. The trench-type power semiconductor device can be a trench-type power transistor or other power semiconductor devices. For example... Figure 1 As shown, the method for manufacturing a trench power semiconductor device includes at least the following steps: in step S100, a trench is formed in an epitaxial layer; in step S110, a bottom insulating layer and a shielding electrode are formed in the trench; in step S120, an isolation structure is formed on the shielding electrode; and in step S130, a gate is formed in the trench.

[0038] Furthermore, the step of forming the isolation structure (S120) further includes: in step S121, forming a covering portion, wherein the covering portion covers the shielding electrode and the bottom insulating layer, and defines at least one recessed region; and in step S122, forming a spacer portion within the at least one recessed region, wherein the spacer portion includes a first blocking portion and a filling body portion, the first blocking portion being sandwiched between the covering portion and the filling body portion, and the filling body portion closing the recessed region. The specific process and details of each step will be described in detail below using the manufacture of a trench-type power semiconductor device according to the first embodiment of the present invention as an example.

[0039] Please refer to Figure 2 And in conjunction with reference Figure 1 In step S100, a trench 11H is formed within the epitaxial layer 11'. It should be noted that prior to this step, the epitaxial layer 11' can be formed on a substrate 10. The substrate 10 has a high concentration of conductive impurities to serve as the drain of the trench power semiconductor device. These conductive impurities can be N-type or P-type. Assuming the substrate 10 is a silicon substrate, the N-type conductive impurities are pentavalent element ions, such as phosphorus or arsenic ions, while the P-type conductive impurities are trivalent element ions, such as boron, aluminum, or gallium ions. If the trench power semiconductor device to be fabricated is an N-type trench power transistor, the substrate 10 can be doped with N-type conductive impurities. On the other hand, if the trench power semiconductor device to be fabricated is a P-type trench power semiconductor device, the substrate 10 is doped with P-type conductive impurities.

[0040] The epitaxial layer 11' has the same conductivity as the substrate 10, but the epitaxial layer 11' has a lower doping concentration. For example... Figure 2 As shown, the trench 11H is formed in the epitaxial layer 11' and extends downward from the surface of the epitaxial layer 11' to a position close to the substrate 10, but does not extend into the substrate 10.

[0041] Please refer to Figures 3 to 5 The diagrams illustrate the steps involved in forming the bottom insulating layer and the shielding electrode in the trench power semiconductor device of the first embodiment. More specifically, as shown... Figure 3As shown, an initial bottom insulating layer 12' is formed within the trench 11H, and the initial bottom insulating layer 12' covers the inner wall surface of the trench 11H. The thickness of the initial bottom insulating layer 12' can be adjusted according to the withstand voltage required by the trench-type power semiconductor device. Furthermore, the material constituting the initial bottom insulating layer 12' can be an oxide, such as silicon oxide, or other insulating materials. In addition, the initial bottom insulating layer 12' can be formed by thermal oxidation, physical vapor deposition, or chemical vapor deposition, etc., and the present invention is not limited thereto.

[0042] Please refer to Figure 4 A shielding electrode 13 is formed within the trench 11H. In one embodiment, a heavily doped semiconductor material can be repeatedly formed on the epitaxial layer 11' and filled into the trench 11H. Then, an etch-back process removes the heavily doped semiconductor material covering the surface of the epitaxial layer 11, leaving the heavily doped semiconductor material in the lower half of the trench 11H to fabricate the shielding electrode 13. The aforementioned heavily doped semiconductor material can be polysilicon containing conductive impurities.

[0043] Please refer to Figure 5 Using the shielding electrode 13 as a cover, a portion of the initial bottom insulating layer 12' located in the upper half of the trench 11H can be removed, thereby forming a bottom insulating layer 12 located in the lower half of the trench 11H. In other words, the bottom insulating layer 12 covers the lower inner wall surface of the trench 11H.

[0044] In addition, such as Figure 5 As shown, a portion of the shielding electrode 13 protrudes from the top surface 12s of the bottom insulating layer 12. In this embodiment, the portion of the shielding electrode 13 that protrudes from the bottom insulating layer 12 but is not surrounded by the bottom insulating layer 12 is defined as the top 131, while the other portion of the shielding electrode 13 embedded within the bottom insulating layer 12 is defined as the main body 130. The main body 130 of the shielding electrode 13 is covered by the bottom insulating layer 12 to isolate it from the epitaxial layer 11'.

[0045] Please refer to Figures 6 to 9 The diagrams illustrate the steps involved in forming the isolation structure on the shielding electrode in the trench power semiconductor device of the first embodiment. Further details can be found in the following figures. Figure 6 And in conjunction with reference Figure 1 In step S121, a dielectric layer 14 is formed to cover the top 131 of the shielding electrode 13. Figure 6As shown, the dielectric layer 14 also covers the upper inner wall surface of the trench 11H and the bottom insulating layer 12. In this embodiment, the dielectric layer 14 is formed by performing a thermal oxidation process, simultaneously oxidizing the upper inner wall surface of the trench 11H and the top 131 of the shielding electrode 13 (which is not covered by the bottom insulating layer 12). Accordingly, in this embodiment, the dielectric layer 14 is a thermally oxidized silicon layer, and has different thicknesses in different portions.

[0046] Furthermore, the dielectric layer 14 in this embodiment includes a cover portion 140 and a sidewall portion 141. The cover portion 140 covers the top 131 and the bottom insulating layer 12 of the shielding electrode 13, while the sidewall portion 141 covers the upper inner wall surface of the trench 11H. During the thermal oxidation process, the top 131 of the shielding electrode 13 is oxidized more than the epitaxial layer 11'. Therefore, the thickness of the cover portion 140 located directly above the shielding electrode 13 is greater than the thickness of the sidewall portion 141. In addition, the width of the upper half of the trench 11H is greater than the width of the lower half of the trench 11H. However, the present invention is not limited to the foregoing examples. In other embodiments, the dielectric layer 14 can also be formed by other deposition processes to have a more uniform thickness. Furthermore, in this embodiment, after the dielectric layer 14 is formed, the width of the top 131 of the shielding electrode 13 is smaller than the width of the main body portion 130.

[0047] It is worth noting that the dielectric layer 14 defines at least one recessed region 14h within the trench 11H. Furthermore, the cover portion 140 defines the aforementioned recessed region 14h next to the top 131 of the shielding electrode 13. Figure 6 In the cross-section shown, the recessed region 14h extends obliquely toward the side surface of the shielding electrode 13, making the cross-sectional shape of the recessed region 14h approximately tooth-shaped. Accordingly, the bottom end of the recessed region 14h is close to the shielding electrode 13 and farther away from the sidewall of the trench 11H.

[0048] It should be noted that, in this embodiment of the invention, the leakage current is reduced and the reliability of the component is improved by filling the recessed area for 14 hours. For details, please refer to [link / reference needed]. Figures 7 to 9 These diagrams illustrate the steps involved in forming the barrier layer and the filling body portion of the trench-type power semiconductor device according to the first embodiment. Figure 7 As shown, the barrier layer 15 conformally covers the surface of the epitaxial layer 11', the upper inner wall surface of the trench 11H, and the cover portion 140 of the dielectric layer 14. Accordingly, the barrier layer 15 includes at least a first barrier portion 150 located within the recessed region 14h and a second barrier portion 151 covering the sidewall portion 141 of the dielectric layer 14 (and the upper inner wall surface of the trench 11H).

[0049] After forming the barrier layer 15, a polysilicon layer 16' that completely covers the barrier layer 15 is then formed. Accordingly, the barrier layer 15 is sandwiched between the polysilicon layer 16' and the dielectric layer 14. The polysilicon layer 16' can be an undoped polysilicon layer (intrinsically polysilicon layer) or a doped polysilicon layer; the present invention is not limited thereto. Furthermore, as... Figure 7 As shown, a portion of the polysilicon layer 16' is located within the recessed region 14h, but does not close the recessed region 14h to define an opening 16h.

[0050] It should be noted that in subsequent steps, the polysilicon layer 16' will be oxidized to fill the recessed region 14h. Therefore, by forming a barrier layer 15 covering the surface of the epitaxial layer 11' and the inner wall surface above the trench 11H, the continuous oxidation of the epitaxial layer 11' in subsequent steps can be avoided, which would increase the threshold voltage of the trench power semiconductor device and affect the device's electrical performance. In one embodiment, the material constituting the barrier layer 15 is a nitride or oxynitride, such as silicon nitride or silicon oxynitride, but the present invention is not limited thereto.

[0051] Furthermore, by controlling the thickness t1 of the polysilicon layer 16' and the thickness t2 of the barrier layer 15, it is possible to prevent the polysilicon layer 16' and the barrier layer 15 from sealing the opening 16h. (Refer to reference) Figure 6 and Figure 7 For example, the sum of the thickness t2 of the barrier layer 15 and the thickness t1 of the polysilicon layer 16' will be less than the maximum width W of at least one recessed region 14h in the horizontal direction. In one embodiment, the following relationship can be satisfied between the thickness t1 of the polysilicon layer 16', the thickness t2 of the barrier layer 15, and the maximum width W of the recessed region 14h in the horizontal direction: W>2×(t1+t2).

[0052] The opening 16h defined by the polysilicon layer 16' has a maximum width W1 in a horizontal direction. In addition, by using the ratio between the maximum width W1 of the opening 16h in the horizontal direction and the thickness t1 of the polysilicon layer 16', the recessed region 14h can be completely closed after performing thermal oxidation treatment on the polysilicon layer 16'.

[0053] Please refer to Figure 7 and 8 A thermal oxidation process is performed on the polysilicon layer 16' to oxidize the polysilicon layer 16' to form a thermal oxide layer 16. A portion of the thermal oxide layer 16 is filled into at least one recessed region 14h to form a filling body portion 160, and another portion 161 of the thermal oxide layer 16 covers the second barrier portion 151 of the barrier layer 15, that is, covers the inner wall surface above the trench 11H.

[0054] Furthermore, it should be noted that due to process limitations, the polysilicon layer 16' at the bottom of the recessed region 14h may not be completely oxidized. Therefore, in one embodiment, the material constituting the filling body 160 may also include silicon oxide and polysilicon, with the polysilicon being covered by silicon oxide. Since the polysilicon is embedded within the silicon oxide and isolated from the gate, it does not affect the electrical performance of the trench power semiconductor device. In another embodiment, the polysilicon layer 16' at the bottom of the recessed region 14h may not be able to merge after oxidation, resulting in voids within the filling body 160, but the filling body 160 can still completely seal the recessed region 14h. That is, the voids located inside the filling body 160 are also isolated from the gate and do not affect the electrical performance of the trench power semiconductor device. Accordingly, even if unoxidized polysilicon or voids are formed within the recessed region 14h due to process limitations, it will not affect the normal operation of the device.

[0055] Please refer to Figure 9 A portion of the thermal oxide layer 16 is removed, while the filling body portion 160 located within the recessed region 14h is retained. Accordingly, the portion 161 of the thermal oxide layer 16 covering the upper inner wall surface of the trench 11H and the portion located directly above the shielding electrode 13 are also removed. That is, except for the filling body portion 160 located within the recessed region 14h, all other portions of the thermal oxide layer 16 are removed. In one embodiment, a portion of the thermal oxide layer 16 can be removed by performing selective etching. During selective etching, the barrier layer 15 is retained and not removed. Accordingly, the first barrier portion 150 located within the recessed region 14h and the filling body portion 160 together form the spacer portion SA filling the recessed region 14h. Through the above steps, an isolation structure (not labeled) located above the shielding electrode 13 can be formed within the trench 11H. The isolation structure includes at least the covering portion 140, the first barrier portion 150, and the filling body portion 160.

[0056] Additionally, please refer to Figure 9 In this embodiment, the top surface 160s of the filling body portion 160 extends obliquely from the second blocking portion 151 toward the top 131 of the shielding electrode 13. In one embodiment, the top surface 160s of the filling body portion 160 is an oblique arc surface.

[0057] Please refer to Figure 10 and in conjunction with reference Figure 1In step S130, a gate 17 is formed within the trench 11H. The gate 17 is located on the isolation structure and is isolated from the shielding electrode 13. It is worth noting that in this embodiment, since the top surface 160s of the filling body portion 160 is an inclined arc surface, the bottom of the gate 17 will have an arc surface to match the top surface 160s of the filling body portion 160. Therefore, less charge will accumulate at the bottom of the gate 17, thus reducing the increase in electric field strength.

[0058] Furthermore, by doping different concentrations and types of conductive impurities in different regions, a drift region 110, a body region 111, and a source region 112 can be formed within the epitaxial layer 11. The body region 111 and the source region 112 are formed in the epitaxial layer 11 on the side of the trench 11H, specifically in the upper half of the epitaxial layer 11, with the source region 112 located on the body region 111. The drift region 110 is located in the epitaxial layer 11 on the side closer to the substrate 10, that is, in the lower half of the epitaxial layer 11.

[0059] In detail, the substrate region 111 and the substrate 10 have different conductivity types, while the source region 112 has the same conductivity type as the substrate 10 and has a higher doping concentration than the substrate region 111. For example, when the trench power semiconductor device T1 is an N-type trench power transistor, the substrate region 111 is doped with P-type conductive impurities (such as P-wells). The portion of the epitaxial layer 11 that is not further doped, that is, the region located below the substrate region 111, is defined as the drift region 110 of the trench power semiconductor device T1.

[0060] Furthermore, the trench-type power semiconductor device T1 in this embodiment includes an epitaxial layer 11, a bottom insulating layer 12, a gate insulating layer, a shielding electrode 13, a gate 17, and an isolation structure. The epitaxial layer 11 has a trench 11H, and the bottom insulating layer 12, the gate insulating layer, the shielding electrode 13, the gate 17, and the isolation structure are located within the trench 11H. The bottom insulating layer 12 covers the lower inner wall surface of the trench 11H, while the gate insulating layer covers the upper inner wall surface of the trench 11H.

[0061] The shielding electrode 13 is disposed in the trench 11H and is isolated from the epitaxial layer 11 by the bottom insulating layer 12. In detail, the shielding electrode 13 can be divided into a top 131 and a main body 130. The top 131 protrudes from the bottom insulating layer 12, and the main body 130 is covered by the bottom insulating layer 12 and isolated from the epitaxial layer 11.

[0062] The gate 17 is disposed on the shielding electrode 13 and is isolated from the epitaxial layer 11 by the gate insulating layer. In this embodiment, the sidewall portion 141 covering the upper inner wall surface of the trench 11H and the second barrier portion 151 together form the gate insulating layer, but the present invention is not limited thereto.

[0063] In this embodiment of the invention, providing a shielding electrode 13 at the bottom of the trench 11H can reduce the gate / drain capacitance (Cgd), thereby reducing operating losses and improving the voltage conversion efficiency of the trench power semiconductor device T1 during operation. Furthermore, the shielding electrode 13 can be electrically connected to the source to achieve charge balance in the drift region 110, further increasing the breakdown voltage. Therefore, the impurity doping concentration in the drift region 110 can be relatively increased, thereby reducing the on-resistance in the drift region 110.

[0064] An isolation structure is located between the gate 17 and the shielding electrode 13, and includes a cover portion 140 and a spacer portion SA. For example... Figure 10 As shown, the cover portion 140 covers the top 131 and bottom insulating layer 12 of the shielding electrode 13 and is connected to the gate insulating layer. The cover portion 140 defines at least one recessed area 14h. Figure 10 (Two examples are shown), and the recessed area 14h is located next to the top 131 of the shielding electrode 13. In addition, the bottom end of the recessed area 14h is closer to the shielding electrode 13 and farther away from the sidewall of the trench 11H.

[0065] The spacer portion SA is located within the recessed area 14h and includes a first barrier portion 150 of the barrier layer 15 and a filling body portion 160. The first barrier portion 150 is sandwiched between the filling body portion 160 and the covering portion 140, and the filling body portion 160 and the first barrier portion 150 are made of different materials. Specifically, the first barrier portion 150 is convexly formed on the inner surface of the recessed area 14h, while the filling body portion 160 fills the remaining space of the recessed area 14h and completely seals the opening end of the recessed area 14h.

[0066] As previously described, the material constituting the filling body portion 160 may consist only of silicon oxide, or it may consist of both silicon oxide and polysilicon. When the material constituting the filling body portion 160 includes both silicon oxide and polysilicon, the polysilicon is embedded within the silicon oxide and isolated from the gate 17. Furthermore, in this embodiment, in addition to the first barrier portion 150 and the second barrier portion 151, the barrier layer 15 further has another portion located between the gate 17 and the cover portion 140.

[0067] Based on the above, since the spacer portion SA is filled within the recessed region for 14 hours, a sharp corner can be avoided at the bottom of the gate 17. This reduces the electric field strength between the gate 17 and the shielding electrode 13, increases the breakdown voltage between the gate 17 and the shielding electrode 13, and reduces the leakage current between the gate 17 and the shielding electrode 13. However, the example given above is merely one possible embodiment and is not intended to limit the invention.

[0068] [Second Embodiment]

[0069] Please refer to Figure 11 . Figure 11 This is a schematic diagram of a trench power semiconductor device according to a second embodiment of the present invention during the step of removing a portion of the barrier layer. Elements identical or similar to those in the first embodiment have the same or similar reference numerals, and the identical parts will not be described again.

[0070] Figure 11 Can be continued Figure 9 The steps shown are, after removing a portion of the thermally oxidized layer, removing a portion of the barrier layer 15. Specifically, the second barrier portion 151 of the barrier layer 15 and the portion located on the cover portion 140 can be removed, while the first barrier portion 150 located in the recessed area 14h is retained.

[0071] Please refer to Figure 12 A gate 17 is formed, and a substrate region 111 and a source region 112 are formed within the epitaxial layer 11, thereby forming a trench power semiconductor device T2 according to the second embodiment of the present invention. In this embodiment, the second barrier portion 151 of the barrier layer 15 and the portion located on the cover portion 140 are removed. The gate insulating layer only includes the sidewall portion 141 of the dielectric layer 14. In addition, the gate 17 is directly connected to the cover portion 140.

[0072] Compared to the trench power semiconductor device T1 in the first embodiment, the thickness of the gate insulating layer is smaller in this embodiment. However, in the trench power semiconductor device T2 of this embodiment, the sharp corner formed at the bottom of the gate 17 can still be avoided, thereby improving the breakdown voltage between the gate 17 and the shielding electrode 13 and reducing the leakage current between the gate 17 and the shielding electrode 13.

[0073] [Third Embodiment]

[0074] Please refer to Figure 13 . Figure 13 This is a schematic diagram of the trench-type power semiconductor device according to the third embodiment of the present invention during the step of forming an insulating layer. Elements that are the same as or similar to those in the second embodiment have the same or similar reference numerals, and the identical parts will not be described again.

[0075] Figure 13 Can be continued Figure 11 The steps shown involve forming another repair layer 18 within the trench 11H after removing a portion of the barrier layer 15. The repair layer 18 covers the inner surface of the gate insulating layer and the top surface of the isolation structure, and surrounds the gate 17. Since removing the second barrier portion 151 of the barrier layer 15 may result in defects in the sidewall portion 141 of the dielectric layer 14, these defects may affect the electrical performance of the device. Therefore, by forming the repair layer 18 covering the sidewall portion 141, these defects can be repaired, preventing them from affecting the electrical performance of the device. In this embodiment, the repair layer 18 also covers the isolation structure formed in the previous steps, that is, it covers the spacer portion SA and the cover portion 140 of the dielectric layer 14. In one embodiment, the repair layer 18 and the sidewall portion 141 are made of the same material, such as silicon oxide.

[0076] Please refer to Figure 14 A gate 17 is formed, and a substrate region 111 and a source region 112 are formed within the epitaxial layer 11, thereby forming a trench power semiconductor device T3 according to the third embodiment of the present invention. In this embodiment, the second barrier portion 151 of the barrier layer 15 and the portion located on the cover portion 140 are removed. Accordingly, the gate insulating layer may include the sidewall portion 141 of the dielectric layer 14 and the repair layer 18. In addition, the bottom surface of the gate 17 is directly connected to the repair layer 18.

[0077] Compared to the trench power semiconductor device T2 in the second embodiment, the trench power semiconductor device T3 in this embodiment has fewer defects in the gate insulating layer, which can prevent leakage current between the gate 17 and the drain, thus avoiding affecting the operation of the trench power semiconductor device T3. In addition, the trench power semiconductor device T3 in this embodiment can still avoid the gate 17 having a sharp corner formed at its bottom, thereby improving the breakdown voltage between the gate 17 and the shielding electrode 13 and reducing the leakage current between the gate 17 and the shielding electrode 13.

[0078] [Beneficial Effects of the Examples]

[0079] One of the beneficial effects of the present invention is that the trench power semiconductor device and its manufacturing method provided by the present invention can improve the withstand voltage between the gate 17 and the shielding electrode 13 and reduce the leakage current between the gate 17 and the shielding electrode 13, thereby improving the reliability of the trench power semiconductor device T1-T3, through the technical solutions of "the isolation structure located between the gate 17 and the shielding electrode 13 includes a cover portion 140 and a spacer portion SA, the cover portion 140 defines at least one recessed region 14h", "the spacer portion SA is located within at least one recessed region 14h, wherein the spacer portion SA includes a first barrier portion 150 and a filling body portion 160", and "the filling body portion 160 closes the recessed region 14h, the first barrier portion 150 is located between the dielectric layer 14 (or the cover portion 140) and the filling body portion 160, and the filling body portion 160 and the barrier layer 15 are respectively made of different materials".

[0080] The content disclosed above is only a preferred and feasible embodiment of the present invention, and is not intended to limit the scope of protection of the claims of the present invention. Therefore, all equivalent technical changes made based on the content of the present invention specification and drawings are included within the scope of protection of the claims of the present invention.

Claims

1. A trench-type power semiconductor device, characterized in that, The trench-type power semiconductor device includes: An epitaxial layer having at least one trench; A bottom insulating layer that covers one of the lower inner walls of the trench; A grid insulating layer covers an upper inner wall surface of the trench; A shielding electrode is disposed in at least one of the trenches, wherein the bottom insulating layer surrounds the shielding electrode; A gate electrode disposed on the shielding electrode and isolated from the epitaxial layer by the gate insulating layer; and An isolation structure is located between the gate and the shielding electrode, wherein the isolation structure includes: A cover portion covering a top and bottom insulating layer of the shielding electrode and connected to the gate insulating layer, wherein the cover portion defines at least one recessed area; and A spacer portion located within at least one of the recessed areas, and including a first barrier portion and a filling body portion, the first barrier portion being sandwiched between the filling body portion and the covering portion, the filling body portion enclosing at least one of the recessed areas, and the filling body portion and the first barrier portion being made of different materials respectively; The materials constituting the filling body include silicon oxide and polysilicon, wherein the polysilicon is embedded in the silicon oxide and isolated from the gate.

2. The trench power semiconductor device according to claim 1, characterized in that, The materials constituting the covering portion and the filling body portion are both silicon oxide, and the material constituting the first barrier portion is a nitride or nitrogen oxide.

3. The trench power semiconductor device according to claim 1, characterized in that, The gate insulation layer includes a sidewall portion that is connected to the cover portion and is made of the same material.

4. The trench power semiconductor device according to claim 3, characterized in that, The gate insulation layer further includes a second barrier portion, the sidewall portion being located between the second barrier portion and the upper inner wall surface of the trench, and the second barrier portion being connected to the first barrier portion and being made of the same material.

5. The trench power semiconductor device according to claim 3, characterized in that, The gate insulation layer further includes: a repair layer covering the surfaces of the sidewall portion, the cover portion, and the filling body portion, wherein the repair layer and the sidewall portion are made of the same material.

6. A method for manufacturing a trench-type power semiconductor device, characterized in that, The method for manufacturing the trench-type power semiconductor device includes: A trench is formed within an epitaxial layer; A bottom insulating layer and a shielding electrode are formed in the trench, wherein the bottom insulating layer covers a lower inner wall surface of the trench, and a top of the shielding electrode protrudes from a top surface of the bottom insulating layer; An isolation structure is formed on the shielding electrode, wherein the step of forming the isolation structure includes at least: A cover is formed, wherein the cover covers the shielding electrode and the bottom insulating layer, and defines at least one recessed area; A spacer portion is formed within at least one of the recessed areas, wherein the spacer portion includes a first blocking portion and a filling body portion, the filling body portion closing the recessed area, and the first blocking portion being sandwiched between the covering portion and the filling body portion; and A gate is formed within the trench; The steps for forming the interval portion include: A barrier layer is formed to cover the covering portion and the upper inner wall surface of the trench. The barrier layer includes a first barrier portion and a second barrier portion covering the upper inner wall surface of the trench. A polysilicon layer is formed to completely cover the barrier layer, wherein a portion of the polysilicon layer is located within at least one of the recessed regions, but does not close off the at least one recessed region, and defines an opening within the at least one recessed region; and A thermal oxidation process is performed on the polysilicon layer to oxidize the polysilicon layer and form a thermal oxide layer, a portion of the thermal oxide layer filling at least one of the recessed regions to form the filling body portion; and The filling body and the first barrier part are respectively made of different materials.

7. The method for manufacturing a trench-type power semiconductor device according to claim 6, characterized in that, The sum of the thickness of the barrier layer and the thickness of the polysilicon layer is less than the maximum width of at least one of the recessed regions in a horizontal direction.

8. The method for manufacturing a trench-type power semiconductor device according to claim 6, characterized in that, After the thermal oxidation process is performed on the polysilicon layer, the thermal oxidation layer covers the second barrier portion, and before the step of forming the gate, a portion of the thermal oxidation layer covering the second barrier portion is removed, while the filling body portion located in at least one of the recessed regions is retained.

9. The method for manufacturing a trench-type power semiconductor device according to claim 6, characterized in that, The method for manufacturing the trench-type power semiconductor device further includes: Prior to the step of forming the gate, the second barrier portion located on the upper inner wall surface of the trench is removed and a portion of the thermal oxide layer is removed, while the first barrier portion and the filling body portion are retained.

10. The method for manufacturing a trench-type power semiconductor device according to claim 9, characterized in that, In the step of forming the covering portion, a side wall portion covering the upper inner wall surface of the trench is also formed, and the manufacturing method further includes: After removing the second barrier portion, a repair layer is formed covering the inner surface of the sidewall portion and the top surface of the isolation structure, and surrounding the gate.

11. The method for manufacturing a trench-type power semiconductor device according to claim 6, characterized in that, The materials constituting the covering portion and the filling body portion are both silicon oxide, and the materials constituting the barrier layer are nitrides or oxynitrides.

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