Silicon carbide coated base substrate, silicon carbide substrate therefor, and method

Abstract

Embodiments of this disclosure generally relate to silicon carbide-coated substrates, silicon carbide substrates thereof, and methods for forming silicon carbide-coated substrates. In some embodiments, one method includes introducing a first silicon-containing precursor into a processing chamber at a first temperature of about 800°C to less than 1000°C to form a first silicon carbide layer on the substrate. The method further includes introducing a second silicon-containing precursor, which may be the same as or different from the first silicon-containing precursor, into the processing chamber at a second temperature of about 1000°C to about 1400°C to form a second silicon carbide layer on the first silicon carbide layer.

Description

background Technical Field

[0002] Embodiments of this disclosure generally relate to silicon carbide-coated substrates, silicon carbide substrates thereof, and methods for forming silicon carbide-coated substrates. Background Technology

[0004] Traditional silicon carbide (SiC) (with 4H or 6H crystallinity) is manufactured using a method known as the Lely process, which forms single-crystal SiC through sublimation. However, sublimation for forming 4H or 6H SiC is a very slow process and can be prohibitively expensive. Furthermore, 4H or 6H SiC formed using the Lely method is single-crystal SiC with high resistivity. Methods for forming SiC with different crystallinities have been explored even less than those for forming 4H or 6H SiC.

[0005] Graphite can be used as a base substrate for depositing SiC. Graphite provides mechanical strength, which can be advantageous when forming SiC components or SiC substrates (which are used in semiconductor processing). However, due to the porosity of graphite, SiC can intercolate into the pores (forming SiC "tendrils"), making it difficult to remove SiC from the graphite (for SiC substrate production) and increasing the surface roughness of the SiC substrate formed when SiC is removed from the graphite substrate. The tightly bonded SiC, once removed, can also form small cracks on the SiC substrate, and these cracks can propagate throughout the entire SiC substrate.

[0006] Furthermore, once SiC is deposited on graphite and cooled, the cooled SiC and graphite exhibit large stress / strain at the interface because the two materials shrink at different rates upon cooling from the high temperature. This large stress / strain can cause warping / bending of the SiC substrate (which occurs immediately upon removal from the graphite). The difference in lattice constants between SiC and graphite can also exacerbate or mask this stress / strain.

[0007] There is a need for methods for forming SiC substrates (such as polycrystalline SiC substrates, such as wafers). Summary of the Invention

[0008] In at least one embodiment, a method includes introducing a first silicon-containing precursor into a processing chamber at a first temperature of about 800°C to less than 1000°C to form a first silicon carbide layer on a substrate. The method further includes introducing a second silicon-containing precursor, which is the same as or different from the first silicon-containing precursor, into the processing chamber at a second temperature of about 1000°C to about 1400°C to form a second silicon carbide layer on the first silicon carbide layer.

[0009] In at least one embodiment, a method includes introducing a first silicon-containing precursor into a processing chamber at a first temperature of about 1000°C to about 1400°C. The method further includes reducing the first temperature to about 800°C to a second temperature less than 1000°C to form a first silicon carbide layer on a substrate. The method also includes introducing a second silicon-containing precursor, which is the same as or different from the first silicon-containing precursor, into the processing chamber at a third temperature of about 1000°C to about 1400°C, the same as or different from the first temperature, to form a second silicon carbide layer on the first silicon carbide layer.

[0010] In at least one embodiment, a multilayer stack includes a graphite substrate and a first silicon carbide layer disposed on the graphite substrate. The multilayer stack includes a second silicon carbide layer disposed on the first silicon carbide layer. The first silicon carbide layer has a thickness of about 1 micrometer to about 200 micrometers. The second silicon carbide layer has a thickness of about 40 micrometers to about 1.5 millimeters. Attached Figure Description

[0011] To gain a more detailed understanding of the features described above, a more specific description of the present disclosure, which has been briefly outlined above, can be obtained by referring to embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate only exemplary embodiments and should not be considered as limiting the scope of the present disclosure, and may allow for other equally effective embodiments.

[0012] Figure 1 This is a flowchart of a method according to one implementation.

[0013] Figure 2 This is a flowchart of a method according to one implementation.

[0014] Figure 3 This is a schematic cross-sectional view of a multilayer stack according to one embodiment.

[0015] For ease of understanding, the same reference numerals are used where possible to denote common elements in the figures. It is anticipated that elements and features of one embodiment can be advantageously incorporated into other embodiments without further description. Detailed Implementation

[0016] Embodiments of this disclosure generally relate to silicon carbide-coated substrates, silicon carbide substrates thereof, and methods for forming silicon carbide-coated substrates. The silicon carbide-coated substrate (and methods thereof) may provide a buffer layer disposed between the substrate and a polycrystalline silicon carbide layer. This buffer layer may be, for example, amorphous silicon carbide. This buffer layer reduces the stress / strain mismatch between the substrate and the polycrystalline silicon carbide layer (compared to polycrystalline silicon carbide directly disposed on the substrate). The reduced stress / strain provides numerous benefits, including (1) reduced warpage or bending of the polycrystalline silicon carbide (which occurs as soon as it is removed from the substrate to form the polycrystalline silicon carbide substrate), and (2) reduced removal of excess silicon carbide from the polycrystalline silicon carbide to obtain a substantially flat polycrystalline silicon carbide substrate, given the reduced warpage / bending. In some embodiments that may be combined with other embodiments, the polycrystalline silicon carbide layer has a 3C crystallinity (e.g., cubic), which can provide lower resistivity and lower cost than, for example, 4H SiC or 6H SiC formed using the Lely process.

[0017] In some embodiments, a method includes introducing a first silicon-containing precursor into a processing chamber at a first temperature of about 800°C to less than 1000°C to form a first silicon carbide layer on a substrate. The method further includes introducing a second silicon-containing precursor, which is the same as or different from the first silicon-containing precursor, into the processing chamber at a second temperature of about 1000°C to about 1400°C to form a second silicon carbide layer on the first silicon carbide layer.

[0018] In some embodiments, a method includes introducing a first silicon-containing precursor into a processing chamber at a first temperature of about 1000°C to about 1400°C. The method further includes reducing the first temperature to about 800°C to a second temperature less than 1000°C to form a first silicon carbide layer on a substrate. The method also includes introducing a second silicon-containing precursor, which is the same as or different from the first silicon-containing precursor, into the processing chamber at a third temperature of about 1000°C to about 1400°C, the same as or different from the first temperature, to form a second silicon carbide layer on the first silicon carbide layer.

[0019] Examples of processing chambers suitable for benefiting from exemplary aspects of this disclosure include CVD chambers available from Applied Materials, Inc., located in Santa Clara, California. It is contemplated that other processing chambers and / or processing platforms, including those from other manufacturers, may also be suitable for benefiting from aspects of this disclosure.

[0020] Formation of the buffer layer and polycrystalline SiC

[0021] In some implementations, such as Figure 1As shown, a method 100 for forming polycrystalline silicon carbide (SiC) includes introducing a first silicon-containing precursor into a processing chamber (102) (chemical vapor deposition chamber) at a first temperature (e.g., substrate temperature) of about 800°C to less than 1000°C (e.g., about 850°C to about 950°C, or about 850°C to about 900°C) and / or a chamber pressure of about 1 mTorr to about 760 Torr to deposit a first SiC layer on a substrate. The first SiC layer may have a Si content of about 40 mol% to about 100 mol%, such as about 40 mol% to about 70 mol%, or about 70 mol% to about 100 mol%. Compared to polycrystalline SiC deposited directly onto a substrate (such as graphite), excess silicon can provide the substrate with a first SiC layer having reduced compressive strain.

[0022] In some embodiments that can be combined with other embodiments, the coefficient of thermal expansion (CTE) of the first SiC layer is, as determined by ASTM E228-17 (Standard Test Method for Linear Thermal Expansion of Solid Materials With a Push-Rod Dilatometer), about 3 × 10E-6 / ℃ to about 5 × 10E-6 / ℃, such as about 3 × 10E-6 / ℃ to about 4 × 10E-6 / ℃, or about 4 × 10E-6 / ℃ to about 5 × 10E-6 / ℃. In some embodiments that can be combined with other embodiments, the substrate (such as graphite) has a coefficient of thermal expansion (CTE) of about 4 × 10E-6 / ℃ to about 8 × 10E-6 / ℃, such as about 4 × 10E-6 / ℃ to about 6 × 10E-6 / ℃, or about 6 × 10E-6 / ℃ to about 8 × 10E-6 / ℃, when measured by ASTM E228-17.

[0023] In some embodiments that can be combined with other embodiments, the first SiC layer has the properties measured by ASTM E1426-14 (Standard Test Method for Determining the X-Ray Elastic Constants for Use in the Measurement of Residual Stress Using X-Ray Diffraction Techniques). to approximately lattice constant Such as to approximately lattice constant And / or approximately when measured by ASTM E1426-14 to approximately lattice constant Such as to approximately lattice constant In some embodiments that can be combined with other implementations, the substrate (such as graphite) has approximately [value missing] when measured by ASTM E1426-14. to approximately lattice constant Such as to approximately lattice constant And / or approximately when measured by ASTM E1426-14 to approximately lattice constant Such as to approximately lattice constant

[0024] The first silicon carbide layer may have a thickness of about 1 micrometer to less than 200 micrometers, such as a thickness of about 20 micrometers to about 150 micrometers, or a thickness of about 30 micrometers to about 100 micrometers. The first SiC layer may be amorphous SiC. The substrate may be any suitable substrate, such as a graphite substrate, for example, a graphite substrate.

[0025] The first SiC layer can act as a buffer layer, preventing SiC tendrils from forming into the graphite. This facilitates the removal of graphite from the SiC during subsequent removal processes, reduces the roughness of the formed SiC substrate, and minimizes warping or bending of the SiC substrate when the graphite is removed. Reduced warping or bending provides for less material (e.g., warped portions of the SiC substrate) that needs to be removed from the SiC substrate after the deposited SiC is removed from the substrate (e.g., ashing).

[0026] The first silicon-containing precursor may be a chlorosilane, such as methyltrichlorosilane (CH3SiCl3), dimethyldichlorosilane (Si(CH3)2Cl2), trimethylsilylchloride ((CH3)3SiCl), or a combination thereof. Alternatively, silane (SiH4), trichlorosilane (HSiCl3), dichlorosilane (H2SiCl2), silicon tetrachloride (SiCl4), or a combination thereof may be used as the first silicon-containing precursor in combination with a hydrocarbon. The hydrocarbon may be propane, butane, pentane, acetylene, or a combination thereof. In some embodiments that can be combined with other embodiments, a mixture of silane and hydrocarbon is introduced into the processing chamber. Additionally or alternatively, the hydrocarbon is introduced directly into the processing chamber (without being mixed with the silane). In some embodiments that can be combined with other embodiments, the temperature is varied while changing (decreasing or increasing) the silane to hydrocarbon ratio, which provides additional flexibility in the Si:C molar ratio of the deposited SiC and CTE tuning.

[0027] Hydrogen (H2) or nitrogen (N2) can also be introduced into the processing chamber substantially simultaneously with the first silicon-containing precursor. For example, a mixture of the first silicon-containing precursor and hydrogen can be introduced into the processing chamber. The mixture of silicon-containing precursor and hydrogen can be obtained by introducing hydrogen into a container holding the silicon-containing precursor, for example by bubbling hydrogen through the silicon-containing precursor in the container and transferring the mixture into the processing chamber. Alternatively or additionally, hydrogen can be introduced directly into the processing chamber (not as a mixture with the silicon-containing precursor).

[0028] The flow rate of the silicon-containing precursor (or a mixture containing the silicon-containing precursor and / or hydrocarbons and / or hydrogen) entering the processing chamber can be from about 2 standard liters per minute (slpm) to about 200 slpm, such as from about 40 slpm to about 180 slpm, such as from about 60 slpm to about 160 slpm, or from about 2 slpm to about 45 slpm. The flow rate can be controlled using any suitable flow meter, such as those from Sierra Instruments Digital MFC.

[0029] The method disclosed herein may include: during the deposition of a first SiC layer, changing (e.g., increasing or decreasing) a first temperature to a second temperature, such that the first layer is formed as a gradient buffer layer. Depositing the buffer layer at a graded temperature (800°C–1200°C) reduces material mismatch between the subsequently deposited polycrystalline silicon carbide and the substrate (e.g., graphite) due to the coefficient of thermal expansion of the substrate. For example, the buffer layer deposited at a gradually increasing temperature shrinks less (compared to deposition without a gradient temperature) when the substrate is eventually cooled or undergoes further heat treatment after polycrystalline silicon carbide deposition. Increasing the temperature during the deposition of the first SiC layer provides a first SiC layer having a “silicon-rich” side close to the substrate and an exposed “carbon-rich” side (wherein the carbon-rich side will be close to the second SiC layer after deposition). In contrast, lowering the temperature during the deposition of the first SiC layer provides a first SiC layer having a “carbon-rich” side close to the substrate and an exposed “silicon-rich” side (wherein the silicon-rich side will be close to the second SiC layer after the second SiC layer is deposited).

[0030] For example, in some embodiments, the Si content of the silicon-rich surface may be from about 50 mol% to about 100 mol%, such as from about 50 mol% to about 75 mol%, or from about 75 mol% to about 100 mol% (when measured at a depth of 0 to 1 micrometer of the silicon-rich surface), and the carbon content of the carbon-rich surface may be from about 50 mol% to about 100 mol%, such as from about 50 mol% to about 75 mol%, or from about 75 mol% to about 100 mol% (when measured at a depth of 0 to 1 micrometer of the carbon-rich surface).

[0031] It has been found that deposition at temperatures below 1000°C promotes the formation of silicon-rich SiC, while deposition at temperatures above 1125°C promotes the formation of carbon-rich SiC. Interestingly, even when a single precursor is used as the silicon and carbon source for forming the first SiC layer, both silicon-rich and carbon-rich surfaces of the first SiC layer can be formed.

[0032] As a supplement to or alternative to raising the temperature during the deposition of the first SiC layer, the first SiC layer can be deposited at a first temperature, followed by annealing at an annealing temperature. The annealing step of the first SiC layer can be performed at a temperature of about 1000°C or higher, such as at a temperature of about 1000°C to about 1300°C, or at a temperature of about 1050°C to about 1200°C.

[0033] The first SiC layer may be amorphous SiC, and the increased heat (during deposition or by reaching a second temperature through post-deposition annealing) can increase the density of the first SiC layer. In some embodiments, the first SiC layer (deposited at elevated temperatures) has a density of approximately 2.3 g / cm³ when measured by ASTM C 559. 3 Approximately 3.21 g / cm³ 3 The density of the first SiC layer is high. A dense first SiC layer can provide a thin SiC layer without substantial tendrils forming into the porous substrate (such as graphite), thereby improving the removal of the deposited SiC from the substrate and reducing the surface roughness of the deposited SiC after removal from the substrate. In some embodiments that can be combined with other embodiments, the deposited SiC has a surface roughness of about 0.5 micrometers to about 3 micrometers.

[0034] Method 100 further includes introducing a second silicon-containing precursor (same as or different from the first silicon-containing precursor) into a processing chamber (104) at a temperature of about 1000°C to about 1400°C, such as about 1125°C to about 1300°C (e.g., a third temperature after raising the first temperature to the second temperature) to deposit a second SiC layer on the first SiC layer. The second SiC layer may be polycrystalline SiC.

[0035] The Si:C molar ratio of the second SiC layer is from about 0.8 to about 1.2, such as from about 0.8 to about 1, such as from about 0.85 to about 0.95. The second SiC layer can have a thickness of from about 40 micrometers to about 20 millimeters, such as from about 100 micrometers to about 1.5 millimeters, such as from about 200 micrometers to about 400 micrometers. It should be noted that other thicknesses are also expected to be acceptable.

[0036] Furthermore, due to the characteristics (e.g., density) of the first SiC layer, it can serve as a seed layer for the polycrystalline growth of the second SiC layer and for controlling the grain size of the resulting polycrystalline SiC. In some embodiments, the second SiC layer is a polycrystalline SiC with an average grain size of about 1 micrometer to about 100 micrometers when measured by a microscope. In some embodiments, the coefficient of thermal expansion (CTE) of the second SiC layer is about 1 × 10⁻⁶ / °C to about 4 × 10⁻⁶ / °C, such as about 2 × 10⁻⁶ / °C to about 3 × 10⁻⁶ / °C, or about 3 × 10⁻⁶ / °C to about 4 × 10⁻⁶ / °C, when measured by ASTM E228-17 (Standard Test Method for Linear Thermal Expansion of Solid Materials with Push Rod Dilatometer). In some embodiments, the second SiC layer has a CTE of about 1 × 10⁻⁶ / °C when measured by ASTM E1426-14. to approximately lattice constant Such as to approximately lattice constant And / or when measured by ASTM E1426-14 approximately to approximately lattice constant Such as about 4 to approximately lattice constant

[0037] The second silicon-containing precursor may be a chlorosilane, such as methyltrichlorosilane (CH3SiCl3), dimethyldichlorosilane (Si(CH3)2Cl2), trimethylsilylchloride ((CH3)3SiCl), or combinations thereof. Alternatively, silane (SiH4), trichlorosilane (HSiCl3), dichlorosilane (H2SiCl2), silicon tetrachloride (SiCl4), or combinations thereof may be combined with a hydrocarbon as the second silicon-containing precursor. The hydrocarbon may be propane, butane, pentane, acetylene, or combinations thereof. In some embodiments, a mixture of silane and hydrocarbon is introduced into the processing chamber. Alternatively or separately, the hydrocarbon is introduced directly into the processing chamber (without being mixed with the silane).

[0038] Hydrogen (H2) and the second silicon-containing precursor can also be introduced into the processing chamber substantially simultaneously. For example, a mixture of the second silicon-containing precursor and hydrogen can be introduced into the processing chamber. The mixture of silicon-containing precursor and hydrogen can be obtained by introducing hydrogen into a tank containing the silicon-containing precursor, for example by bubbling hydrogen through the silicon-containing precursor in the tank and transferring the mixture into the processing chamber. Alternatively or alternatively, hydrogen can be introduced directly into the processing chamber (without being mixed with the silicon-containing precursor).

[0039] The flow rate of the second silicon-containing precursor (or a mixture containing the second silicon-containing precursor and / or hydrocarbons and / or hydrogen) entering the processing chamber can be from about 2 slpm to about 200 slpm, from about 25 slpm to about 200 slpm, from about 40 slpm to about 180 slpm, from about 60 slpm to about 160 slpm, or from about 25 slpm to about 45 slpm. The flow rate can be controlled using any suitable flow meter (such as those from SILER Instruments Digital MFC).

[0040] Figure 2This is a flowchart of method 200. Method 200 includes: introducing a first silicon-containing precursor into a processing chamber (202) at a first temperature of about 1000°C to about 1400°C. Method 200 includes: reducing the first temperature (204) to about 800°C to a second temperature less than 1000°C (such as about 850°C to about 950°C, such as about 850°C to about 900°C) to form a first silicon carbide layer on a substrate. Method 200 includes: introducing a second silicon-containing precursor, which is the same as or different from the first silicon-containing precursor, into a processing chamber (206) at a third temperature of about 1000°C to about 1400°C, the same as or different from the first temperature, to form a second silicon carbide layer on the first silicon carbide layer.

[0041] Figure 3 This is a schematic cross-sectional view of a multilayer stack 300. The multilayer stack 300 includes a substrate 302 and a first silicon carbide layer 304 disposed on the substrate. The multilayer stack includes a second silicon carbide layer 306 disposed on the first silicon carbide layer 304. The first silicon carbide layer 304 may have a thickness of about 1 micrometer to less than about 200 micrometers. The second silicon carbide layer 306 may have a thickness of about 40 micrometers to about 1.5 millimeters.

[0042] The method disclosed herein may further include removing deposited SiC (e.g., a second SiC layer and a first SiC layer) from a substrate. Removal can be performed using any suitable method, such as peeling, sawing, O2 ashing, or a combination thereof. For example, O2 ashing may include plasma or thermal O2 ashing to decompose the organic portion of the sample. For example, graphite can react with oxygen to decompose, while SiC is substantially (if not completely) unreacted. O2 ashing can be performed at temperatures from about 600°C to about 1000°C.

[0043] Because these treatments of this disclosure provide reduced stress / strain between the SiC deposited on the substrate (e.g., the second SiC layer and the first SiC layer), annealing of the deposited SiC is merely optional. However, in some embodiments, the deposited SiC may be annealed. For example, annealing can be performed after CVD deposition, which can release thermal stress on the SiC layer. Annealing of the deposited SiC can be performed before or after removing the deposited SiC from the substrate. Annealing of the deposited SiC can be performed at temperatures of about 1000°C or higher, such as from about 1000°C to about 1300°C, such as from about 1050°C to about 1200°C. In some embodiments, the density of the second SiC layer (after annealing) is about 2.3 g / cm³, as measured by ASTM C 559. 3 Approximately 3.21 g / cm³ 3.

[0044] After the deposited SiC is removed, the first SiC layer can be removed from the second SiC layer, for example, by O2 ashing, sawing, or similar processes. Because the first SiC layer can be thin, the amount of SiC removed from the second SiC layer is much less than that removed using conventional SiC deposition techniques, for example, due to reduced "tendril" formation. O2 ashing may involve exposing the first SiC layer (after removal from the graphite substrate) to oxygen plasma. The oxygen plasma can be formed in a remote plasma source or in situ within a processing chamber.

[0045] The processing described in this disclosure also provides polycrystalline SiC substrates (with or without a first SiC layer) that exhibit reduced warpage or bending compared to conventional as-deposited SiC substrates. In some embodiments, the polycrystalline SiC substrates of this disclosure exhibit warpage and / or bending (both as-deposited and as-removed from the substrate) of approximately 50 micrometers to approximately 1 millimeter when measured by ASTM F534 (Standard Test Method for Bow of Silicon).

[0046] The polycrystalline SiC substrates of this disclosure have lower resistivity than monocrystalline SiC substrates. In some embodiments, the polycrystalline SiC substrates have a resistivity of about 0.005 ohm-cm to about 50 ohm-cm when measured by the Standard Test Method for Sheet Resistance Uniformity Evaluation by In-Line Four-Point Probe with the Dual-Configuration Procedure (ASTM F1529-97).

[0047] Graphite substrate

[0048] Graphite substrates can be made from any suitable graphite element, such as by cutting graphite into the desired size and shape.

[0049] In some embodiments, the graphite substrate has a purity of at least 99%.

[0050] The graphite substrate may have pinholes, such as pinholes having an average pinhole size (pinhole diameter) of about 0.4 μm to about 5 μm. The graphite substrate may have a surface pinhole diameter of about 10 μm or less. The graphite substrate may have a porosity of about 6% to about 15%, such as about 6% to about 13%, such as about 9% to about 11.5%.

[0051] Graphite can be grain-type, super-fine grain-type, and / or ultra-fine grain-type. Such graphite grain types indicate that the graphite has an exceptionally fine grain size. In some embodiments, the graphite has an average grain size of about 0.05 mm or less, such as about 0.04 mm or less, about 0.03 mm or less, or about 0.015 mm or less.

[0052] Graphite substrates can have a density of approximately 1.5 g / cm³. 3 Or higher densities, such as 1.7 g / cm³ 3 Or higher densities, such as 1.75 g / cm³ 3 Or higher density.

[0053] Grain size, pore size / diameter, and porosity can be determined using scanning electron microscopy (SEM). Porosity can be calculated by measuring the number of pores per unit weight (cm²) of the graphite substrate. 3 (g / cm³) and bulk density (g / cm³) 3 The porosity is obtained by multiplying the volume of the two components. Therefore, porosity can be expressed as [volume / volume] in volumetric terms.

[0054] The (bulk) density can be obtained by dividing the mass of a graphite sample by its volume.

[0055] Silicon carbide coated substrate

[0056] This disclosure further provides silicon carbide-coated substrates. Silicon carbide-coated substrates can be formed using the methods of this disclosure. For example, in embodiments where the deposited SiC (e.g., a second SiC layer and a first SiC layer) is not removed from the substrate after SiC deposition, silicon carbide-coated substrates can be produced.

[0057] In some implementations, the substrate can be any suitable component of the processing chamber. For example, the substrate may be a wafer carrier, a base, a lifting rod, or a preheating ring.

[0058] Additional aspects

[0059] This disclosure provides in particular aspects, each of which may be considered to optionally include any alternative aspects.

[0060] Clause 1. A method comprising the following steps:

[0061] A first silicon-containing precursor is introduced into a processing chamber at a first temperature of approximately 800°C to less than 1000°C to form a first silicon carbide layer on a substrate; and

[0062] A second silicon-containing precursor, which is the same as or different from the first silicon-containing precursor, is introduced into the processing chamber at a second temperature of about 1000°C to about 1400°C to form a second silicon carbide layer on the first silicon carbide layer.

[0063] Clause 2. The method as described in Clause 1, wherein the first silicon carbide layer is amorphous and the second silicon carbide layer is polycrystalline.

[0064] Clause 3. The method as described in Clause 1 or 2, wherein the second silicon carbide layer has 3C crystallinity.

[0065] Clause 4. The method of any one of Clauses 1 to 3, wherein the substrate is graphite.

[0066] Clause 5. The method as described in any one of Clauses 1 to 4, wherein the first temperature is about 850°C to about 950°C.

[0067] Clause 6. The method as described in any one of Clauses 1 to 5, wherein the second temperature is about 1125°C to about 1300°C.

[0068] Clause 7. The method of any one of Clauses 1 to 6 further includes the step of raising the first temperature to a third temperature while forming the first silicon carbide layer.

[0069] Clause 8. The method as described in any one of Clauses 1 to 7, wherein the third temperature is about 1125°C to about 1200°C.

[0070] Clause 9. The method as described in any one of Clauses 1 to 8, wherein the first silicon carbide layer has:

[0071] A first surface, adjacent to the substrate, has a Si content of about 50 mol% to about 100 mol%, such as about 50 mol% to about 75 mol%, or about 75 mol% to about 100 mol% (when measured at a depth of 0 micrometers to 1 micrometer on the first surface).

[0072] The second surface, which is close to the second silicon carbide layer, has a carbon content of about 50 mol% to about 100 mol%, such as about 50 mol% to about 75 mol%, or about 75 mol% to about 100 mol% (when measured at a depth of 0 micrometers to 1 micrometer on the second surface).

[0073] Clause 10. The method of any one of Clauses 1 to 9, wherein the first silicon carbide layer has a Si content of about 75 mol% to about 100 mol%.

[0074] Clause 11. The method as described in any one of Clauses 1 to 10, wherein the first silicon carbide layer has a content of approximately 2.3 g / cm³ when measured by ASTM C 559. 3 Approximately 3.21 g / cm³ 3 The density.

[0075] Clause 12. The method as described in any one of Clauses 1 to 11, wherein:

[0076] When measured by ASTM E228-17, the coefficient of thermal expansion of the first silicon carbide layer is approximately 3 × 10⁻⁶ / ℃ to approximately 5 × 10⁻⁶ / ℃; and

[0077] When measured by ASTM E228-17, the substrate has a coefficient of thermal expansion of approximately 4 × 10E-6 / ℃ to approximately 8 × 10E-6 / ℃.

[0078] Clause 13. The method of any one of Clauses 1 to 12, wherein the second silicon carbide layer has a coefficient of thermal expansion (CTE) of about 1 × 10E-6 / ℃ to about 4 × 10E-6 / ℃ when measured by ASTM E228-17.

[0079] Clause 14. The method as described in any one of Clauses 1 to 13, wherein:

[0080] The first silicon carbide layer has approximately [value missing] when measured by ASTM E1426-14. to approximately lattice constant and approximately when measured by ASTM E1426-14 to approximately lattice constant and

[0081] The substrate has approximately [a certain value] when measured by ASTM E1426-14. to approximately lattice constant and approximately when measured by ASTM E1426-14 to approximately lattice constant

[0082] Clause 15. The method of any one of Clauses 1 to 14, wherein the second silicon carbide layer has approximately [value missing] when measured by ASTM E1426-14. to approximately lattice constant and approximately when measured by ASTM E1426-14 to approximately lattice constant

[0083] Clause 16. The method as described in any one of Clauses 1 to 15, wherein:

[0084] The first silicon carbide layer has a thickness of approximately 1 micrometer to less than approximately 200 micrometers; and

[0085] The second silicon carbide layer has a thickness of approximately 40 micrometers to approximately 1.5 millimeters.

[0086] Clause 17. The method of any one of Clauses 1 to 16, wherein the first silicon-containing precursor is dimethyldichlorosilane.

[0087] Clause 18. The method of any one of Clauses 1 to 17 further comprises the step of introducing hydrogen gas and the first silicon-containing precursor substantially simultaneously into the processing chamber.

[0088] Clause 19. The method as described in any one of Clauses 1 to 18, wherein:

[0089] The first silicon-containing precursor is SiH4; and

[0090] The method further includes the following steps: introducing the hydrocarbon and the first silicon-containing precursor substantially simultaneously into the processing chamber.

[0091] Clause 20. The method as described in any one of Clauses 1 to 19, wherein the hydrocarbon is propane.

[0092] Clause 21. The method of any one of Clauses 1 to 20 further comprises the step of removing the first silicon carbide layer and the second silicon carbide layer from the substrate to form a silicon carbide substrate, wherein the silicon carbide substrate has a warpage or curvature of about 50 micrometers to about 1 millimeter as measured by ASTM F534.

[0093] Clause 22. The method of any one of Clauses 1 to 21, wherein the substrate is selected from the group consisting of: wafer carrier, base, lifting rod, and combinations thereof.

[0094] Clause 23. A method comprising the following steps:

[0095] The first silicon-containing precursor is introduced into the processing chamber at a first temperature of about 1000°C to about 1400°C;

[0096] The first temperature is lowered to a second temperature of approximately 800°C to <1000°C to form a first silicon carbide layer on the substrate; and

[0097] A second silicon-containing precursor, which is the same as or different from the first silicon-containing precursor, is introduced into the processing chamber at a third temperature, which is the same as or different from the first temperature, at a temperature of about 1000°C to about 1400°C, so as to form a second silicon carbide layer on the first silicon carbide layer.

[0098] Clause 24. The method as described in Clause 23, wherein the substrate is graphite.

[0099] Clause 25. The method as described in Clause 23 or 24, wherein the second temperature is about 850°C to about 950°C.

[0100] Clause 26. The method as described in any one of Clauses 23 to 25, wherein the first temperature is about 1125°C to about 1300°C.

[0101] Clause 27. The method of any one of Clauses 23 to 26, wherein the first silicon carbide layer has:

[0102] A first surface, adjacent to the substrate, has a Si content of about 50 mol% to about 100 mol%, such as about 50 mol% to about 75 mol%, or about 75 mol% to about 100 mol% (when measured at a depth of 0 micrometers to 1 micrometer on the first surface).

[0103] The second surface, which is close to the second silicon carbide layer, has a carbon content of about 50 mol% to about 100 mol%, such as about 50 mol% to about 75 mol%, or about 75 mol% to about 100 mol% (when measured at a depth of 0 micrometers to 1 micrometer on the second surface).

[0104] Clause 28. The method of any one of Clauses 23 to 27, wherein the substrate is selected from the group consisting of: wafer carrier, base, lifting rod, and combinations thereof.

[0105] Clause 29. A multi-layered stack comprising:

[0106] Substrate;

[0107] A first silicon carbide layer, the first silicon carbide layer being disposed on the substrate; and

[0108] A second silicon carbide layer is disposed on the first silicon carbide layer, wherein:

[0109] The first silicon carbide layer has a thickness of about 1 micrometer to less than about 200 micrometers, and

[0110] The second silicon carbide layer has a thickness of approximately 40 micrometers to approximately 1.5 millimeters.

[0111] Clause 30. A multi-layered stack as described in Clause 29, wherein:

[0112] When measured by ASTM E228-17, the coefficient of thermal expansion of the first silicon carbide layer is approximately 3 × 10⁻⁶ / ℃ to approximately 5 × 10⁻⁶ / ℃; and

[0113] When measured by ASTM E228-17, the substrate has a coefficient of thermal expansion of approximately 4 × 10E-6 / ℃ to approximately 8 × 10E-6 / ℃.

[0114] Clause 31. A multilayer stack as described in Clause 29 or 30, wherein the second silicon carbide layer has a coefficient of thermal expansion (CTE) of about 1 × 10E-6 / ℃ to about 4 × 10E-6 / ℃ when measured by ASTM E228-17.

[0115] Clause 32. A multi-layered stack as described in any one of Clauses 29 to 31, wherein:

[0116] The first silicon carbide layer has approximately [value missing] when measured by ASTM E1426-14. to approximately lattice constant and approximately when measured by ASTM E1426-14 to approximately lattice constant and

[0117] The substrate has approximately [a certain value] when measured by ASTM E1426-14. to approximately lattice constant and approximately when measured by ASTM E1426-14 to approximately lattice constant

[0118] Clause 33. The multilayer stack as described in any one of Clauses 29 to 32, wherein the second silicon carbide layer has approximately [value missing] when measured by ASTM E1426-14. to approximately lattice constant and approximately when measured by ASTM E1426-14 to approximately lattice constant

[0119] Clause 34. A multilayer stack as described in any one of Clauses 29 to 33, wherein the first silicon carbide layer is amorphous and the second silicon carbide layer is polycrystalline.

[0120] Clause 35. The multilayer stack as described in any one of Clauses 29 to 34, wherein the first silicon carbide layer has:

[0121] A first surface, adjacent to the substrate, has a Si content of about 50 mol% to about 100 mol%, such as about 50 mol% to about 75 mol%, or about 75 mol% to about 100 mol% (when measured at a depth of 0 micrometers to 1 micrometer on the first surface).

[0122] The second surface, which is close to the second silicon carbide layer, has a carbon content of about 50 mol% to about 100 mol%, such as about 50 mol% to about 75 mol%, or about 75 mol% to about 100 mol% (when measured at a depth of 0 micrometers to 1 micrometer on the second surface).

[0123] Clause 36. The method of any one of Clauses 29 to 35, wherein the first silicon carbide layer is amorphous and the second silicon carbide layer is polycrystalline.

[0124] Clause 37. The method of any one of Clauses 29 to 36, wherein the substrate is graphite.

[0125] Clause 38. The method of any one of Clauses 29 to 37, wherein the first silicon carbide layer has:

[0126] A first surface, adjacent to the substrate, has a Si content of about 50 mol% to about 100 mol%, such as about 50 mol% to about 75 mol%, or about 75 mol% to about 100 mol% (when measured at a depth of 0 micrometers to 1 micrometer on the first surface).

[0127] The second surface, which is close to the second silicon carbide layer, has a carbon content of about 50 mol% to about 100 mol%, such as about 50 mol% to about 75 mol%, or about 75 mol% to about 100 mol% (when measured at a depth of 0 micrometers to 1 micrometer on the second surface).

[0128] Clause 39. The method of any one of Clauses 29 to 38, wherein the first silicon carbide layer has a Si content of about 40 mol% to about 100 mol%, such as a Si content of about 40 mol% to about 70 mol%, or a Si content of about 70 mol% to about 100 mol%.

[0129] Clause 40. The method as described in any one of Clauses 29 to 39, wherein the first silicon carbide layer has a content of approximately 2.3 g / cm³ when measured by ASTM C559. 3 Approximately 3.21 g / cm³ 3 The density.

[0130] In general, this disclosure provides a method for forming a polycrystalline silicon carbide coated substrate. The silicon carbide substrate (and the method thereof) may provide a buffer layer disposed between the substrate and the polycrystalline silicon carbide layer. The buffer layer may be, for example, amorphous silicon carbide. The buffer layer reduces the stress / strain mismatch between the substrate and the polycrystalline silicon carbide layer (compared to polycrystalline silicon carbide disposed directly on the substrate). The reduced stress / strain provides a number of benefits, including (1) reduced warpage or bending of the polycrystalline silicon carbide (which occurs as soon as it is removed from the substrate to form the polycrystalline silicon carbide substrate), and (2) reduced removal of excess silicon carbide from the polycrystalline silicon carbide to obtain a substantially flat polycrystalline silicon carbide substrate due to the reduced warpage or bending.

[0131] Although the foregoing describes embodiments of this disclosure, other and further embodiments of this disclosure may be designed without departing from the basic scope of this disclosure.

Claims

1. A method for forming a silicon carbide-coated substrate, comprising the following steps: A first silicon-containing precursor is introduced into a processing chamber at a first temperature of 800°C to less than 1000°C to form an amorphous first silicon carbide layer on a substrate; and At a second temperature of 1000°C to 1400°C, a second silicon-containing precursor, which is the same as or different from the first silicon-containing precursor, is introduced into the processing chamber to form a polycrystalline second silicon carbide layer on the amorphous first silicon carbide layer.

2. The method of claim 1, wherein the substrate is graphite.

3. The method of claim 1, wherein: The first temperature is 850°C to 950°C, and The second temperature is 1125°C to 1300°C.

4. The method of claim 1, further comprising the following steps: While introducing the first silicon-containing precursor into the processing chamber, the first temperature is raised to a third temperature.

5. The method of claim 4, wherein the third temperature is from 1125°C to 1200°C.

6. The method of claim 4, wherein the first silicon carbide layer comprises: A first surface, adjacent to the substrate, has a Si content of 50 mol% to 100 mol% when measured at a depth of 0 to 1 micrometer. The second surface, which is close to the polycrystalline second silicon carbide layer, has a carbon content of 50 mol% to 100 mol% when measured at a depth of 0 to 1 micrometer.

7. The method of claim 1, wherein the amorphous first silicon carbide layer has a carbon content of 50 mol% to 100 mol%.

8. The method of claim 1, wherein the amorphous first silicon carbide layer has a density of 2.3 g / cm 3 to 3.21 g / cm 3 when determined by ASTM C 559.

9. The method of claim 1, wherein: When measured by ASTM E228-17, the coefficient of thermal expansion of the amorphous first silicon carbide layer is 3 × 10E-6 / ℃ to 5 × 10E-6 / ℃; and When measured by ASTM E228-17, the substrate has a coefficient of thermal expansion of 4×10E-6 / ℃ to 8×10E-6 / ℃.

10. The method of claim 9, wherein the coefficient of thermal expansion (CTE) of the polycrystalline second silicon carbide layer is from 1 × 10E-6 / ℃ to 4 × 10E-6 / ℃ as measured by ASTM E228-17.

11. The method of claim 1, wherein: The amorphous first silicon carbide layer has a lattice constant a (Å) of 4 Å to 7 Å as measured by ASTM E1426-14 and a lattice constant c (Å) of 4 Å to 7 Å as measured by ASTM E1426-14; and The substrate has a lattice constant a (Å) of 1 Å to 4 Å as determined by ASTM E1426-14 and a lattice constant c (Å) of 5 Å to 8 Å as determined by ASTM E1426-14.

12. The method of claim 11, wherein the polycrystalline second silicon carbide layer has a lattice constant a (Å) of 3 Å to 6 Å as determined by ASTM E1426-14 and a lattice constant c (Å) of 3 Å to 6 Å as determined by ASTM E1426-14.

13. The method of claim 1, wherein: The amorphous first silicon carbide layer has a thickness of 1 micrometer to less than 200 micrometers; and The polycrystalline second silicon carbide layer has a thickness of 40 micrometers to 1.5 millimeters.

14. A method for forming a silicon carbide-coated substrate, comprising the following steps: The first silicon-containing precursor is introduced into the processing chamber at a first temperature of 1000°C to 1400°C; The first temperature is lowered to a second temperature of 800°C to less than 1000°C to form an amorphous first silicon carbide layer on the substrate. as well as A second silicon-containing precursor, which is the same as or different from the first silicon-containing precursor, is introduced into the processing chamber at a third temperature of 1000°C to 1400°C, which is the same as or different from the first temperature, to form a polycrystalline second silicon carbide layer on the amorphous first silicon carbide layer.

15. The method of claim 14, wherein the substrate is graphite.

16. The method of claim 14, wherein: The first silicon-containing precursor is dimethyldichlorosilane, and The method further includes the following steps: introducing hydrogen gas and the first silicon-containing precursor substantially simultaneously into the processing chamber.

17. The method of claim 14, wherein: The first silicon-containing precursor is SiH4; and The method further includes the following steps: introducing the hydrocarbon and the first silicon-containing precursor substantially simultaneously into the processing chamber.

18. The method of claim 14, further comprising the following steps: The amorphous first silicon carbide layer and the polycrystalline second silicon carbide layer are removed from the substrate to form a silicon carbide substrate, wherein the silicon carbide substrate has a warpage or bend of 50 micrometers to 1 millimeter as measured by ASTM F534.

19. A multi-layered stack, comprising: Graphite substrate; An amorphous first silicon carbide layer is disposed on the substrate. as well as A polycrystalline second silicon carbide layer is disposed on the amorphous first silicon carbide layer, wherein: The amorphous first silicon carbide layer has a thickness of 1 micrometer to less than 200 micrometers, and The polycrystalline second silicon carbide layer has a thickness of 40 micrometers to 1.5 millimeters.

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