A Method for Remote Online Update of FPGA Based on PowerPC

Abstract

The present application provides an FPGA remote online update method based on PowerPC, belonging to the technical field of embedded computer data processing. Specifically, the FPGA uses the BPI mode to load the target file from an external FLASH, and the PowerPC processor receives the target file to be updated from an external interface such as a serial port or an Ethernet, and performs writing to the external FLASH of the FPGA through the local bus interface LBC, so as to realize the solidification of the updated target file in the FLASH. The method of the present application realizes the remote online update of the FPGA without using a programming cable without adding additional hardware circuits, and improves the flexibility in the use and maintenance process of the module.

Description

Technical Field

[0001] This application relates to the field of embedded computer data processing, and in particular to a method for remote online update of FPGA based on PowerPC. Background Art

[0002] Due to its high performance and low power consumption characteristics, PowerPC processors are widely used in the fields of aviation, avionics, and vehicle-mounted embedded computers. At the same time, the requirements for miniaturization and high reliability of embedded computers have led to the wide application of high-performance FPGAs with multiple interface IPs in the design of PowerPC processor modules. In the design, development, and later use and maintenance of PowerPC modules, the update of FPGA programs is inevitable. The traditional FPGA program update requires the use of a dedicated FPGA development environment to perform FPGA update work through a programming cable, and a dedicated JTAG interface needs to be reserved for FPGA update during module design. This traditional FPGA update method brings great inconvenience to the use and maintenance of the entire PowerPC. Therefore, more and more PowerPC design engineers have begun to study methods for remote online update of FPGA.

[0003] The patent "A System and Method for Remote Online Update of FPGA Program Based on DSP" (application number 201811245075.0, publication number 109343888) applied by the Automation Research Institute of China North Industries Corporation and the patent "A Method, System and Device for Online Update of FPGA Board" (application number 201811463889.1, publication number 109542492) applied by Zhengzhou Yunhai Information Technology Co., Ltd. respectively provide two effective solutions for remote online update of FPGA. However, both of the above solutions have an obvious drawback: additional CPLD or management FPGA needs to be added. This not only makes the FPGA online update process more complex, but also reduces the reliability of the module due to the additional circuits added. Summary of the Invention

[0004] In view of this, this application provides a method for remote online update of FPGA based on PowerPC, which solves the problem of remote online loading of PowerPC modules without adding additional hardware circuits.

[0005] A method for remote online update of FPGA based on PowerPC provided by this application adopts the following technical solutions:

[0006] A method for remote online update of FPGA based on PowerPC includes the following steps:

[0007] Build a PowerPC module, including a PowerPC processor, an FPGA, an external FLASH, and a boot FLASH. The PowerPC processor and the FPGA are connected by a local bus controller bus. The FPGA and the external FLASH are connected by a FLASH parallel line. The boot FLASH is communicatively connected to the FPGA;

[0008] Store the update target file in the external FLASH of the FPGA;

[0009] Store a boot file in the boot FLASH;

[0010] The PowerPC processor indirectly accesses the external FLASH of the FPGA through the local bus controller bus. When the PowerPC processor accesses the external FLASH, the FPGA completes the latching of the local bus controller address signal and converts the chip select signal, data signal, read / write signal, and address latching signal of the local bus controller bus into the chip select signal, read / write signal, address, and data of the external Flash bus, realizing the access of the local bus controller to the external Flash;

[0011] Start the remote update program through the debug serial port, load the logic target code from the external Flash into the FPGA, and update the FPGA;

[0012] Load the boot target code into the boot Flash from the external Flash.

[0013] Optionally, the FPGA designs a Flash protection register. The PowerPC processor can only perform a write operation on the Flash when the status of the Flash protection register is in the write enable state. The status of the Flash protection register is only modified in the FPGA remote update program.

[0014] Optionally, the modification of the Flash protection register adopts a two - write access method. The FPGA provides two addresses for the Flash protection register. To modify the status of the Flash protection register, the PowerPC processor needs to first write the access address of the Flash protection register to the first address, and then write the data to be modified to the second address.

[0015] Optionally, the two - write access method and the access address pair of the Flash protection register are only valid for the FPGA remote update program of the PowerPC module.

[0016] Optionally, the PowerPC processor adopts an error detection and error recovery mechanism to calculate the checksum of the target file to be updated in the external Flash and transmit the checksum to the PowerPC processor; the PowerPC processor receives the update file and calculates the checksum of the update file. If the checksums on both sides are not equal, it indicates that there is an error during data transmission. The PowerPC processor notifies the debug PC to retransmit the data and compares the checksums again. If there is still an error, it continues to retransmit. When the number of retransmissions exceeds the specified threshold, the FPGA online update is stopped.

[0017] Optionally, the PowerPC processor caches the target file in the module memory and divides the buffered data into data blocks a1, a2, a3, …, a n and calculates the checksums S1, S2, S3, …, S n for all data blocks respectively. After the PowerPC processor completes the Flash writing, it reads back the data in the Flash and calculates the checksum S ’ 1, S ’ 2, S ’ 3, …, S ’ n for each sector of the read-back data. Then, compare S1, S2, S3, …, S n with S ’ 1, S ’ 2, S ’ 3, …, S ’ n If there exists a sector i such that S i is not consistent with S ’ i record the label i of this sector. After detecting all sectors, if there are error sectors, rewrite the corresponding sectors according to the labels of the error sectors. Repeat the above detection process. If the rewrite counter exceeds the error threshold, it is determined that the FPGA update fails.

[0018] Optionally, before writing the update target file, the PowerPC module backs up the original target file in the Flash; after writing the update target file, if the PowerPC processor detects a writing error and cannot recover the error by rewriting, the PowerPC module will stop the current FPGA online update and restore the original target file in the Flash.

[0019] In summary, the present application includes the following beneficial technical effects:

[0020] The FPGA loads the target file from the external FLASH in BPI mode. The PowerPC processor receives the target file to be updated from external interfaces such as the serial port or Ethernet, and writes to the external FLASH of the FPGA through the local bus interface LBC, realizing the solidification of the updated target file in the FLASH. Without adding additional hardware circuits, this method realizes the remote online update of the FPGA without using a programming cable, improving the flexibility in the use and maintenance process of the module. Description of the Drawings

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0022] Figure 1 It is the structural block diagram of the PowerPC module of the present application;

[0023] Figure 2 It is the timing diagram of the method of the present application;

[0024] Figure 3 It is the flowchart of the method of the present application. Detailed Embodiments

[0025] The embodiments of the present application will be described in detail below with reference to the drawings.

[0026] The following uses specific specific examples to illustrate the implementation manners of the present application. Those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts belong to the scope of protection of the present application.

[0027] Note that the following describes various aspects of embodiments within the scope of the appended claims. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is illustrative only. Based on this application, those skilled in the art should understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects described herein can be used to implement an apparatus and / or practice a method. Additionally, this apparatus and / or method can be implemented using other structures and / or functionality in addition to one or more of the aspects described herein.

[0028] It should also be noted that the diagrams provided in the following embodiments only illustrate the basic concept of this application schematically. The diagrams only show the components related to this application and are not drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and proportion of each component in its actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0029] In addition, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that the aspects described can be practiced without these specific details.

[0030] An embodiment of this application provides a method for remotely and online updating an FPGA based on PowerPC.

[0031] As Figures 1-3 shown, a method for remotely and online updating an FPGA based on PowerPC includes the following steps:

[0032] Establish a PowerPC module, including a PowerPC processor, an FPGA, an external FLASH, and a boot FLASH. The PowerPC processor and the FPGA are connected by a local bus controller bus. The FPGA and the external FLASH are connected by a FLASH parallel line. The boot FLASH is communicatively connected to the FPGA;

[0033] Store an update target file in the external FLASH of the FPGA;

[0034] Store a boot file in the boot FLASH;

[0035] The PowerPC processor indirectly accesses the external FLASH of the FPGA through the local bus controller bus. When the PowerPC processor accesses the external FLASH, the FPGA completes the address signal latching of the local bus controller and converts the chip select signal, data signal, read / write signal, and address latching signal of the local bus controller bus into the chip select signal, read / write signal, address, and data of the external Flash bus, realizing the access of the local bus controller to the external Flash;

[0036] Start the remote update program through the debug serial port, load the logic object code from the external Flash into the FPGA, and update the FPGA;

[0037] Load the startup object code from the external Flash into the startup Flash (Nor Flash).

[0038] This method configures the FPGA loading mode as the BPI mode, which uses a parallel Nor Flash to store the FPGA target file. The FPGA can use a programming cable through the JTAG port to solidify the target file into the Nor Flash. After the FPGA is powered on, it reads data from the NorFlash. After the target file is loaded, it enters the normal working state. When the FPGA is configured and loaded, it reads data from the Nor Flash using the dedicated signals of the BPI mode. These signals include: Flash chip select signal, Flash read / write valid signal, Flash address signal, and Flash data signal. After the FPGA configuration and loading are completed, the above dedicated signals become ordinary signals for the FPGA user to use on their own. This method uses the above pins. When the FPGA is working normally, it generates the write timing required for the Flash by means of the LBC bus signal, realizing the programming of the Flash.

[0039] The PowerPC processor is connected to the FPGA via the LBC bus. The LBC bus signals include chip select signals, read / write enable signals, data / address multiplexed signals, and address latch signals. The LBC bus uses a multiplexed address / data signal line method. Therefore, the FPGA first latches the LBC bus address information using the address latch signal, and converts the latched address signal, data signal, read / write enable signal, and chip select signal into signals corresponding to accessing the Nor Flash. The FPGA uses combinational logic to complete the above signal conversion, without involving signal timing control. The timing control for accessing the Nor Flash is completed by the LBC bus controller of the PowerPC. The LBC bus control can be configured through software, and its configuration process can be divided into two steps: Step 1: Access the LBC bus base register BR (Base Register) to allocate an address space for the Nor Flash and set the corresponding LBC chip select signal for this address space; Step 2: Access the options register OR (options register) of the LBC bus to set the access timing of the Nor Flash. After the LBC bus timing parameters are configured, the PowerPC processor can perform read and write operations on the external Flash of the FPGA via the LBC bus, and further complete sector erasing and programming of the Flash to achieve the Flash programming function.

[0040] The "Flash protection register" is designed inside the FPGA. When the status of the Flash protection register is in the write enable state, the PowerPC processor can perform write operations on the Flash. The status of the Flash protection register can only be modified by the FPGA remote update program. This is used to prevent the "accidental write" operation of the PowerPC to the external Flash of the FPGA. The FPGA will adopt the following mechanism to prevent the "accidental write" operation of the PowerPC:

[0041] 1. The PowerPC initiates an LBC write operation;

[0042] 2. The FPGA determines whether the target of this write operation is the external Flash of the FPGA through the LBC bus chip select signal;

[0043] 3. If the PowerPC performs a write operation on the external Flash of the FPGA, the FPGA checks the status of the "Flash protection register". If the register status is "write prohibited", the FPGA masks this write operation. If the register status is "write enabled", the FPGA performs a bus conversion to complete this write operation.

[0044] The default state of the "Flash protection register" is "write prohibited". The PowerPC can modify the state of the "Flash protection register" through the LBC bus. The "Flash protection register" adopts a "two - write" access method to ensure that the PowerPC processor cannot modify this register randomly. Its access method is that the FPGA provides two addresses to the PowerPC. When accessing the internal registers of the FPGA, it is necessary to first write the address value of the accessed register into the first address, and then write or read the data of the accessed register into the second address to complete the access to the register. This strategy can effectively improve the security of the important status (control) registers inside the FPGA, and the "Flash protection register" belongs to this type of important register.

[0045] The remote online update of the FPGA is completed by the "FPGA remote update program" running inside the PowerPC. Before writing to the external Flash of the FPGA, this program enables the "Flash protection register" in the above - mentioned manner. After completing the writing to the external Flash of the FPGA, it disables this register. The "two - write" access method and access addresses of the "Flash protection register" are only visible to the designers of the "FPGA remote update program" and are transparent to other applications of the PowerPC module, so as to ensure that other applications of the PowerPC module will not modify the external Flash of the FPGA incorrectly. The two - write access method and access addresses of the Flash protection register are only valid for the FPGA remote update program of the PowerPC module. This improves the usage security of the "Flash protection register".

[0046] The "FPGA remote update program" adopts an error detection and error recovery mechanism to avoid the occurrence of the phenomenon that the module cannot work due to incorrect updates, and improves the robustness of the update process.

[0047] Error detection is divided into transmission error detection and programming error detection.

[0048] The target file to be updated is transmitted from the debugging PC to the PowerPC processor through the debugging serial port or the Ethernet port. When transmitting the update file, the debugging PC calculates the checksum S whole , and transmits S whole to the PowerPC. The PowerPC receives the update file and calculates the checksum S ’ whole . If S whole is the same as S ’ wholeIf they are not equal, it indicates that there is an error during data transmission. PowerPC notifies the debugging PC to retransmit the data and compares the checksum again. If there is still an error, continue to retransmit. When the number of retransmissions exceeds the specified threshold, stop the FPGA online update.

[0049] PowerPC caches the target file into the memory and divides the buffered data into data blocks a1, a2, a3, …, a in units of sectors. n , and calculates the checksums S1, S2, S3, …, S of all data blocks respectively. n , after PowerPC finishes Flash programming, it reads back the data in the Flash and calculates the checksum S of each sector of the read-back data at the same time. ’ 1, S ’ 2, S ’ 3, …, S ’ n , compare S1, S2, S3, …, S n and S ’ 1, S ’ 2, S ’ 3, …, S ’ n . If there exists a sector i such that Si and S’i are inconsistent, record the label i of this sector. After all sectors are detected, if there are error sectors, rewrite the corresponding sectors according to the labels of the error sectors. Repeat the above detection process. If the "rewrite counter" exceeds the error threshold, it is determined that the FPGA update fails. Avoid the occurrence of the phenomenon that the module cannot work due to incorrect update and improve the robustness of the whole process.

[0050] After the FPGA update fails, error recovery is required. Before PowerPC programs the Flash, it first reads the original target file in the Flash and makes a backup. When it is determined that the FPGA update fails, it rewrites the backup data to the external Flash of the FPGA to ensure the normal operation of the FPGA.

[0051] In one embodiment, the FPGA remote online update method based on PowerPC includes the following steps:

[0052] Step 1, the debugging serial port (and debugging network port) of the PowerPC module is connected to the debugging PC. The module is powered on and starts up, entering the maintenance state. In this state, start the "FPGA remote update program" through the debugging serial port.

[0053] Step 2, select the update target file transmission method at the debugging PC end. The available data transmission methods are "serial port transmission" and "network port transmission", and start data transmission;

[0054] Step 2-1, after the transmission is completed, the PowerPC calculates the checksum of the received data and compares this checksum with the original data checksum sent by the PC side. If the two are equal, it indicates that the data transmission is correct and the target file burning is prepared.

[0055] Step 2-2, when the two checksums are not equal, it means that a data error occurred during the transmission of the updated target file. The PowerPC first determines whether the retransmission count exceeds the pre-set retransmission threshold. If the retransmission threshold is not reached, the PowerPC requests the peer debugging PC to retransmit the data, and then compares the correctness of the transmitted data again according to Steps 2-1 and 2-2. When the retransmission count is equal to the retransmission threshold value, it means that the error in the data transmission between the debugging PC and the PowerPC cannot be recovered by retransmitting the data. At this time,

[0056] the PowerPC will stop the "FPGA remote update program" and output "Data transmission error, FPGA online update stopped!" on the debugging serial port to prompt the module designer.

[0057] Step 3, the PowerPC prepares to burn the updated target file. The PowerPC reads the original target file of the FPGA from the external Flash of the FPGA and makes a backup. When the burning of the updated target file fails, it can be restored.

[0058] Step 4, the PowerPC checks the status of the "Flash protection register" inside the FPGA through the LBC bus. If the status of this register is "write prohibited", it means that the external Flash of the FPGA is in the write protection state, and the PowerPC cannot perform operations such as erasing and programming on it. The PowerPC sets the

[0059] status of the "Flash protection register" to "write enabled" and starts the operation of burning the updated target file to the Flash.

[0060] Step 4-1, after the Flash burning is completed, the PowerPC reads back the burned data and calculates the checksum of each sector of the read-back data. The checksum of the read-back data and the data cached by the PowerPC is compared in units of sectors. If the two sets of checksums are equal, it means that the data burning is correct and the Flash online update is successful. The PowerPC sets the status of the "Flash protection register" to "write prohibited" and outputs "FPGA update completed!" on the debugging serial port.

[0061] Step 4-2: If there is an inconsistent sector checksum, record the error sector numbers of all inconsistent checksums, and determine whether the number of rewrites exceeds the set Flash rewrite threshold. If the number of rewrites is less than the threshold, rewrite the recorded error sectors and perform the Flash correctness comparison again according to Steps 4-1 and 4-2. When the number of Flash rewrites equals the threshold, the Flash rewrite fails. The PowerPC uses the original FPGA target file backed up in Step 3 to recover the original data of the Flash, outputs "FPGA update failed!" on the debug serial port, and simultaneously sets the status of the "Flash protection register" to "write prohibited".

[0062] As described above, it is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed in the present application should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method for remotely and online updating an FPGA based on PowerPC, characterized in that, The steps are as follows: Establish a PowerPC module, including a PowerPC processor, an FPGA, an external FLASH, and a boot FLASH. The PowerPC processor and the FPGA are connected by a local bus controller bus. The FPGA and the external FLASH are connected by a FLASH parallel line. The boot FLASH is communicatively connected to the FPGA; Store the update target file in the external FLASH of the FPGA; Store a boot file in the boot FLASH; The PowerPC processor indirectly accesses the external FLASH of the FPGA through the local bus controller bus. When the PowerPC processor accesses the external FLASH, the FPGA completes the latching of the local bus controller address signal, and converts the chip select signal, data signal, read / write signal, and address latching signal of the local bus controller bus into the chip select signal, read / write signal, address, and data of the external Flash bus, realizing the access of the local bus controller to the external Flash; Start the remote update program through the debug serial port, load the logic target code from the external Flash into the FPGA, and update the FPGA; Load the boot target code into the boot Flash from the external Flash; The PowerPC processor adopts an error detection and error recovery mechanism, calculates the checksum of the target file to be updated in the external Flash, and transmits the checksum to the PowerPC processor; The PowerPC processor receives the update file and calculates the checksum of the update file. If the checksums on both sides are not equal, it means that there is an error in the data transmission process. The PowerPC processor notifies the debug PC to retransmit the data and compares the checksums again. If there is still an error, continue to retransmit. When the number of retransmissions exceeds the specified threshold, the on-line update of the FPGA is stopped; The PowerPC processor caches the target file into the module memory. Taking sectors as units, the buffered data is divided into data blocks a1, a2, a3, …, a n , and the checksums S1, S2, S3, …, S of all data blocks are calculated respectively n . After the PowerPC processor finishes Flash programming, it reads back the data in the Flash and calculates the checksum S of each sector of the read-back data ’ 1, S ’ 2, S ’ 3, …, S ’ n . For S1, S2, S3, …, S n and S ’ 1, S ’ 2, S ’ 3, …, S ’ n , a comparison is made. If there exists a sector i such that S i and S ’ i are inconsistent, the label i of this sector is recorded. After all sectors are detected, if there are error sectors, the error sectors are reprogrammed according to the labels of the error sectors, and the detection process is repeated. If the reprogramming counter exceeds the error threshold value, it is determined that the FPGA update fails.

2. The method for remotely and online updating an FPGA based on PowerPC according to claim 1, wherein The FPGA designs a Flash protection register. The PowerPC processor can only perform a write operation on the Flash when the status of the Flash protection register is in the write enable state. The status of the Flash protection register is only modified in the FPGA remote update program.

3. The FPGA remote online update method based on PowerPC according to claim 2, wherein The modification of the Flash protection register adopts a two-write access method. The FPGA provides two addresses for the Flash protection register. To modify the status of the Flash protection register, the PowerPC processor needs to first write the access address of the Flash protection register into the first address, and then write the data to be modified into the second address.

4. The method for remotely and online updating an FPGA based on PowerPC according to claim 3, wherein The two-write access method and access address pair of the Flash protection register are only valid for the FPGA remote update program of the PowerPC module.

5. The method for remotely and online updating an FPGA based on PowerPC according to claim 1, wherein Before burning the update target file, the PowerPC module will back up the original target file in the Flash; After the update target file is burned, if the PowerPC processor detects a burning error and the error cannot be recovered by re-burning, the PowerPC module will stop the on-line update of the FPGA this time and restore the original target file in the Flash.

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