A 14-bit sampling accuracy fiber-optic gyroscope signal processing system

Abstract

The present application relates to the field of fiber-optic gyroscope signal processing, in particular to a 14-bit sampling accuracy fiber-optic gyroscope signal processing system, comprising a 14-bit ADC, a data processing subsystem, a 14-bit DAC, a clock reset subsystem, a power management subsystem and an RS422 interface circuit, the 14-bit ADC is electrically connected with the data processing subsystem through a data bus, the data processing subsystem is electrically connected with the 14-bit DAC through the data bus, the RS422 interface circuit is electrically connected with the data processing subsystem through a serial bus, the clock reset subsystem is electrically connected with the 14-bit ADC, the data processing subsystem and the 14-bit DAC through a clock signal and a reset signal respectively, and the power management subsystem supplies power to the 14-bit ADC, the data processing subsystem, the 14-bit DAC and the RS422 interface circuit; the present application solves the problems of high development complexity, large size and high power consumption of the existing system.

Description

Technical Field

[0001] The present invention relates to the field of fiber optic gyroscope signal processing, and in particular to a fiber optic gyroscope signal processing system with 14-bit sampling accuracy. Background Art

[0002] A fiber optic gyroscope (FOG) is an angular rate sensor based on the Sagnac effect. It measures the rotational speed of a fiber optic coil by measuring the optical path difference between two beams of light traveling clockwise and counterclockwise along the coil. Due to its high measurement accuracy, high sensitivity, large dynamic range, small size, light weight, and ease of integration, as well as its broad application prospects in both military and civilian fields, it has become a research hotspot in the field of inertial devices both domestically and internationally in recent years.

[0003] A fiber optic gyroscope signal processing chip structure with 14-bit sampling accuracy integrates the FPGA, ADC, DAC, RS422 and other circuits in the traditional fiber optic gyroscope system into an ASIC chip, realizing the miniaturization of the fiber optic gyroscope and reducing the size and power consumption of the fiber optic gyroscope system. Summary of the Invention

[0004] In response to the above problems, in order to achieve the miniaturization of the fiber optic gyroscope and reduce the volume and power consumption of the fiber optic gyroscope system, the present invention proposes a fiber optic gyroscope signal processing system with 14-bit sampling accuracy, including a 14-bit ADC, a data processing subsystem, a 14-bit DAC, a clock reset subsystem, a power management subsystem and an RS422 interface circuit. The 14-bit ADC is electrically connected to the data processing subsystem via a data bus, the data processing subsystem is electrically connected to the 14-bit DAC via a data bus, the RS422 interface circuit is electrically connected to the data processing subsystem via a serial bus, the clock reset subsystem is electrically connected to the 14-bit ADC, the data processing subsystem and the 14-bit DAC via a clock signal and a reset signal respectively, and the power management subsystem supplies power to the 14-bit ADC, the data processing subsystem, the 14-bit DAC and the RS422 interface circuit respectively.

[0005] Furthermore, the input end of the 14-bit ADC is signal-connected to the chip input port, and the output end of the 14-bit ADC is electrically connected to the data processing subsystem via a data bus.

[0006] Furthermore, the data processing subsystem includes an angular velocity signal modem, a closed-loop controller, a feedback phase shift generator, a square wave bias generator, a serial interface, and an EEPROM read-write circuit. The angular velocity signal modem receives the signal sent by the 14-bit ADC and transmits it to the closed-loop controller; the closed-loop controller generates two identical signals, one of which is connected to the 14-bit DAC through the feedback phase shift generator, and the other signal generates a square wave output through the square wave bias generator; the EEPROM read-write circuit reads the control signals of the angular velocity signal modem, closed-loop controller, feedback phase shift generator, and square wave bias generator after power-on reset is completed; and the serial interface output data is connected to the RS422 interface circuit.

[0007] Furthermore, the input end of the 14-bit DAC is electrically connected to the data processing subsystem via a data bus, and the output end of the 14-bit DAC is output to the chip analog output port.

[0008] Furthermore, the input end of the RS422 interface circuit is electrically connected to the serial port unit in the data processing subsystem via a serial bus, and the output end of the RS422 interface circuit outputs data to a host computer for debugging.

[0009] Furthermore, the power management subsystem is composed of four low-voltage difference linear regulators, which are powered by a 5V power supply. The first low-voltage difference linear regulator provides 3V voltage for the analog part of the 14-bit ADC, and the third low-voltage difference linear regulator provides 3.3V voltage for the data processing subsystem, the 14-bit DAC digital part, and the 14-bit ADC digital part; the second low-voltage difference linear regulator provides 4V voltage for the 14-bit DAC analog part; the fourth low-voltage difference linear regulator provides 3.3V voltage for the clock reset subsystem, the I / O port of the 14-bit DAC and 14-bit ADC, and the peripheral circuits of the chip.

[0010] Furthermore, the four low-voltage difference linear regulators in the electronic management subsystem are powered on in a cascade manner. When the first low-voltage difference linear regulator completes power-on, it outputs an indication signal of successful power-on detection to the third low-voltage difference linear regulator and the fourth low-voltage difference linear regulator, and the third low-voltage difference linear regulator and the fourth low-voltage difference linear regulator start to power on; when the third low-voltage difference linear regulator completes power-on, it sends an indication signal of successful power-on detection to the second low-voltage difference linear regulator, and the second low-voltage difference linear regulator starts to power on.

[0011] Furthermore, the clock reset subsystem includes a phase-locked loop, a power-on reset unit and a clock and reset signal shaping unit; the phase-locked loop is a universal on-chip phase-locked loop that realizes a 2-time frequency multiplication function; the power-on reset unit is a universal module, and the clock and reset signal shaping unit realizes shaping and filtering processing of the clock and reset signals.

[0012] The subsystem integrated on the chip of the present invention realizes the functions of front-stage signal conditioning and acquisition, post-stage conversion and drive, serial communication, etc. in the fiber optic gyroscope signal processing system, and solves the problems of poor consistency, low debugging efficiency, and high cost of discrete devices commonly used in fiber optic gyroscope signal processing systems. It also facilitates users to carry out secondary integration applications and can also meet similar application needs in the field of fiber optic gyroscope processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is a schematic diagram of the structure of a fiber optic gyroscope signal processing system with 14-bit sampling accuracy according to the present invention;

[0014] Figure 2 This is a schematic diagram of the structure of a power management subsystem in a fiber optic gyroscope signal processing system with 14-bit sampling accuracy according to the present invention;

[0015] Figure 3 The invention is to invent a power-on sequence diagram of each low-dropout linear regulator in the power management subsystem of a fiber optic gyroscope signal processing system with 14-bit sampling accuracy. DETAILED DESCRIPTION

[0016] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0017] The present invention provides a fiber optic gyroscope signal processing system with 14-bit sampling accuracy, comprising a 14-bit ADC (i.e., a 14-bit analog-to-digital converter), a data processing subsystem, a 14-bit DAC (i.e., a 14-bit digital-to-analog converter), a clock reset subsystem, a power management subsystem, and an RS422 interface circuit. The 14-bit ADC is electrically connected to the data processing subsystem via a data bus, the data processing subsystem is electrically connected to the 14-bit DAC via a data bus, the RS422 interface circuit is electrically connected to the data processing subsystem via a serial bus, the clock reset subsystem is electrically connected to the 14-bit ADC, the data processing subsystem, and the 14-bit DAC via a clock signal and a reset signal, respectively, and the power management subsystem supplies power to the 14-bit ADC, the data processing subsystem, the 14-bit DAC, and the RS422 interface circuit, respectively.

[0018] like Figure 1As shown, this embodiment provides a preferred implementation of a fiber optic gyroscope signal processing system with 14-bit sampling accuracy. In this implementation scheme, the system includes a 14-bit ADC, a data processing subsystem, a 14-bit DAC, an RS422 interface circuit, a power management subsystem, and a clock reset subsystem.

[0019] In this embodiment, a 14-bit ADC is used to convert a continuous analog signal into a discrete digital signal. The device is generally composed of a weighted resistor network, an operational amplifier, a reference power supply, and an analog switch. Those skilled in the art divide the various parts of the device into an analog part, a digital part, an analog I / O port part, and a digital I / O port part based on the functions of the various components. The input end of the 14-bit ADC is connected to the universal input port, and the output end is electrically connected to the data processing subsystem via a bus. The ADC is a single-channel ADC with a resolution of 14 bits and an SFDR (spurious-free dynamic range) ≥ 70dBc at a sampling rate of 25Msps.

[0020] In this embodiment, the data processing subsystem includes an angular velocity signal modem, a closed-loop controller, a feedback phase shift generator, a square wave bias generator, a serial port communication, and an EEPROM (Electrically Erasable Programmable Read-Only Memory) read / write circuit. The angular velocity signal modem unit receives the data signal sent by the ADC and transmits it to the closed-loop controller. The first signal generated by the closed-loop controller is connected to the 14-bit DAC via the feedback phase shift generator. The second signal generated by the closed-loop controller is passed through the square wave bias generator to generate a square wave and output it to the outside of the chip. The EEPROM read / write circuit reads the control signals of the above modules after power-on reset is completed. The serial port output data is connected to the RS422 interface circuit.

[0021] In this embodiment, a 14-bit DAC is used to convert discrete digital signals into continuous analog signals. Similar to a 14-bit ADC, the device is generally composed of a weighted resistor network, an operational amplifier, a reference power supply, and an analog switch. Those skilled in the art divide the various parts of the device into an analog part, a digital part, an analog I / O port part, and a digital I / O port part based on the functions of the various components. The input end of the 14-bit DAC is electrically connected to the data processing subsystem, and the output end is electrically connected to the general output port. The DAC is a single-channel DAC with a resolution of 14 bits and an SFDR (spurious-free dynamic range) ≥ 65dBc at a sampling rate of 25Msps.

[0022] In this embodiment, the input end of the RS422 interface circuit is electrically connected to the serial port unit in the data processing subsystem through a serial bus, and the output end of the RS422 interface circuit outputs data to the host computer for debugging. The power supply voltage of the RS422 interface circuit is 5V, and the maximum operating frequency of the RS422 interface circuit is 8Mhz.

[0023] like Figure 2 As shown, in the design of the power management subsystem, the isolation effect between digital / analog signals is considered, and factors such as the power supply voltage at which the ADC and DAC can achieve optimal performance must be taken into account, and power planning is considered in a compromise manner. In this embodiment, the overall power supply solution is to integrate four low-dropout linear regulators (LDOs) on the chip, which are uniformly powered by a 5V power supply. To achieve the best performance indicators, based on the actual test results of each IP, the ADC analog part and analog I / O are powered by a 3V output LDO, the DAC analog part and analog I / O are powered by a 4V output LDO, and the digital circuit part of the ADC and DAC, as well as the data processing subsystem, are all powered by a 3.3V output LDO. The last 3.3V LDO provides power for other modules outside the chip (temperature sensor, EEPROM, etc.), the clock reset subsystem, and the digital I / O ring inside the chip.

[0024] like Figure 3 As shown, in the present fiber optic gyroscope chip, if the power-on timing design is not performed, the power-on sequence should be data processing subsystem → DAC (analog part) → ADC (analog part). In this embodiment, the data processing subsystem is powered on first, followed by the DAC, and the ADC is the slowest. In this case, it is possible that during the power-on process, the digital part has completed the 3.3V power-on work, but the ADC part serving as its input has not completed the power-on. Its digital output level is less than 3.3V, causing the subsequent digital circuit to be in a conjugate conduction state, generating a transient large current, and in extreme cases, even causing the circuit to burn out.

[0025] To avoid this problem, this embodiment designs the power-on sequence of the chip circuit in the power management subsystem and integrates a power-on detection unit inside the LDO. The overall architecture adopts a cascade method. After the front-stage LDO completes power-on, it will output a power-on detection success indication signal (FLAGn). Only then will the next-stage LDO start powering on. After the power-on detection passes, the indication signal is transmitted to the next-stage LDO. The cascade order is arranged according to the digital signal flow, which is ADC (analog part) → data processing subsystem.

[0026] →DAC (analog part).

[0027] Specifically, in this embodiment, the first low-voltage difference linear regulator (i.e., LDO1 in the figure) outputs an indication signal FLAG1 during the power-on process. When the voltage is greater than 2.4V, the value of the indication signal FLAG1 is "1", otherwise the value of the indication signal FLAG1 is "0"; when the third low-voltage difference linear regulator (i.e., LDO3 in the figure) receives the value of the indication signal FLAG1 as "1", it starts to power on. The third low-voltage difference linear regulator outputs an indication signal FLAG2 during the power-on process. When the voltage is greater than 2.7V, the value of the indication signal FLAG1 is "1", otherwise the value of the indication signal FLAG1 is "0"; when the second low-voltage difference linear regulator (LDO2 in the figure) receives the value of the indication signal FLAG2 as "1", it starts to power on. The present invention mainly limits the power-on sequence of the first low-voltage difference linear regulator, the second low-voltage difference linear regulator, and the third low-voltage difference linear regulator. In this embodiment, the third low-voltage difference linear regulator can be powered on at the same time as the fourth low-voltage difference linear regulator.

[0028] In this embodiment, the clock reset subsystem includes a phase-locked loop, a power-on reset unit, and a clock and reset signal shaping unit. The phase-locked loop is a general on-chip phase-locked loop that realizes a 2-time frequency function and a maximum operating frequency of 50Mhz; the power-on reset unit is a general module, and the clock and reset signal shaping unit realizes shaping and filtering processing of the clock and reset signals.

[0029] By adopting the chip structure of the present invention, not only can the integrated fiber optic gyroscope signal acquisition system be controlled, but through different EEPROM configurations, it can also meet the application requirements of fiber optic gyroscope processing systems with different configurations while maintaining the same accuracy. The chip structure of the present invention can be manufactured using a 0.35μm CMOS process, achieving a monolithic integrated fiber optic gyroscope signal acquisition system. This solves the problems of high system development complexity, large size, and high power consumption associated with discrete device integration solutions for integrated fiber optic gyroscope signal acquisition systems, while also facilitating secondary integration applications.

[0030] The above embodiments further illustrate the purpose, technical solutions and advantages of the present invention in detail. It should be understood that the above embodiments are only preferred implementation plans of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made to the present invention within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A fiber optic gyroscope signal processing system with 14-bit sampling accuracy, characterized in that: The system comprises a 14-bit ADC, a data processing subsystem, a 14-bit DAC, a clock reset subsystem, a power management subsystem and an RS422 interface circuit. The 14-bit ADC is electrically connected to the data processing subsystem via a data bus. The data processing subsystem is electrically connected to the 14-bit DAC via a data bus. The RS422 interface circuit is electrically connected to the data processing subsystem via a serial bus. The clock reset subsystem is electrically connected to the 14-bit ADC, the data processing subsystem and the 14-bit DAC via a clock signal and a reset signal respectively. The power management subsystem is electrically connected to the 14-bit ADC, the data processing subsystem and the 14-bit DAC respectively. The data processing subsystem includes an angular velocity signal modem, a closed-loop controller, a feedback phase shift generator, a square wave bias generator, a serial interface, and an EEPROM read-write circuit. The angular velocity signal modem receives the signal sent by the 14-bit ADC and transmits it to the closed-loop controller. The closed-loop controller generates two identical signals, one of which is connected to the 14-bit DAC through the feedback phase shift generator, and the other signal is output as a square wave through the square wave bias generator. The EEPROM read-write circuit reads the angular velocity signal modem, the closed-loop controller, the feedback phase shift generator, the square wave bias generator, the serial interface, and the EEPROM read-write circuit after the power-on reset is completed. The controller, feedback phase shift generator, and square wave bias generator control signal; the serial interface output data is connected to the RS422 interface circuit; the power management subsystem is composed of four low-voltage difference linear regulators, and the four low-voltage difference linear regulators are powered by a 5V power supply. The first low-voltage difference linear regulator provides 3V voltage for the analog part of the 14-bit ADC, and the third low-voltage difference linear regulator provides 3.3V voltage for the data processing subsystem, the 14-bit DAC digital part, and the 14-bit ADC digital part; the second low-voltage difference linear regulator provides 4V voltage for the 14-bit DAC analog part; the fourth low-voltage difference linear regulator is the clock The reset subsystem, the I / O ports of the 14-bit DAC and the 14-bit ADC, and the peripheral circuits of the chip provide a 3.3V voltage; the four low-voltage difference linear regulators in the electronic management subsystem are powered on in a cascade manner. When the first low-voltage difference linear regulator completes power-on, it outputs a power-on detection success indication signal to the third low-voltage difference linear regulator and the fourth low-voltage difference linear regulator, and the third low-voltage difference linear regulator and the fourth low-voltage difference linear regulator start to power on; when the third low-voltage difference linear regulator completes power-on, it sends a power-on detection success indication signal to the second low-voltage difference linear regulator, and the second low-voltage difference linear regulator starts to power on.

2. The fiber optic gyroscope signal processing system with 14-bit sampling accuracy according to claim 1, characterized in that: The input end of the 14-bit ADC is connected to the chip input port signal, and the output end of the 14-bit ADC is electrically connected to the data processing subsystem through the data bus.

3. The fiber optic gyroscope signal processing system with 14-bit sampling accuracy according to claim 1, characterized in that: The input end of the 14-bit DAC is electrically connected to the data processing subsystem through a data bus, and the output end of the 14-bit DAC is output to the chip analog output port.

4. The fiber optic gyroscope signal processing system with 14-bit sampling accuracy according to claim 1, characterized in that: The input end of the RS422 interface circuit is electrically connected to the serial port unit in the data processing subsystem through a serial bus, and the output end of the RS422 interface circuit outputs data to a host computer for debugging.

5. The fiber optic gyroscope signal processing system with 14-bit sampling accuracy according to claim 1, characterized in that: The clock reset subsystem includes a phase-locked loop, a power-on reset unit and a clock and reset signal shaping unit; the phase-locked loop is a universal on-chip phase-locked loop that realizes a 2-time frequency multiplication function; the power-on reset unit is a universal module, and the clock and reset signal shaping unit realizes shaping and filtering processing of the clock and reset signals.

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