Method for controlling memory voltage generation sequence and memory

Abstract

The present application provides a method for controlling the order of memory voltage generation and a memory. The method includes: first, after receiving a power-on signal, issuing a first start-up signal, the first start-up signal is used to generate a substrate voltage of a switching transistor, and controlling the substrate voltage to gradually decrease to a first predetermined value, the first predetermined value being less than the ground potential of the memory; then, after issuing the first start-up signal, issuing a second start-up signal, the second start-up signal is used to generate a plate voltage of a storage capacitor, and controlling the plate voltage to rise to a second predetermined value, the second predetermined value being greater than the ground potential. This method first controls the generation of the substrate voltage to ensure that other circuits can operate stably, and then controls the generation of the plate voltage, thereby reducing the mutual coupling effect between the substrate voltage and the plate voltage, thereby reducing leakage, thereby solving the problem of leakage generated during the power-on startup process of the memory in the prior art.

Description

Technical Field

[0001] The present application relates to the field of semiconductor integrated circuits, and in particular to a method for controlling a memory voltage generation sequence and a memory. Background Art

[0002] To meet DRAM (Dynamic Random Access Memory) specification requirements, improve performance, and reduce power consumption, DRAM chips must internally generate multiple voltages to serve as power supplies or reference voltages for other modules. When the DRAM chip is powered on, the order in which these voltages are generated must be carefully considered to minimize leakage during startup and coupling between voltages of varying magnitudes. Summary of the Invention

[0003] The main purpose of the present application is to provide a method for controlling a memory voltage generation sequence and a memory, so as to at least solve the problem of leakage generated during the power-on startup process of the memory in the prior art.

[0004] In order to achieve the above-mentioned purpose, according to one aspect of the present application, a method for controlling the memory voltage generation sequence is provided, which is applied to the power timing control unit of the memory, wherein the memory includes a memory array, the memory array includes a word line and a plurality of memory cells, the memory cell includes a storage capacitor and a switching transistor, and the method includes: after receiving a power-on signal, issuing a first start signal, the first start signal is used to generate a substrate voltage of the switching transistor, and control the substrate voltage to gradually decrease to a first predetermined value, and the first predetermined value is less than the ground terminal potential of the memory; after issuing the first start signal, issuing a second start signal, the second start signal is used to generate a plate voltage of the storage capacitor, and control the plate voltage to rise to a second predetermined value, and the second predetermined value is greater than the ground terminal potential, one end of the storage capacitor is connected to the switching transistor, and the other end of the storage capacitor receives the plate voltage.

[0005] Optionally, after sending the first start signal, sending the second start signal includes: sending the second start signal within a predetermined time range after sending the first start signal.

[0006] Optionally, after issuing the first start signal, issuing a second start signal includes: detecting the size of the substrate voltage in real time; issuing the second start signal when the substrate voltage is less than or equal to a third predetermined value, and the third predetermined value is less than the ground terminal potential of the memory and greater than the first predetermined value.

[0007] Optionally, after issuing the second start-up signal, the method further includes: issuing a third start-up signal after the substrate voltage drops to the first predetermined value, the third start-up signal being used to generate a reset voltage for the word line in the storage array, and controlling the reset voltage to drop to a fourth predetermined value, the reset voltage being the default voltage after the word line is turned off, and the fourth predetermined value being less than the ground terminal potential of the memory and greater than the first predetermined value.

[0008] Optionally, after receiving the power-on signal and before sending the first start signal, the method further includes: controlling the plate voltage and the reset voltage to be clamped to the ground terminal potential.

[0009] Optionally, before receiving the power-on signal, the method further includes: controlling the substrate voltage to be clamped to the ground terminal potential.

[0010] Optionally, the memory also includes a voltage pump, which is used to generate the substrate voltage based on the oscillation signal output by the oscillator. After issuing a second start signal, the method also includes: controlling to increase the frequency of the oscillation signal output by the oscillator to increase the update frequency of the substrate voltage.

[0011] Optionally, the method further includes: after the substrate voltage reaches the first predetermined value, controlling to reduce the frequency of the oscillation signal output by the oscillator.

[0012] Optionally, after issuing the first start signal and before issuing the second start signal, the method further includes: issuing a fourth start signal, wherein the fourth start signal is used to generate a pre-charge voltage for the bit line and control the pre-charge voltage to rise to a fifth predetermined value, wherein the fifth predetermined value is greater than the ground terminal potential and less than the second predetermined value.

[0013] Optionally, after issuing the fourth start signal, the method further includes: issuing a fifth start signal, wherein the fifth start signal is used to control the pre-charge voltage to rise to a sixth predetermined value, and the sixth predetermined value is greater than the fifth predetermined value.

[0014] According to another aspect of the present application, a memory is provided, comprising a power timing control unit and a memory array, wherein the power timing control unit is used to execute any one of the methods for controlling the memory voltage generation sequence; the memory array is electrically connected to the power timing control unit, the memory array comprises a word line and a plurality of memory cells, the memory cells comprise electrically connected storage capacitors and switching transistors, and the word line is used to control whether the word line is turned on or off.

[0015] Optionally, the memory also includes a voltage generating circuit, which is electrically connected to the power timing control unit. The voltage generating circuit is used to control the timing of generating the substrate voltage of the switching transistor, the plate voltage of the storage capacitor and the reset voltage of the word line according to the signal sent by the power timing control unit. The reset voltage is the default voltage after the word line is turned off.

[0016] Applying the technical solution of the present application, in the control method of the memory voltage generation sequence, first, after receiving the power-on signal, a first start-up signal is issued, the first start-up signal is used to generate the substrate voltage of the switching transistor, and control the substrate voltage to gradually decrease to a first predetermined value, the first predetermined value is less than the ground terminal potential of the memory; then, a second start-up signal is issued, the second start-up signal is used to generate the plate voltage of the storage capacitor, and control the plate voltage to rise to a second predetermined value, the second predetermined value is greater than the ground terminal potential, one end of the storage capacitor is connected to the switching transistor, and the other end of the storage capacitor receives the plate voltage. This method first controls the generation of the substrate voltage to ensure that other circuits can work stably, and then controls the generation of the plate voltage, thereby reducing the mutual coupling effect between the substrate voltage and the plate voltage, thereby reducing leakage, and thus solving the problem of leakage generated during the power-on startup process of the memory in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings that constitute part of this application are used to provide a further understanding of this application. The illustrative embodiments of this application and their descriptions are used to explain this application and do not constitute an improper limitation on this application. In the drawings:

[0018] Figure 1 A hardware structure block diagram of a mobile terminal for executing a method for controlling a memory voltage generation sequence provided in an embodiment of the present application is shown;

[0019] Figure 2 A schematic flow chart of a method for controlling a memory voltage generation sequence according to an embodiment of the present application is shown;

[0020] Figure 3 A diagram showing a relationship between a memory voltage and time provided in accordance with an embodiment of the present application is shown;

[0021] Figure 4 A circuit diagram for generating a memory voltage according to an embodiment of the present application is shown;

[0022] Figure 5 A structural block diagram of a device for controlling a memory voltage generation sequence provided according to an embodiment of the present application is shown.

[0023] The above drawings include the following reference numerals:

[0024] 102. Processor; 104. Memory; 106. Transmission device; 108. Input / output device. DETAILED DESCRIPTION

[0025] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in this application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0026] In order to enable those skilled in the art to better understand the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of this application.

[0027] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0028] As introduced in the background technology, the prior art has the problem of leakage during the power-on startup of the memory. To solve the above problem, the embodiments of the present application provide a method for controlling the voltage generation sequence of the memory and a memory.

[0029] The technical solutions in the embodiments of the present invention will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present invention.

[0030] The method embodiments provided in the embodiments of the present application can be executed in a mobile terminal, a computer terminal or a similar computing device. Taking running on a mobile terminal as an example, Figure 1 FIG. 1 is a hardware structure block diagram of a mobile terminal according to an embodiment of the present invention, which includes a method for controlling the memory voltage generation sequence. Figure 1 As shown, the mobile terminal may include one or more ( Figure 1Only one is shown) a processor 102 (the processor 102 may include but is not limited to a microprocessor MCU or a programmable logic device FPGA and other processing devices) and a memory 104 for storing data, wherein the mobile terminal may also include a transmission device 106 and an input and output device 108 for communication functions. It will be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the mobile terminal. Figure 1 More or fewer components than shown, or with Figure 1 Different configurations shown.

[0031] The memory 104 can be used to store computer programs, such as software programs and modules of application software, such as the computer program corresponding to the device information display method in the embodiment of the present invention. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, implementing the above-mentioned method. The memory 104 may include a high-speed random access memory and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include a memory remotely located relative to the processor 102, and these remote memories can be connected to the mobile terminal via a network. Examples of the above-mentioned networks include but are not limited to the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof. The transmission device 106 is used to receive or send data via a network. Specific examples of the above-mentioned network may include a wireless network provided by the mobile terminal's communication provider. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, abbreviated as NIC), which can be connected to other network devices via a base station to communicate with the Internet. In one example, the transmission device 106 may be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0032] In this embodiment, a method for controlling the voltage generation sequence of a memory running on a mobile terminal, a computer terminal or a similar computing device is provided, which is applied to a power timing control unit of the above-mentioned memory. The above-mentioned memory includes a memory array, and the above-mentioned memory array includes a word line and a plurality of memory cells. The above-mentioned memory cell includes a storage capacitor and a switching transistor. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that here.

[0033] In actual applications, the memory's plate voltage Vap2 and substrate voltage Vkb are both generated when the power is turned on. Coupling occurs between the two voltages, causing Vap2 to be lower than the ideal value and Vkb to be pulled higher. In this case, if Vap2 is lower than the ground potential Vss, leakage may occur.

[0034] Figure 2 FIG. 1 is a flow chart of a method for controlling the memory voltage generation sequence according to an embodiment of the present application. Figure 2 As shown, the method includes the following steps:

[0035] Step S201, after receiving the power-on signal, issuing a first start signal, the first start signal being used to generate a substrate voltage of the switching transistor and controlling the substrate voltage to gradually decrease to a first predetermined value, the first predetermined value being less than a ground potential of the memory;

[0036] Specifically, after receiving the power-on signal, the substrate voltage of the switching transistor is first generated to ensure stable operation of other circuits. The first predetermined value may be -0.7 V. In the present disclosure, "controlling" the corresponding voltage rise / fall may refer to the corresponding start signal not only directly generating the corresponding voltage but also directly controlling the change trend and amplitude of the corresponding voltage through its own potential and timing changes. It may also refer to merely participating in the generation of the corresponding voltage without participating in controlling the change trend and amplitude of the corresponding voltage.

[0037] In step S202, after the first start signal is issued, a second start signal is issued. The second start signal is used to generate a plate voltage of the storage capacitor and control the plate voltage to rise to a second predetermined value. The second predetermined value is greater than the ground potential. One end of the storage capacitor is connected to the switching transistor, and the other end of the storage capacitor receives the plate voltage.

[0038] Specifically, after the first start signal is sent, the second start signal is sent, that is, Figure 3 As shown, after the substrate voltage Vkb of the switching transistor is generated, the plate voltage Vap2 of the storage capacitor is generated. Following this power-on sequence can reduce the influence of the plate voltage Vap2 of the storage capacitor on the substrate voltage Vkb of the switching transistor, reduce the coupling between the two, prevent the plate voltage from being lower than the ideal voltage, and prevent the substrate voltage from being pulled up. The above-mentioned second predetermined value can be 0.5V.

[0039] Through this embodiment, the substrate voltage is first controlled to ensure that other circuits can operate stably, and then the plate voltage is controlled to reduce the mutual coupling effect between the substrate voltage and the plate voltage, thereby reducing leakage, thereby solving the problem of leakage generated during the power-on startup process of the memory in the prior art.

[0040] In practical applications, semiconductor integrated circuit devices, more specifically semiconductor memories, must drive all internal power supplies to a predetermined voltage within the startup time defined by the specification during power-up. This voltage is achieved by charging parasitic capacitance or stabilization capacitance formed in the semiconductor substrate using an external power supply. The internal power supply can include multiple power supplies, such as an intermediate power supply with a potential intermediate between the external power supply and ground, a boost power supply higher than the external power supply, and a negative power supply lower than ground. In the above-described embodiment, the memory includes a memory array, which includes word lines and a plurality of memory cells. The memory cells include storage capacitors and switching transistors. The substrate voltage of the switching transistor corresponds to the negative power supply within the memory cell, and the plate voltage of the storage capacitor corresponds to the intermediate power supply within the memory cell.

[0041] To generate the plate voltage after the substrate voltage is generated, an optional solution includes issuing a second start signal after issuing the first start signal, which includes issuing the second start signal within a predetermined time range after issuing the first start signal. After the first start signal is issued, the substrate voltage begins to decrease, and after a predetermined time, the second start signal is issued, at which point the plate voltage is generated.

[0042] Specifically, the minimum value of the predetermined time range is smaller than the maximum value of the time range required for the substrate voltage to drop from the initial value to the first predetermined value. The time range required for the substrate voltage to drop to the first predetermined value can be obtained through testing.

[0043] In another optional embodiment, after issuing the first start signal, issuing a second start signal includes: detecting the substrate voltage in real time; and issuing the second start signal when the substrate voltage is less than or equal to a third predetermined value, wherein the third predetermined value is less than the ground potential of the memory and greater than the first predetermined value. After issuing the first start signal, determining that the substrate voltage has dropped to or less than the third predetermined value further confirms that the plate voltage is generated at this time and prevents coupling with the substrate voltage, thereby reducing leakage.

[0044] To further prevent coupling between different voltages generated within the memory cells during power-up, after issuing the second startup signal in step S202, the method further includes issuing a third startup signal after the substrate voltage drops to the first predetermined value. The third startup signal is used to generate a reset voltage for the word lines in the memory array and control the reset voltage to drop to a fourth predetermined value. The reset voltage is a default voltage after the word lines are turned off. The fourth predetermined value is less than the ground potential of the memory and greater than the first predetermined value. The reset voltage is also referred to as the voltage that turns off the word lines.

[0045] Specifically, the reset voltage used to indicate that the word line is not selected is the same as the substrate voltage mentioned above, and also corresponds to the negative power supply inside the memory cell. In order to reduce the mutual influence between the two negative power supplies, as shown in FIG. Figure 3 As shown, after the substrate voltage Vkb drops to the first predetermined value, the reset voltage Vwln is generated again, and the reset voltage Vwln is controlled to drop to a fourth predetermined value, which may be -0.2V.

[0046] In one optional embodiment, after receiving the power-on signal and before issuing the first start-up signal, the method further includes: controlling the plate voltage and the reset voltage to be clamped to the ground potential. This method clamps the plate voltage and the reset voltage to the ground potential before issuing the first start-up signal to ensure that the substrate voltage is not affected by the plate voltage and the reset voltage when it is generated.

[0047] In order to further ensure that the voltage generation sequence within the memory cell is not affected and to avoid coupling between internal voltages, in another optional solution, before receiving the power-on signal, the method further includes: controlling the substrate voltage to be clamped to the ground potential.

[0048] In another alternative embodiment, the memory further includes a voltage pump configured to generate the substrate voltage based on an oscillation signal output by an oscillator. After issuing the second start signal, the method further includes controlling to increase the frequency of the oscillation signal output by the oscillator to increase the update frequency of the substrate voltage. Increasing the frequency of the oscillation signal output by the oscillator increases the update frequency of the substrate voltage, that is, speeds up the build-up time (discharge rate) of the substrate voltage, thereby offsetting the coupling effect of plate voltage changes on the substrate voltage, thereby allowing the substrate voltage to reach the first predetermined value normally or more quickly.

[0049] In practical applications, the frequency of the oscillation signal before the second start signal is issued is referred to as the first frequency, and the frequency after the second start signal is issued is referred to as the second frequency. The second frequency may be 8 times the first frequency.

[0050] After the substrate voltage reaches the first predetermined value, the substrate voltage stabilizes at the first predetermined value and will not affect the generation of the plate voltage. Therefore, further, the above method also includes: after the above substrate voltage reaches the above first predetermined value, controlling to reduce the frequency of the above oscillation signal output by the above oscillator.

[0051] In practical applications, the frequency of the oscillation signal can be restored from the second frequency to the first frequency.

[0052] The internal power supply of the memory cell also includes a precharge power supply for the bit line. In order to solve the leakage problem inside the memory during power-on, in another optional solution, after sending the above-mentioned first start signal and before sending the second start signal, the above-mentioned method also includes: sending a fourth start signal, the above-mentioned fourth start signal is used to generate a precharge voltage for the bit line, and control the above-mentioned precharge voltage to rise to a fifth predetermined value, the above-mentioned fifth predetermined value is greater than the above-mentioned ground terminal potential and less than the above-mentioned second predetermined value. The precharge power supply also belongs to the intermediate power supply inside the memory cell. The fourth start signal is sent after the first start signal and before the second start signal. Figure 3 As shown, the pre-charge voltage vad2 is controlled to rise to a fifth predetermined value, so that the generation order of the pre-charge voltage vad2, the substrate voltage Vkb and the plate voltage Vwln are staggered to avoid coupling between the three voltages.

[0053] In practical applications, such as Figure 4 As shown, when vad2e (i.e., Vad2 mentioned above) is clamped to Vss and the gate voltage of Q1 is lower than the low-voltage threshold, a complete current path is formed between Vcc, Q1, Q2, Q4, Q7, and Vss. Q4 is a low-threshold voltage NMOS transistor. This type of MOS transistor itself has a large leakage current, resulting in a large leakage current in the memory array at this time. Raising the precharge voltage to the fifth predetermined value is beneficial to reducing the source-drain voltage difference of Q4, thereby weakening or even blocking the leakage current of Q4, thereby avoiding the formation of a leakage path and reducing the overall leakage current.

[0054] In order to further reduce leakage, in an optional solution, after issuing the fourth start signal, the above method also includes: issuing a fifth start signal, and the above fifth start signal is used to control the above pre-charge voltage to rise to a sixth predetermined value, the above sixth predetermined value is greater than the above fifth predetermined value, and the above sixth predetermined value is greater than or equal to the above second predetermined value.

[0055] The embodiment of the present application also provides a control device for the memory voltage generation sequence. It should be noted that the control device for the memory voltage generation sequence of the embodiment of the present application can be used to execute the control method for the memory voltage generation sequence provided by the embodiment of the present application. The device is used to implement the above-mentioned embodiments and preferred embodiments, and the details that have been described will not be repeated. As used below, the term "module" can implement a combination of software and / or hardware for a predetermined function. Although the device described in the following embodiments is preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceived.

[0056] The following introduces a control device for a memory voltage generation sequence provided by an embodiment of the present application.

[0057] Figure 5 Schematic diagram of a control device for a memory voltage generation sequence according to an embodiment of the present application. Figure 5 As shown, the device includes a first sending unit 10 and a second sending unit 20, wherein:

[0058] The first sending unit 10 is configured to send a first start signal after receiving a power-on signal, wherein the first start signal is configured to generate a substrate voltage of the switching transistor and control the substrate voltage to gradually decrease to a first predetermined value, wherein the first predetermined value is less than a ground potential of the memory;

[0059] Specifically, after receiving the power-on signal, the substrate voltage of the switching transistor is generated first to ensure that other circuits can operate stably. The first predetermined value may be -0.7V.

[0060] The above-mentioned second sending unit 20 is used to send a second start signal after sending the above-mentioned first start signal. The above-mentioned second start signal is used to generate the plate voltage of the above-mentioned storage capacitor and control the above-mentioned plate voltage to rise to a second predetermined value. The above-mentioned second predetermined value is greater than the above-mentioned ground terminal potential. One end of the above-mentioned storage capacitor is connected to the above-mentioned switching transistor, and the other end of the above-mentioned storage capacitor receives the above-mentioned plate voltage.

[0061] Specifically, after the first start signal is sent, the second start signal is sent, that is, Figure 3 As shown, after the substrate voltage Vkb of the switching transistor is generated, the plate voltage Vap2 of the storage capacitor is generated. Following this power-on sequence can reduce the influence of the plate voltage Vap2 of the storage capacitor on the substrate voltage Vkb of the switching transistor, reduce the coupling between the two, prevent the plate voltage from being lower than the ideal voltage, and prevent the substrate voltage from being pulled up. The above-mentioned second predetermined value can be 0.5V.

[0062] Through this embodiment, the substrate voltage is first controlled to ensure that other circuits can operate stably, and then the plate voltage is controlled to reduce the mutual coupling effect between the substrate voltage and the plate voltage, thereby reducing leakage, thereby solving the problem of leakage generated during the power-on startup process of the memory in the prior art.

[0063] In practical applications, semiconductor integrated circuit devices, more specifically semiconductor memories, must drive all internal power supplies to a predetermined voltage within the startup time defined by the specification during power-up. This voltage is achieved by charging parasitic capacitance or stabilization capacitance formed in the semiconductor substrate using an external power supply. The internal power supply can include multiple power supplies, such as an intermediate power supply with a potential intermediate between the external power supply and ground, a boost power supply higher than the external power supply, and a negative power supply lower than ground. In the above-described embodiment, the memory includes a memory array, which includes word lines and a plurality of memory cells. The memory cells include storage capacitors and switching transistors. The substrate voltage of the switching transistor corresponds to the negative power supply within the memory cell, and the plate voltage of the storage capacitor corresponds to the intermediate power supply within the memory cell.

[0064] To ensure that the plate voltage is generated after the substrate voltage is generated, in one optional solution, the second transmitting unit includes a first transmitting module configured to transmit the second start signal within a predetermined time range after the first start signal is transmitted. After the first start signal is transmitted, the substrate voltage begins to decrease, and after a predetermined time, the second start signal is transmitted, at which point the plate voltage is generated.

[0065] Specifically, the minimum value of the predetermined time range is smaller than the maximum value of the time range required for the substrate voltage to drop from the initial value to the first predetermined value.

[0066] In another optional embodiment, the second transmitting unit includes a detection module and a second transmitting module. The detection module is configured to detect the substrate voltage in real time. The second transmitting module is configured to issue the second start signal when the substrate voltage is less than or equal to a third predetermined value, wherein the third predetermined value is less than the ground potential of the memory and greater than the first predetermined value. After the first start signal is issued, determining that the substrate voltage has dropped to or less than the third predetermined value further confirms that the plate voltage is generated at this time and prevents coupling with the substrate voltage, thereby reducing leakage.

[0067] To further prevent coupling between different voltages generated within the memory cells during power-up, the apparatus further includes a third sending unit configured to, after issuing the second start-up signal and after the substrate voltage drops to the first predetermined value, issue a third start-up signal. The third start-up signal is used to generate a reset voltage for the word lines in the memory array and control the reset voltage to drop to a fourth predetermined value. The reset voltage is a default voltage after the word lines are turned off. The fourth predetermined value is less than the ground potential of the memory and greater than the first predetermined value. The reset voltage is also referred to as the voltage that turns off the word lines.

[0068] Specifically, the reset voltage for the word line as the unselected power supply of the word line is the same as the substrate voltage, and also corresponds to the negative power supply inside the memory cell. In order to reduce the mutual influence between the two negative power supplies, as shown in FIG. Figure 3 As shown, after the substrate voltage Vkb drops to the first predetermined value, the reset voltage Vwln is generated again, and the reset voltage Vwln is controlled to drop to a fourth predetermined value, which may be -0.2V.

[0069] In one optional solution, after receiving the power-on signal, the apparatus further includes a first control unit configured to control the plate voltage and the reset voltage to be clamped to the ground potential before issuing the first start signal. This method clamps the plate voltage and the reset voltage to the ground potential before issuing the first start signal to ensure that the substrate voltage is not affected by the plate voltage and the reset voltage when it is generated.

[0070] In order to further ensure that the voltage generation order inside the memory cell is not affected and to avoid coupling between internal voltages, in another optional solution, the above-mentioned device also includes a second control unit, which is used to control the above-mentioned substrate voltage to be clamped to the above-mentioned ground terminal potential before receiving the above-mentioned power-on signal.

[0071] In another alternative embodiment, the memory further includes a voltage pump configured to generate the substrate voltage based on an oscillation signal output by the oscillator. The apparatus further includes a third control unit configured to, after issuing a second start signal, control an increase in the frequency of the oscillation signal output by the oscillator to increase the update frequency of the substrate voltage. Increasing the frequency of the oscillation signal output by the oscillator increases the update frequency of the substrate voltage, that is, speeds up the build-up time (discharge rate) of the substrate voltage, thereby offsetting the coupling effect of plate voltage changes on the substrate voltage, and allowing the substrate voltage to reach the first predetermined value normally or more quickly.

[0072] In practical applications, the frequency of the oscillation signal before the second start signal is issued is referred to as the first frequency, and the frequency after the second start signal is issued is referred to as the second frequency. The second frequency may be 8 times the first frequency.

[0073] After the substrate voltage reaches the first predetermined value, the substrate voltage stabilizes at the first predetermined value and will not affect the generation of the plate voltage. Therefore, the above-mentioned device further includes a fourth control unit, which is used to control the reduction of the frequency of the above-mentioned oscillation signal output by the above-mentioned oscillator after the above-mentioned substrate voltage reaches the above-mentioned first predetermined value.

[0074] In practical applications, the frequency of the oscillation signal can be restored from the second frequency to the first frequency.

[0075] The internal power supply of the memory cell also includes a precharge power supply for the bit line. In order to solve the leakage problem inside the memory when powered on, in another optional solution, the above-mentioned device also includes a fourth sending unit. The above-mentioned fourth sending unit is used to send a fourth start signal after sending the above-mentioned first start signal and before sending the second start signal. The above-mentioned fourth start signal is used to generate a precharge voltage for the bit line and control the above-mentioned precharge voltage to rise to a fifth predetermined value. The above-mentioned fifth predetermined value is greater than the above-mentioned ground terminal potential and less than the above-mentioned second predetermined value. The precharge power supply also belongs to the intermediate power supply inside the memory cell. The fourth start signal is sent after the first start signal and before the second start signal. Figure 3 As shown, the pre-charge voltage vad2 is controlled to rise to a fifth predetermined value, so that the generation order of the pre-charge voltage vad2, the substrate voltage Vkb and the plate voltage Vwln are staggered to avoid coupling between the three voltages.

[0076] In practical applications, such as Figure 4 As shown, when vad2e (i.e., Vad2 mentioned above) is clamped to Vss and the gate voltage of Q1 is lower than the low-voltage threshold, a complete current path is formed between Vcc, Q1, Q2, Q4, Q7, and Vss. Q4 is a low-threshold voltage NMOS transistor. This type of MOS transistor itself has a large leakage current, resulting in a large leakage current in the memory array at this time. Raising the precharge voltage to the fifth predetermined value is beneficial to reducing the source-drain voltage difference of Q4, thereby weakening or even blocking the leakage current of Q4, thereby avoiding the formation of a leakage path and reducing the overall leakage current.

[0077] In order to further reduce leakage, in an optional solution, the above-mentioned device also includes a fifth sending unit, which is used to send a fifth start signal after sending the fourth start signal. The above-mentioned fifth start signal is used to control the above-mentioned pre-charge voltage to rise to a sixth predetermined value, the above-mentioned sixth predetermined value is greater than the above-mentioned fifth predetermined value, and the above-mentioned sixth predetermined value is greater than or equal to the above-mentioned second predetermined value.

[0078] The aforementioned control device for the memory voltage generation sequence includes a processor and a memory. The aforementioned first sending unit and the aforementioned second sending unit are stored as program units in the memory, and the processor executes the program units stored in the memory to implement the corresponding functions. The aforementioned modules are all located in the same processor; alternatively, the aforementioned modules may be located in different processors in any combination.

[0079] The processor includes a core, which calls the corresponding program unit from the memory. The core can be set to one or more, and the leakage problem caused by the power-on startup process of the memory in the prior art can be solved by adjusting the core parameters.

[0080] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM, and the memory includes at least one memory chip.

[0081] An embodiment of the present invention provides a computer-readable storage medium, which includes a stored program. When the program is executed, the device where the computer-readable storage medium is located is controlled to execute the method for controlling the memory voltage generation sequence.

[0082] Specifically, the method for controlling the memory voltage generation sequence includes:

[0083] Step S201, after receiving the power-on signal, issuing a first start signal, the first start signal being used to generate a substrate voltage of the switching transistor and controlling the substrate voltage to gradually decrease to a first predetermined value, the first predetermined value being less than a ground potential of the memory;

[0084] Specifically, after receiving the power-on signal, the substrate voltage of the switching transistor is generated first to ensure that other circuits can operate stably. The first predetermined value may be -0.7V.

[0085] In step S202, after the first start signal is issued, a second start signal is issued. The second start signal is used to generate a plate voltage of the storage capacitor and control the plate voltage to rise to a second predetermined value. The second predetermined value is greater than the ground potential. One end of the storage capacitor is connected to the switching transistor, and the other end of the storage capacitor receives the plate voltage.

[0086] Specifically, after the first start signal is sent, the second start signal is sent, that is, Figure 3As shown, after the substrate voltage Vkb of the switching transistor is generated, the plate voltage Vap2 of the storage capacitor is generated. Following this power-on sequence can reduce the influence of the plate voltage Vap2 of the storage capacitor on the substrate voltage Vkb of the switching transistor, reduce the coupling between the two, prevent the plate voltage from being lower than the ideal voltage, and prevent the substrate voltage from being pulled up. The above-mentioned second predetermined value can be 0.5V.

[0087] Optionally, after sending the first start signal, sending the second start signal includes: sending the second start signal within a predetermined time range after sending the first start signal.

[0088] Optionally, after issuing the above-mentioned first start signal, issuing a second start signal includes: detecting the size of the above-mentioned substrate voltage in real time; issuing the above-mentioned second start signal when the above-mentioned substrate voltage is less than or equal to a third predetermined value, and the above-mentioned third predetermined value is less than the ground terminal potential of the above-mentioned memory and greater than the above-mentioned first predetermined value.

[0089] Optionally, after issuing the second start signal, the method further includes: issuing a third start signal after the substrate voltage drops to the first predetermined value, the third start signal being used to generate a reset voltage for the word line in the memory array, and controlling the reset voltage to drop to a fourth predetermined value, the reset voltage being the default voltage after the word line is turned off, and the fourth predetermined value being less than the ground terminal potential of the memory and greater than the first predetermined value.

[0090] Optionally, after receiving the power-on signal and before sending the first start signal, the method further includes: controlling the plate voltage and the reset voltage to be clamped to the ground potential.

[0091] Optionally, before receiving the power-on signal, the method further includes: controlling the substrate voltage to be clamped to the ground potential.

[0092] Optionally, the above-mentioned memory also includes a voltage pump, which is used to generate the above-mentioned substrate voltage based on the oscillation signal output by the oscillator. After issuing the second start signal, the above-mentioned method also includes: controlling to increase the frequency of the above-mentioned oscillation signal output by the above-mentioned oscillator to increase the update frequency of the above-mentioned substrate voltage.

[0093] Optionally, the method further includes: after the substrate voltage reaches the first predetermined value, controlling to reduce the frequency of the oscillation signal output by the oscillator.

[0094] Optionally, after issuing the above-mentioned first start signal and before issuing the second start signal, the above-mentioned method also includes: issuing a fourth start signal, the above-mentioned fourth start signal is used to generate a pre-charge voltage of the bit line, and control the above-mentioned pre-charge voltage to rise to a fifth predetermined value, the above-mentioned fifth predetermined value is greater than the above-mentioned ground terminal potential and less than the above-mentioned second predetermined value.

[0095] Optionally, after issuing the fourth start signal, the method further includes: issuing a fifth start signal, wherein the fifth start signal is used to control the pre-charge voltage to rise to a sixth predetermined value, and the sixth predetermined value is greater than the fifth predetermined value.

[0096] An embodiment of the present invention provides a processor, which is used to run a program, wherein the method for controlling the memory voltage generation sequence is executed when the program is run.

[0097] Specifically, the method for controlling the memory voltage generation sequence includes:

[0098] Step S201, after receiving the power-on signal, issuing a first start signal, the first start signal being used to generate a substrate voltage of the switching transistor and controlling the substrate voltage to gradually decrease to a first predetermined value, the first predetermined value being less than a ground potential of the memory;

[0099] Specifically, after receiving the power-on signal, the substrate voltage of the switching transistor is generated first to ensure that other circuits can operate stably. The first predetermined value may be -0.7V.

[0100] In step S202, after the first start signal is issued, a second start signal is issued. The second start signal is used to generate a plate voltage of the storage capacitor and control the plate voltage to rise to a second predetermined value. The second predetermined value is greater than the ground potential. One end of the storage capacitor is connected to the switching transistor, and the other end of the storage capacitor receives the plate voltage.

[0101] Specifically, after the first start signal is sent, the second start signal is sent, that is, Figure 3 As shown, after the substrate voltage Vkb of the switching transistor is generated, the plate voltage Vap2 of the storage capacitor is generated. Following this power-on sequence can reduce the influence of the plate voltage Vap2 of the storage capacitor on the substrate voltage Vkb of the switching transistor, reduce the coupling between the two, prevent the plate voltage from being lower than the ideal voltage, and prevent the substrate voltage from being pulled up. The above-mentioned second predetermined value can be 0.5V.

[0102] Optionally, after sending the first start signal, sending the second start signal includes: sending the second start signal within a predetermined time range after sending the first start signal.

[0103] Optionally, after issuing the above-mentioned first start signal, issuing a second start signal includes: detecting the size of the above-mentioned substrate voltage in real time; issuing the above-mentioned second start signal when the above-mentioned substrate voltage is less than or equal to a third predetermined value, and the above-mentioned third predetermined value is less than the ground terminal potential of the above-mentioned memory and greater than the above-mentioned first predetermined value.

[0104] Optionally, after issuing the second start signal, the method further includes: issuing a third start signal after the substrate voltage drops to the first predetermined value, the third start signal being used to generate a reset voltage for the word line in the memory array, and controlling the reset voltage to drop to a fourth predetermined value, the reset voltage being the default voltage after the word line is turned off, and the fourth predetermined value being less than the ground terminal potential of the memory and greater than the first predetermined value.

[0105] Optionally, after receiving the power-on signal and before sending the first start signal, the method further includes: controlling the plate voltage and the reset voltage to be clamped to the ground potential.

[0106] Optionally, before receiving the power-on signal, the method further includes: controlling the substrate voltage to be clamped to the ground potential.

[0107] Optionally, the above-mentioned memory also includes a voltage pump, which is used to generate the above-mentioned substrate voltage based on the oscillation signal output by the oscillator. After issuing the second start signal, the above-mentioned method also includes: controlling to increase the frequency of the above-mentioned oscillation signal output by the above-mentioned oscillator to increase the update frequency of the above-mentioned substrate voltage.

[0108] Optionally, the method further includes: after the substrate voltage reaches the first predetermined value, controlling to reduce the frequency of the oscillation signal output by the oscillator.

[0109] Optionally, after issuing the above-mentioned first start signal and before issuing the second start signal, the above-mentioned method also includes: issuing a fourth start signal, the above-mentioned fourth start signal is used to generate a pre-charge voltage of the bit line, and control the above-mentioned pre-charge voltage to rise to a fifth predetermined value, the above-mentioned fifth predetermined value is greater than the above-mentioned ground terminal potential and less than the above-mentioned second predetermined value.

[0110] Optionally, after issuing the fourth start signal, the method further includes: issuing a fifth start signal, wherein the fifth start signal is used to control the pre-charge voltage to rise to a sixth predetermined value, and the sixth predetermined value is greater than the fifth predetermined value.

[0111] An embodiment of the present invention provides a device, comprising a processor, a memory, and a program stored in the memory and executable on the processor. When the processor executes the program, at least the following steps are performed:

[0112] Step S201, after receiving the power-on signal, issuing a first start signal, the first start signal being used to generate a substrate voltage of the switching transistor and controlling the substrate voltage to gradually decrease to a first predetermined value, the first predetermined value being less than a ground potential of the memory;

[0113] In step S202, after the first start signal is issued, a second start signal is issued. The second start signal is used to generate a plate voltage of the storage capacitor and control the plate voltage to rise to a second predetermined value. The second predetermined value is greater than the ground potential. One end of the storage capacitor is connected to the switching transistor, and the other end of the storage capacitor receives the plate voltage.

[0114] Optionally, after sending the first start signal, sending the second start signal includes: sending the second start signal within a predetermined time range after sending the first start signal.

[0115] Optionally, after issuing the above-mentioned first start signal, issuing a second start signal includes: detecting the size of the above-mentioned substrate voltage in real time; issuing the above-mentioned second start signal when the above-mentioned substrate voltage is less than or equal to a third predetermined value, and the above-mentioned third predetermined value is less than the ground terminal potential of the above-mentioned memory and greater than the above-mentioned first predetermined value.

[0116] Optionally, after issuing the second start signal, the method further includes: issuing a third start signal after the substrate voltage drops to the first predetermined value, the third start signal being used to generate a reset voltage for the word line in the memory array, and controlling the reset voltage to drop to a fourth predetermined value, the reset voltage being the default voltage after the word line is turned off, and the fourth predetermined value being less than the ground terminal potential of the memory and greater than the first predetermined value.

[0117] Optionally, after receiving the power-on signal and before sending the first start signal, the method further includes: controlling the plate voltage and the reset voltage to be clamped to the ground potential.

[0118] Optionally, before receiving the power-on signal, the method further includes: controlling the substrate voltage to be clamped to the ground potential.

[0119] Optionally, the above-mentioned memory also includes a voltage pump, which is used to generate the above-mentioned substrate voltage based on the oscillation signal output by the oscillator. After issuing the second start signal, the above-mentioned method also includes: controlling to increase the frequency of the above-mentioned oscillation signal output by the above-mentioned oscillator to increase the update frequency of the above-mentioned substrate voltage.

[0120] Optionally, the method further includes: after the substrate voltage reaches the first predetermined value, controlling to reduce the frequency of the oscillation signal output by the oscillator.

[0121] Optionally, after issuing the above-mentioned first start signal and before issuing the second start signal, the above-mentioned method also includes: issuing a fourth start signal, the above-mentioned fourth start signal is used to generate a pre-charge voltage of the bit line, and control the above-mentioned pre-charge voltage to rise to a fifth predetermined value, the above-mentioned fifth predetermined value is greater than the above-mentioned ground terminal potential and less than the above-mentioned second predetermined value.

[0122] Optionally, after issuing the fourth start signal, the method further includes: issuing a fifth start signal, wherein the fifth start signal is used to control the pre-charge voltage to rise to a sixth predetermined value, and the sixth predetermined value is greater than the fifth predetermined value.

[0123] The devices in this article can be servers, PCs, PADs, mobile phones, etc.

[0124] The present application also provides a computer program product, which, when executed on a data processing device, is adapted to execute a program for initializing at least the following method steps:

[0125] Step S201, after receiving the power-on signal, issuing a first start signal, the first start signal being used to generate a substrate voltage of the switching transistor and controlling the substrate voltage to gradually decrease to a first predetermined value, the first predetermined value being less than a ground potential of the memory;

[0126] In step S202, after the first start signal is issued, a second start signal is issued. The second start signal is used to generate a plate voltage of the storage capacitor and control the plate voltage to rise to a second predetermined value. The second predetermined value is greater than the ground potential. One end of the storage capacitor is connected to the switching transistor, and the other end of the storage capacitor receives the plate voltage.

[0127] Optionally, after sending the first start signal, sending the second start signal includes: sending the second start signal within a predetermined time range after sending the first start signal.

[0128] Optionally, after issuing the above-mentioned first start signal, issuing a second start signal includes: detecting the size of the above-mentioned substrate voltage in real time; issuing the above-mentioned second start signal when the above-mentioned substrate voltage is less than or equal to a third predetermined value, and the above-mentioned third predetermined value is less than the ground terminal potential of the above-mentioned memory and greater than the above-mentioned first predetermined value.

[0129] Optionally, after issuing the second start signal, the method further includes: issuing a third start signal after the substrate voltage drops to the first predetermined value, the third start signal being used to generate a reset voltage for the word line in the memory array, and controlling the reset voltage to drop to a fourth predetermined value, the reset voltage being the default voltage after the word line is turned off, and the fourth predetermined value being less than the ground terminal potential of the memory and greater than the first predetermined value.

[0130] Optionally, after receiving the power-on signal and before sending the first start signal, the method further includes: controlling the plate voltage and the reset voltage to be clamped to the ground potential.

[0131] Optionally, before receiving the power-on signal, the method further includes: controlling the substrate voltage to be clamped to the ground potential.

[0132] Optionally, the above-mentioned memory also includes a voltage pump, which is used to generate the above-mentioned substrate voltage based on the oscillation signal output by the oscillator. After issuing the second start signal, the above-mentioned method also includes: controlling to increase the frequency of the above-mentioned oscillation signal output by the above-mentioned oscillator to increase the update frequency of the above-mentioned substrate voltage.

[0133] Optionally, the method further includes: after the substrate voltage reaches the first predetermined value, controlling to reduce the frequency of the oscillation signal output by the oscillator.

[0134] Optionally, after issuing the above-mentioned first start signal and before issuing the second start signal, the above-mentioned method also includes: issuing a fourth start signal, the above-mentioned fourth start signal is used to generate a pre-charge voltage of the bit line, and control the above-mentioned pre-charge voltage to rise to a fifth predetermined value, the above-mentioned fifth predetermined value is greater than the above-mentioned ground terminal potential and less than the above-mentioned second predetermined value.

[0135] Optionally, after issuing the fourth start signal, the method further includes: issuing a fifth start signal, wherein the fifth start signal is used to control the pre-charge voltage to rise to a sixth predetermined value, and the sixth predetermined value is greater than the fifth predetermined value.

[0136] Obviously, those skilled in the art will appreciate that the various modules or steps of the present invention described above can be implemented using a general-purpose computing device, can be centralized on a single computing device, or can be distributed across a network of multiple computing devices. They can be implemented using program code executable by the computing device, and thus, can be stored in a storage device and executed by the computing device. In some cases, the steps shown or described herein can be performed in a different order than that shown, or can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, the present invention is not limited to any particular combination of hardware and software.

[0137] An embodiment of the present application also provides a memory, including a power timing control unit and a memory array, wherein the power timing control unit is used to execute any one of the above-mentioned methods for controlling the memory voltage generation sequence; the memory array is electrically connected to the power timing control unit, the memory array includes a word line and multiple memory cells, the memory cells include electrically connected storage capacitors and switching transistors, and the word line is used to control the conduction or cutoff of the word line.

[0138] The above-mentioned memory includes a power timing control unit and a storage array. The above-mentioned power timing control unit is used to execute any of the above-mentioned methods. This method first controls the generation of substrate voltage to ensure that other circuits can operate stably, and then controls the generation of plate voltage to reduce the mutual coupling effect between the substrate voltage and the plate voltage, thereby reducing leakage, thereby solving the problem of leakage generated during the power-on startup process of the memory in the prior art.

[0139] In order to generate a voltage inside the storage array, in an optional solution, the above-mentioned memory also includes a voltage generating circuit, which is electrically connected to the above-mentioned power timing control unit. The above-mentioned voltage generating circuit is used to control the timing of generating the substrate voltage of the above-mentioned switching transistor, the plate voltage of the above-mentioned storage capacitor and the reset voltage of the above-mentioned word line according to the signal sent by the above-mentioned power timing control unit. The above-mentioned reset voltage is the default voltage after the above-mentioned word line is turned off.

[0140] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0141] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the steps in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0142] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0143] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0144] In a typical configuration, a computing device includes one or more processors (CPUs), input / output interfaces, network interfaces, and memory.

[0145] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0146] Computer-readable media includes permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. The information can be computer-readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassettes, magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer-readable media does not include transitory computer-readable media (transitory media), such as modulated data signals and carrier waves.

[0147] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or includes elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, commodity, or apparatus that includes the element.

[0148] From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

[0149] 1) In the control method of the memory voltage generation sequence of the present application, first, after receiving the power-on signal, a first start-up signal is issued, the first start-up signal is used to generate the substrate voltage of the switching transistor, and control the substrate voltage to gradually drop to a first predetermined value, the first predetermined value is less than the ground terminal potential of the memory; then, after issuing the first start-up signal, a second start-up signal is issued, the second start-up signal is used to generate the plate voltage of the storage capacitor, and control the plate voltage to rise to a second predetermined value, the second predetermined value is greater than the ground terminal potential, one end of the storage capacitor is connected to the switching transistor, and the other end of the storage capacitor receives the plate voltage. This method first controls the generation of the substrate voltage to ensure that other circuits can work stably, and then controls the generation of the plate voltage, thereby reducing the mutual coupling effect between the substrate voltage and the plate voltage, thereby reducing leakage, and thus solving the problem of leakage generated during the power-on startup process of the memory in the prior art.

[0150] 2) The above-mentioned memory of the present application includes a power timing control unit and a storage array, wherein the power timing control unit is used to execute any of the above-mentioned methods; the storage array is electrically connected to the power timing control unit, the storage array includes a word line and a plurality of storage cells, the storage cells include electrically connected storage capacitors and switching transistors, and the word line is used to control the conduction or cutoff of the word line. The above-mentioned memory includes a power timing control unit and a storage array, wherein the power timing control unit is used to execute any of the above-mentioned methods, which first controls the generation of substrate voltage to ensure that other circuits can work stably, and then controls the generation of plate voltage to reduce the mutual coupling effect between substrate voltage and plate voltage, thereby reducing leakage, thereby solving the problem of leakage generated during the power-on startup process of the memory in the prior art.

[0151] The above description is merely a preferred embodiment of the present application and is not intended to limit the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application shall be included within the scope of protection of the present application.

Claims

1. A method for controlling a memory voltage generation sequence, characterized in that: In a power timing control unit applied to the memory, the memory includes a memory array, the memory array includes a word line and a plurality of memory cells, the memory cells include a storage capacitor and a switching transistor, and the method includes: After receiving the power-on signal, issuing a first start signal, wherein the first start signal is used to generate a substrate voltage of the switching transistor and control the substrate voltage to gradually decrease to a first predetermined value, wherein the first predetermined value is less than a ground potential of the memory; After the first start signal is issued, a second start signal is issued, and the second start signal is used to generate a plate voltage of the storage capacitor and control the plate voltage to rise to a second predetermined value, and the second predetermined value is greater than the ground terminal potential. One end of the storage capacitor is connected to the switching transistor, and the other end of the storage capacitor receives the plate voltage.

2. The method according to claim 1, characterized in that After sending the first start signal, sending a second start signal includes: The second start signal is issued within a predetermined time range after the first start signal is issued.

3. The method according to claim 1, characterized in that After sending the first start signal, sending a second start signal includes: detecting the magnitude of the substrate voltage in real time; The second start signal is issued when the substrate voltage is less than or equal to a third predetermined value, and the third predetermined value is less than the ground potential of the memory and greater than the first predetermined value.

4. The method according to claim 1, wherein After sending the second start signal, the method further includes: After the substrate voltage drops to the first predetermined value, a third start signal is issued, wherein the third start signal is used to generate a reset voltage for the word line in the memory array and control the reset voltage to drop to a fourth predetermined value. The reset voltage is a default voltage after the word line is turned off. The fourth predetermined value is less than the ground terminal potential of the memory and greater than the first predetermined value.

5. The method according to claim 4, characterized in that After receiving the power-on signal and before sending the first start signal, the method further includes: The plate voltage and the reset voltage are controlled to be clamped to the ground potential.

6. The method according to claim 2, characterized in that Before receiving the power-on signal, the method further includes: The substrate voltage is controlled to be clamped to the ground potential.

7. The method according to claim 1, characterized in that The memory further includes a voltage pump, the voltage pump being configured to generate the substrate voltage based on an oscillation signal output by an oscillator. After issuing the second start signal, the method further includes: The frequency of the oscillation signal output by the oscillator is controlled to increase so as to increase the updating frequency of the substrate voltage.

8. The method according to claim 7, characterized in that The method further comprises: After the substrate voltage reaches the first predetermined value, the frequency of the oscillation signal output by the oscillator is controlled to be reduced.

9. The method according to any one of claims 1 to 8, characterized in that After sending the first start signal and before sending the second start signal, the method further includes: A fourth start signal is issued, wherein the fourth start signal is used to generate a precharge voltage of the bit line and control the precharge voltage to rise to a fifth predetermined value, wherein the fifth predetermined value is greater than the ground terminal potential and less than the second predetermined value.

10. The method according to claim 9, characterized in that After sending the fourth start signal, the method further includes: A fifth start signal is issued, where the fifth start signal is used to control the pre-charge voltage to rise to a sixth predetermined value, where the sixth predetermined value is greater than the fifth predetermined value.

11. A memory, characterized in that: include: A power timing control unit, configured to execute the method for controlling the memory voltage generation sequence according to any one of claims 1 to 10; A memory array is electrically connected to the power timing control unit, the memory array includes a word line and a plurality of memory cells, the memory cells include electrically connected storage capacitors and switching transistors, and the word line is used to control the word line to be turned on or off.

12. The memory according to claim 11, wherein: The memory further comprises: A voltage generating circuit is electrically connected to the power timing control unit. The voltage generating circuit is used to control the timing of generating the substrate voltage of the switching transistor, the plate voltage of the storage capacitor and the reset voltage of the word line according to the signal sent by the power timing control unit. The reset voltage is the default voltage after the word line is turned off.

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