Method for reducing the height of the horn and expanding the photoresist etch-back process window

Abstract

The application provides a method for reducing the height of a horn and expanding the photoresist etching process window, which comprises the following steps: providing a substrate, forming STI on the substrate to define an active region, forming a gate structure and a metal silicide on the active region, wherein the gate structure is composed of a pseudo-gate polysilicon layer, a gate nitride layer and a gate oxide layer from bottom to top, and the thickness of the gate oxide layer is a preset value; a first sidewall and a second sidewall on the first sidewall are formed on the sidewall of the gate structure; the gate oxide layer and the first and second sidewalls are ground to the top of the gate nitride layer; a photoresist layer covering the remaining gate structure is formed on the substrate; the photoresist layer and the gate nitride layer, the first and second sidewalls thereunder are etched, so that the first sidewall on the sidewall of the pseudo-gate polysilicon layer is reserved, and the metal silicide is not etched; and the remaining photoresist layer is removed. The method of the application significantly reduces the height of the horn, reduces the number of defects, and expands the upper limit process window of the photoresist etching.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for reducing the height of the photoresist horn and expanding the photoresist back-etching process window. Background Technology

[0002] Please see Figure 1 A semiconductor structure in the prior art includes: a substrate 101, on which an STI is formed to define an active region, and a gate structure and a metal silicide are formed on the active region. The gate structure is composed of a pseudo-gate polysilicon layer 102, a gate nitride layer 103, and a gate oxide layer 104 from bottom to top. The sidewalls of the gate structure have a first sidewall 105 and a second sidewall 106 located on the first sidewall 105.

[0003] like Figure 2 The presence of the horn structure 107 shown affects the photoresist etch-back (PREB) process, causing defects when the photoresist thickness is thick, resulting in incomplete etching of the normal gate, abnormal metal gate filling, and abnormal device performance. Simply changing the photoresist etch-back / interlayer dielectric layer related processes cannot effectively solve the horn structure 107 problem, and will also bring other problems such as metal silicide loss. Therefore, the current safe pass-through window for photoresist etch-back is small and cannot meet the needs of mass production.

[0004] The growth height of the first sidewall 105 is affected by the height of the gate hard mask. While the gate hard mask height is relatively high, the first sidewall 105 is also protected by the second sidewall 106 and photoresist. This makes it impossible for the etching process to effectively reduce the height of the horn structure 107 while ensuring that the metal silicide in the active region is not etched. Therefore, the photoresist back-etching process window is relatively small.

[0005] To solve the above problems, a novel method is needed to reduce the height of the horn and expand the photoresist back-etching process window. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for reducing the height of the horn structure and expanding the photoresist etch-back process window. This method addresses the problem that the presence of the horn structure in the prior art affects the photoresist etch-back process, leading to defects when the photoresist thickness is too thick, resulting in incomplete etching of the normal gate, abnormal metal gate filling, and abnormal device performance. Simply changing the photoresist etch-back / interlayer dielectric layer related processes cannot effectively solve the horn structure problem and will also bring other problems such as metal silicide loss, resulting in a small safe pass-through window for photoresist etch-back, which cannot meet mass production requirements.

[0007] To achieve the above object and other related objects, the present application provides a method for reducing the height of horn and expanding the photoresist etching process window, comprising:

[0008] Step one, providing a substrate, the substrate is formed with STI to define an active region, the active region is formed with a gate structure and a metal silicide, the gate structure is composed of a pseudo-gate polysilicon layer from bottom to top, a gate nitride layer, a gate oxide layer, the thickness of the gate oxide layer is a preset value; the sidewall of the gate structure is formed with a first sidewall and a second sidewall on the first sidewall;

[0009] Step two, grinding the gate oxide layer and the first and second sidewalls to the top of the gate nitride layer;

[0010] Step three, forming a photoresist layer on the substrate to cover the remaining gate structure;

[0011] Step four, etching the photoresist layer and the gate nitride layer, the first and second sidewalls thereunder, so that the first sidewall on the sidewall of the pseudo-gate polysilicon layer is retained, and the metal silicide is not etched;

[0012] Step five, removing the remaining photoresist layer.

[0013] Preferably, the substrate in step one comprises a bulk semiconductor substrate or a silicon-on-insulator substrate.

[0014] Preferably, the material of the gate nitride layer in step one is silicon nitride.

[0015] Preferably, the material of the gate oxide layer in step one is silicon dioxide.

[0016] Preferably, the thickness of the gate oxide layer in step one is 600 to 850 angstroms.

[0017] Preferably, the material of the first sidewall in step one is SiCN.

[0018] Preferably, the material of the second sidewall in step one is SiN.

[0019] Preferably, the metal silicide in step one is nickel silicide.

[0020] Preferably, the method of grinding in step two is chemical mechanical planarization grinding.

[0021] Preferably, the method of etching in step four is wet etching.

[0022] As described above, the method for reducing the height of horn and expanding the photoresist etching process window of the present application has the following beneficial effects:

[0023] The method of the present application significantly reduces the height of the horn, improves the horn by more than 30%, improves the in-plane uniformity, effectively reduces the difficulty of the photoresist etch-back to the metal gate forming process, reduces the concave situation caused by chemical mechanical planarization grinding, reduces the number of defects, and expands the upper limit process window of the photoresist etch-back. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 A semiconductor structure schematic diagram of the prior art is shown;

[0025] Figure 2 A horn structure schematic diagram of the prior art is shown;

[0026] Figure 3 A process flow schematic diagram of the present application is shown;

[0027] Figure 4 A semiconductor structure schematic diagram of the present application is shown;

[0028] Figure 5 A horn structure schematic diagram of the present application is shown. DETAILED DESCRIPTION

[0029] The embodiments of the present application will be described in detail with specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the disclosure. The present application can also be implemented or applied by different specific embodiments, and various modifications or changes can be made to the details in the specification without departing from the spirit of the present application.

[0030] Referring to Figure 3 The present application provides a method for reducing the height of the horn and expanding the process window of the photoresist etch-back, comprising:

[0031] Step one, referring to Figure 4 A substrate 201 is provided, and STI is formed on the substrate 201 to define an active region, a gate structure and a metal silicide are formed on the active region, the gate structure is composed of a pseudo gate polysilicon layer 202, a gate nitride layer 203 and a gate oxide layer 204 from bottom to top, the thickness of the gate oxide layer 204 is a preset value, which is thinner than the normal thickness of the gate oxide layer 204 in the prior art, which can reduce the total thickness of the gate nitride layer 203 and the gate oxide layer 204, thereby reducing the height of the first side wall 205; the sidewall of the gate structure is formed with a first side wall 205 and a second side wall 206 located on the first side wall 205; ALD technology (atomic layer deposition technology) can be used to form the first and second side walls.

[0032] Preferably, the substrate 201 in step one comprises a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate comprises an insulator layer under a thin semiconductor layer as an active layer of the SOI substrate. The semiconductor of the active layer and the bulk semiconductor generally comprise a crystalline semiconductor material silicon, but can also comprise one or more other semiconductor materials, such as germanium, silicon-germanium alloy, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, etc.) or alloys thereof (e.g., GaxAl1-xAs, GaxAl1-xN, InxGa1-xAs, etc.), oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3, etc.) or combinations thereof. The semiconductor material can be doped or undoped. Other substrates that can be used include multilayer substrates, graded substrates or hybrid orientation substrates.

[0033] Preferably, the material of the gate nitride layer 203 in step one is silicon nitride.

[0034] Preferably, the material of the gate oxide layer 204 in step one is silicon dioxide.

[0035] Preferably, the thickness of the gate oxide layer 204 in step one is 600 to 850 angstroms. That is, the thickness of the gate oxide layer 204 in the present application is thinner than the normal thickness of the gate oxide layer 204 in the prior art by 100 to 200 angstroms.

[0036] Preferably, the material of the first side wall 205 in step one is SiCN. The etching rate of wet etching can be reduced by doping C atoms in SIN. Generally, a layer of SiCN material is deposited, and then the first side wall 205 is formed by etching back. Since the thickness of the gate oxide layer 204 is controlled in the previous step, the height of the first side wall 205 is reduced.

[0037] Preferably, the material of the second side wall 206 in step one is SiN. Generally, a layer of SiN material is deposited, and then the second side wall 206 is formed by etching back.

[0038] Preferably, the metal silicide in step one is nickel silicide. The method for forming the nickel silicide can be as follows: after the substrate 201 is pre-processed to remove the oxide on the surface, the substrate is sent into a high-vacuum sealed cavity, and a thin film layer of nickel and a protective layer are sequentially sputtered and deposited on the surface of the semiconductor device. The device after the deposition is subjected to a first high-temperature annealing. The unreacted thin film layer of nickel and the protective layer after the high-temperature annealing are removed by wet etching. Finally, the device is subjected to a second high-temperature annealing.

[0039] Step two: grinding the gate oxide layer 204 and the first and second side walls to the top of the gate nitride layer 203;

[0040] Preferably, the polishing method in step two is chemical mechanical planarization polishing.

[0041] Step three, forming a photoresist layer covering the remaining gate structure on the substrate 201;

[0042] Step four, etching the photoresist layer and the gate nitride layer 203, the first and second side walls under the photoresist layer, so that the first side wall 205 on the sidewall of the dummy gate polysilicon layer 202 remains, the metal silicide is not etched, and a structure as shown in Figure 5 is formed; that is, by controlling the thickness of the gate oxide layer 204, the height of the first side wall 205 is reduced, the height of the horn structure 207 to be etched and removed is reduced, and the upper limit process window of the photoresist etch-back is expanded.

[0043] Preferably, the etching method in step four is wet etching.

[0044] Step five, removing the remaining photoresist layer, usually treating the photoresist layer with an ashing process, and then wet cleaning the substrate 201.

[0045] It should be noted that the drawings provided in the embodiments only schematically illustrate the basic concepts of the present application, and only the components related to the present application are shown in the drawings, rather than the number, shape and size of the components when actually implemented. The actual implementation of each component can be a random change, and the component layout pattern can be more complex.

[0046] In summary, the method of the present application significantly reduces the horn height, improves the horn by more than 30%, improves the in-plane uniformity, effectively reduces the difficulty of the photoresist etch-back to metal gate forming process, reduces the concave situation caused by chemical mechanical planarization polishing, reduces the number of defects, and expands the upper limit process window of the photoresist etch-back. Therefore, the present application effectively overcomes the various shortcomings in the prior art and has high industrial utilization value.

[0047] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not intended to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical idea disclosed by the present application should be covered by the claims of the present application.

Claims

1. A method for reducing the height of the photoresist horn and expanding the photoresist back-etching process window, characterized in that, At least comprising: Step one, providing a substrate, the substrate is formed with STI to define active region, the active region is formed with gate structure and metal silicide, the gate structure is composed of bottom-up pseudo gate polysilicon layer, gate nitride layer, gate oxide layer, the thickness of the gate oxide layer is 600-850 angstrom; the sidewall of the gate structure is formed with first sidewall and second sidewall on the first sidewall, the material of the first sidewall is SiCN, the material of the second sidewall is SiN; Step two, grinding the gate oxide layer and the first and second sidewalls to the top of the gate nitride layer; Step three, forming photoresist layer on the substrate to cover the remaining gate structure; Step four, etching the photoresist layer and the gate nitride layer, the first and second sidewalls thereunder, so that the first sidewall on the sidewall of the pseudo gate polysilicon layer remains, and the metal silicide is not etched; Step five, removing the remaining photoresist layer.

2. The method of reducing the height of the horn, enlarging the photoresist etch back process window of claim 1, wherein: The substrate in step one comprises bulk semiconductor substrate or silicon-on-insulator substrate.

3. The method of reducing the height of the horn, expanding the photoresist etch back process window of claim 1, wherein: The material of the gate nitride layer in step one is silicon nitride.

4. The method of reducing the height of the horn, expanding the photoresist etch back process window of claim 1, wherein: The material of the gate oxide layer in step one is silicon dioxide.

5. The method of reducing the height of the horn, expanding the photoresist etch back process window of claim 1, wherein: The metal silicide in step one is nickel silicide.

6. The method of reducing the height of the horn, expanding the photoresist etch back process window of claim 1, wherein: The method of grinding in step two is chemical mechanical planarization grinding.

7. The method of reducing the height of the horn, expanding the photoresist etch back process window of claim 1, wherein: The method of etching in step four is wet etching.

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