Array substrate, manufacturing method thereof, and detection device

Abstract

The embodiments of the present application provide an array substrate, a manufacturing method thereof, and a detection device. The array substrate includes: a thin-film transistor structure, disposed on one side of a substrate; the thin-film transistor structure includes an active structure, a gate, and a source-drain electrode, the gate being disposed on the side of the active structure away from the substrate, and the source-drain electrode being disposed on the side of the gate away from the active structure; a first electrode structure, disposed on one side of the substrate; the first electrode structure and the active structure being in the same layer and separated from each other, and electrically connected via the source-drain electrode; a photoelectric device structure, disposed on the side of the first electrode structure away from the substrate; and a light-shielding structure, disposed between the thin-film transistor structure and the substrate, and electrically connected to the source-drain electrode. The array substrate provided by the embodiments of the present application effectively reduces light leakage noise and effectively reduces X-ray exposure dose.

Description

Technical Field

[0001] The present application relates to the field of photoelectric detection technology. Specifically, the present application relates to an array substrate, a manufacturing method thereof, and a detection device. Background Art

[0002] The array substrate of an X-ray detector primarily consists of thin-film transistors (TFTs) and photodiodes. X-rays are converted into visible light signals by the array substrate's fluorescent dielectric material. The photosensitive element then converts the visible light signals into electrical signals, which are then transmitted via the TFTs to the electrical signal receiving end. A digital-to-analog converter then converts the analog electrical signals into digital signals, ultimately presenting an image.

[0003] X-rays are harmful to the human body, so it's important to minimize the amount of X-rays used. However, reducing the amount of X-rays results in a smaller photocurrent. Furthermore, in related technologies, the thin-film transistors (TFTs) on the array substrate are easily affected by external light, generating photocurrents and consequently, large noise electrical signals. This affects the electrical performance of the TFTs, making it impossible for the array substrate to effectively reduce X-ray exposure. Summary of the Invention

[0004] In view of the shortcomings of the existing methods, this application proposes an array substrate and its manufacturing method, as well as a detection device, to solve the technical problems in related technologies such as large optical leakage noise of flat panel detectors and inability to effectively reduce X-ray exposure dose.

[0005] In the first aspect, an embodiment of the present application provides an array substrate, comprising at least one photosensitive sub-pixel, the photosensitive sub-pixel comprising: a substrate; a thin-film transistor structure, arranged on one side of the substrate, the thin-film transistor structure comprising an active structure, a gate, and a source and drain, the gate being arranged on a side of the active structure away from the substrate, and the source and drain being arranged on a side of the gate away from the active structure; a first electrode structure, arranged on one side of the substrate; the first electrode structure and the active structure are in the same layer and separated from each other, and are electrically connected through the source and drain; a photoelectric device structure, arranged on a side of the first electrode structure away from the substrate; a source and drain, arranged on a side of both the active structure and the first electrode structure away from the substrate; a light-shielding structure, arranged between the thin-film transistor structure and the substrate, the light-shielding structure being electrically connected to the source and drain.

[0006] Optionally, the oxide semiconductor material of the active structure is the same as the oxide semiconductor material of the first electrode structure, and the carrier mobility of the active structure is different from the carrier mobility of the first electrode structure.

[0007] Optionally, the flat-panel detector further includes: a first interlayer dielectric layer, covering the gate and the first electrode structure; the source and drain are arranged on a side of the first interlayer dielectric layer away from the active structure and the first electrode structure; the source and drain include a first source and drain; the first source and drain are electrically connected to the first source and drain region of the active structure through a first sub-via of the first via of the first interlayer dielectric layer, and electrically connected to the first electrode structure through a third via of the first interlayer dielectric layer.

[0008] Optionally, the orthographic projection of the light-shielding structure on the substrate at least overlaps with the orthographic projection of the channel region of the active structure on the substrate; and the light-shielding structure is electrically connected to the first source and drain region of the active structure through the source and drain electrodes.

[0009] Optionally, the array substrate also includes: a buffer layer covering the shading structure and the base, and a first interlayer dielectric layer covering the gate and the first electrode structure; the first source and drain of the source and drain are electrically connected to the shading structure through the first interlayer dielectric layer and the second via hole of the buffer layer.

[0010] Optionally, the first interlayer dielectric layer is provided with a through groove in a partial area covering the first electrode structure, and the optoelectronic device structure is arranged in the through groove of the first interlayer dielectric layer; along the first direction, the size of the optoelectronic device structure is not larger than the size of the first interlayer dielectric layer, and the first direction refers to the direction perpendicular to the substrate; the optoelectronic device structure is electrically connected to the first electrode structure.

[0011] Optionally, along the second direction, the size of the first electrode structure is larger than the size of the active structure; the third direction is parallel to the substrate and points from the active structure to the first electrode structure, and the second direction is parallel to the substrate and perpendicular to the third direction.

[0012] In a second aspect, an embodiment of the present application provides a detection device, comprising: an array substrate as described in the first aspect.

[0013] In a third aspect, an embodiment of the present application provides a method for manufacturing the array substrate described in the first aspect, comprising: manufacturing a light-shielding structure on one side of a substrate; manufacturing an active structure of a thin-film transistor structure on a side of the light-shielding structure away from the substrate, and manufacturing an oxide semiconductor thin film structure that is located in the same layer as the active structure and separated from each other on a side of the substrate not covered by the light-shielding structure; conducting the oxide semiconductor thin film structure into a first electrode structure; manufacturing a gate on a side of the active structure away from the light-shielding structure; manufacturing a photoelectric device structure on a side of the first electrode structure away from the substrate; manufacturing a source and drain of a thin-film transistor on a side where both the active structure and the first electrode structure are away from the substrate, and electrically connecting the source and drain to the active structure, the first electrode structure, and the light-shielding structure.

[0014] Optionally, before manufacturing the optoelectronic device structure on the side of the first electrode structure away from the substrate, it also includes: manufacturing a buffer layer covering the shading structure and the substrate; manufacturing a first interlayer dielectric layer covering the gate and the first electrode structure; opening a first via in the first interlayer dielectric layer covering the first source and drain region of the active structure, opening a third via at the edge region covering the first electrode structure, opening a through groove in the partial region covering the first electrode structure, and opening a second via at the edge region where the first interlayer dielectric layer and the buffer layer cover the shading structure; preparing source and drain electrodes on the side of the first interlayer dielectric layer away from the substrate; so that the first source and drain electrodes are electrically connected to the first source and drain region through the first via hole, electrically connected to the shading structure through the second via hole, and electrically connected to the first electrode structure through the third via hole.

[0015] The beneficial technical effects brought about by the technical solutions provided in the embodiments of the present application include:

[0016] In the array substrate provided by the embodiment of the present application, the active structure of the thin-film transistor structure is arranged on one side of the substrate, the gate of the thin-film transistor structure is arranged on the side of the active structure away from the light-shielding structure, the light-shielding structure is arranged between the active structure and the substrate, and the first electrode structure is arranged on one side of the substrate; the active structure and the first electrode structure are in the same layer and separated from each other, and are electrically connected through the source and drain electrodes. By arranging the light-shielding structure on the side of the active structure close to the substrate and the gate on the side of the active structure away from the substrate, the photocurrent generated in the channel region of the active structure due to the influence of external light is reduced, thereby reducing the noise signal, making the optical leakage noise of the array substrate small, and improving the stability of the array substrate. By separating the active structure and the first electrode structure and electrically connecting them through the source and drain electrodes, the resistance of the electrical signal transmission can be reduced, and the sensitivity of the array substrate can be improved.

[0017] Additional aspects and advantages of the present application will be given in part in the following description, which will become apparent from the following description, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0019] Figure 1 A top view of an array substrate provided in an embodiment of the present application;

[0020] Figure 2 A cross-sectional view of an array substrate provided in an embodiment of the present application;

[0021] Figure 3 A schematic flow chart of a method for manufacturing an array substrate provided in an embodiment of the present application;

[0022] Figure 4 A schematic flow chart of a patterning process in a method for manufacturing an array substrate provided in an embodiment of the present application;

[0023] Figure 5a A top view of a substrate after a light shielding structure is fabricated on one side of the substrate according to an embodiment of the present application;

[0024] Figure 5b This is a cross-sectional view of an embodiment of the present application after a light shielding structure is manufactured on one side of the substrate;

[0025] Figure 6a This is a top view of the active structure and the first electrode structure after patterning according to an embodiment of the present application;

[0026] Figure 6b This is a cross-sectional view of the active structure and the first electrode structure after patterning according to an embodiment of the present application;

[0027] Figure 7a This is a top view of the gate after patterning in an embodiment of the present application;

[0028] Figure 7b This is a cross-sectional view of the gate after patterning in an embodiment of the present application;

[0029] Figure 8a This is a top view of the first interlayer dielectric layer after patterning in an embodiment of the present application;

[0030] Figure 8b This is a cross-sectional view of the first interlayer dielectric layer after patterning in an embodiment of the present application;

[0031] Figure 9a This is a top view of the source and drain after patterning in the embodiment of the present application;

[0032] Figure 9b This is a cross-sectional view of the source and drain electrodes after patterning in an embodiment of the present application;

[0033] Figure 10a This is a top view of an embodiment of the present application after a photoelectric device structure is disposed in the through groove of the first interlayer dielectric layer;

[0034] Figure 10b This is a cross-sectional view of an embodiment of the present application after a photoelectric device structure is provided in the through-groove of the first interlayer dielectric layer;

[0035] Figure 11a This is a top view of the second interlayer dielectric layer after patterning in an embodiment of the present application;

[0036] Figure 11b This is a cross-sectional view of the second interlayer dielectric layer after patterning in an embodiment of the present application;

[0037] Figure 12a This is a top view of the second electrode structure after patterning in an embodiment of the present application;

[0038] Figure 12b This is a cross-sectional view of the second electrode structure after patterning according to an embodiment of the present application.

[0039] In the picture:

[0040] 100-base; 200-shading structure;

[0041] 300 - thin film transistor structure; 310 - active structure; 311 - channel region; 312 - first source and drain region; 313 - second source and drain region; 320 - gate; 330 - gate insulation layer; 340 - source and drain; 341 - first source and drain; 342 - second source and drain;

[0042] 400-first electrode structure; 600-second electrode structure;

[0043] 500-photoelectric device structure; 510-N-type semiconductor layer, 520-intrinsic semiconductor layer; 530-P-type semiconductor layer;

[0044] 700 - first interlayer dielectric layer; 710 - first via hole; 720 - through groove; 730 - third via hole; 740 - fourth via hole; 800 - buffer layer; 810 - second via hole;

[0045] 900 - second interlayer dielectric layer; 910 - fifth via hole. DETAILED DESCRIPTION

[0046] The following describes the embodiments of the present application in conjunction with the accompanying drawings. It should be understood that the embodiments described below in conjunction with the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions of the embodiments of the present application.

[0047] Those skilled in the art will understand that, unless otherwise stated, the singular forms "a", "an", "said", and "the" used herein may also include plural forms. It should be further understood that the term "comprising" used in the specification of this application refers to the presence of the described features, integers, steps, operations, elements and / or components, but does not exclude the implementation of other features, information, data, steps, operations, elements, components and / or combinations thereof supported by the technical field. The term "and / or" used herein refers to at least one of the items defined by the term, for example, "A and / or B" can be implemented as "A", or as "B", or as "A and B".

[0048] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0049] First, the relevant technologies involved in this application are described:

[0050] The inventors of this application have discovered through research that X-rays are harmful to the human body, and therefore it is desirable to minimize X-ray exposure. However, reducing the amount of X-rays results in a smaller photocurrent. Furthermore, in related art, the thin-film transistors (TFTs) in flat-panel detectors are easily affected by external light, generating photocurrents that, in turn, produce large noise signals, affecting the electrical performance of the TFTs. This results in the TFTs being unable to effectively reduce X-ray exposure.

[0051] The following is a detailed description of the technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems with specific embodiments. It should be noted that the following embodiments can refer to, draw on, or combine with each other, and the same terms, similar features, and similar implementation steps in different embodiments will not be repeated.

[0052] The embodiment of the present application provides an array substrate, which includes at least one photosensitive sub-pixel. Figure 1-2 As shown, it includes: a substrate 100.

[0053] The thin film transistor structure 300 is arranged on one side of the substrate 100. The thin film transistor structure 300 includes an active structure 310, a gate 320 and a source and drain 340. The gate 320 is arranged on the side of the active structure 310 away from the substrate 100, and the source and drain 340 is arranged on the side of the gate 320 away from the active structure 310.

[0054] The first electrode structure 400 is disposed on one side of the substrate 100 . The first electrode structure 400 and the active structure 320 are in the same layer and separated from each other, and are electrically connected via the source and drain electrodes 340 .

[0055] The optoelectronic device structure 500 is disposed on a side of the first electrode structure 400 away from the substrate 100 .

[0056] The light shielding structure 200 is disposed between the thin film transistor structure 300 and the substrate 100 . The light shielding structure 200 is electrically connected to the source and drain electrodes 340 .

[0057] Optionally, in the top view of the array substrate, the projections of the substrate 100, the first interlayer dielectric layer 700, the buffer layer 800, and the second interlayer dielectric layer 900 overlap with each other and cover other structures. Therefore, in order to more clearly reflect the relationship between other structures, the present application Figure 2 The base 100 , the first interlayer dielectric layer 700 , the buffer layer 800 and the second interlayer dielectric layer 900 are omitted in the top view of the array substrate.

[0058] In the array substrate provided by the embodiment of the present application, the active structure 310 of the thin-film transistor structure 300 is arranged on the side of the light-shielding structure 200 away from the substrate 100, the gate 320 of the thin-film transistor structure 300 is arranged on the side of the active structure 310 away from the light-shielding structure 200, the light-shielding structure 200 is arranged between the active structure 310 and the substrate 100, and the first electrode structure 400 is arranged on the side of the substrate 100; the active structure 310 and the first electrode structure 400 are in the same layer and separated from each other, and are electrically connected via the source and drain electrodes 340. By providing the light-shielding structure 200 on the side of the active structure 310 close to the substrate 100 and the gate 320 on the side of the active structure 310 away from the substrate 100, the photocurrent generated in the channel region 311 of the active structure 310 due to the influence of external light is reduced, thereby reducing the noise signal, reducing the optical leakage noise of the array substrate, and improving the stability of the detector. By separating the active structure 310 and the first electrode structure 400 and electrically connecting them through the source and drain electrodes 340 , the resistance of electrical signal transmission can be reduced and the sensitivity of the array substrate can be improved.

[0059] Moreover, the active structure 310 and the first electrode structure 400 are disposed in the same layer, which is beneficial to simplifying the process.

[0060] Alternatively, in one embodiment of the present application, see Figure 1-2 As shown, the oxide semiconductor material of the active structure 310 is the same as the oxide semiconductor thin film material of the first electrode structure 400 , and the carrier mobility of the active structure 310 is different from that of the first electrode structure 400 .

[0061] Optionally, in the embodiment of the present application, the active structure 310 and the first electrode structure 400 are in the same layer. The active structure 310 is an oxide semiconductor thin film structure, and the first electrode structure 400 is a conductive oxide semiconductor thin film structure. Optionally, the oxide semiconductor material of the first electrode structure 400 is the same as the oxide semiconductor material of the active structure 310, and both can be one or a combination of indium gallium zinc oxide, indium tin zinc oxide, or indium gallium zinc tin oxide. Optionally, the degree of conductivity of the oxide semiconductor thin film structure is proportional to the carrier mobility in the oxide semiconductor thin film structure, and the carrier mobility of the oxide semiconductor thin film structure increases with the increase in the degree of conductivity; the carrier mobility of the conductive oxide semiconductor thin film structure is higher than the carrier mobility of the non-conductive oxide semiconductor thin film structure, so the carrier mobility in the first electrode structure 400 is higher than the carrier mobility in the active structure 310. Using the same oxide semiconductor material for the active structure 310 and the first electrode structure 400 is conducive to simplifying the process.

[0062] Optionally, the active structure 310 and the first electrode structure 400 located in the same layer have a thickness ranging from 100 to 1000 Å. The gate 320 may be made of an alloy of one or more of molybdenum, aluminum, copper, and titanium, and have a thickness ranging from 2000 to 6000 Å. The source and drain electrodes 340 may be made of an alloy of one or more of molybdenum, aluminum, copper, and titanium, and have a thickness ranging from 2000 to 6000 Å.

[0063] Alternatively, in one embodiment of the present application, see Figure 1-2 As shown, the array substrate also includes: a first interlayer dielectric layer 700, covering the gate 320 and the first electrode structure 400; the source and drain 340 are arranged on the side of the first interlayer dielectric layer 700 away from the active structure 310 and the first electrode structure 400; the source and drain 340 include a first source and drain 341; the first source and drain 341 is electrically connected to the first source and drain region 312 of the active structure 310 through the first via 710 of the first interlayer dielectric layer 700, and is electrically connected to the first electrode structure 400 through the third via 730 of the first interlayer dielectric layer 700.

[0064] Optionally, in the embodiment of the present application, the first electrode structure 400 may be a cathode. The first source / drain electrode 341 may be a source or a drain, with the first source / drain electrode 341 being at a high potential. The material of the first interlayer dielectric layer 700 may be silicon oxide, silicon oxynitride, or a combination thereof, and the thickness of the first interlayer dielectric layer 700 may be in the range of 1000-3000 Å.

[0065] In an embodiment of the present application, the first source and drain electrode 341 is electrically connected to the first source and drain region 312 of the active structure 310 through the first via 710 of the first interlayer dielectric layer 700, and the first source and drain electrode 341 is electrically connected to the first electrode structure 400 through the third via 730 of the first interlayer dielectric layer 700, which can reduce the resistance of electrical signal transmission, thereby improving the sensitivity of the array substrate.

[0066] Alternatively, in one embodiment of the present application, see Figure 1-2 As shown, the orthographic projection of the light shielding structure 200 on the substrate 100 at least overlaps with the orthographic projection of the channel region 311 of the active structure 310 on the substrate 100 ; the light shielding structure 200 is electrically connected to the first source and drain region 312 of the active structure 310 through the source and drain electrodes 340 .

[0067] Optionally, in an embodiment of the present application, the light-shielding structure 200 is conductive, and the material of the light-shielding structure 200 may be an alloy of one or more of molybdenum, aluminum, copper, and titanium, and the thickness of the light-shielding structure 200 is 2000-6000A. After the gate 320 is turned on, a conductive channel is formed on the side of the active structure 310 close to the gate 320, so that a large number of electrons are gathered on the side of the active structure 310 close to the gate 320. The light-shielding structure 200 is electrically connected to the first source and drain region 312 of the active structure 310 through the source and drain electrodes 340, so there is charge on the light-shielding structure 200. The light-shielding structure 200 forms a conductive channel on the side of the active structure 310 close to the light-shielding structure 200, so that a large number of electrons are gathered on the side of the active structure 310 close to the light-shielding structure 200. Since a large number of electrons are gathered on both sides of the active structure 310, the mobility of the carriers in the channel region 311 of the thin film transistor structure 300 is improved. Therefore, the light shielding structure 200 is electrically connected to the first source and drain region 312 of the active structure 310 through the source and drain electrodes 340 , which can effectively improve the mobility of carriers in the channel region 311 of the thin film transistor structure 300 , thereby improving the response speed of the thin film transistor 300 .

[0068] Alternatively, in one embodiment of the present application, see Figure 1-2 As shown, the array substrate also includes: a buffer layer 800 covering the shading structure 200 and the substrate 100, and a first interlayer dielectric layer 700 of the gate 320 and the first electrode structure 400; the first source and drain 341 of the source and drain 340 is electrically connected to the shading structure 200 through the first interlayer dielectric layer 700 and the second via 810 of the buffer layer 800.

[0069] Optionally, in the embodiment of the present application, a via hole that penetrates both the first interlayer dielectric layer 700 and the buffer layer 800 is defined as a second via hole 810. The buffer layer 800 covers the light shielding structure 200 and the substrate 100. The material of the buffer layer 800 can be a combination of silicon nitride and silicon oxide. The thickness of the buffer layer 800 is 2000-5000 Å.

[0070] Alternatively, in one embodiment of the present application, see Figure 1-2 As shown, the first interlayer dielectric layer 700 is provided with a through groove 720 in a partial area covering the first electrode structure 400, and the optoelectronic device structure 500 is arranged in the through groove 720 of the first interlayer dielectric layer 700; along the first direction, the size of the optoelectronic device structure 500 is not larger than the size of the first interlayer dielectric layer 700, and the first direction refers to the direction perpendicular to the substrate 100; the optoelectronic device structure 500 is electrically connected to the first electrode structure 400.

[0071] Optionally, in the embodiment of the present application, the dimension of the optoelectronic device structure 500 along the first direction refers to the thickness of the optoelectronic device structure 500. The first direction refers to the thickness direction of the optoelectronic device structure 500. The optoelectronic device structure 500 is disposed in the through groove 720 of the first interlayer dielectric layer 700. The optoelectronic device structure 500 is sequentially stacked with an N-type semiconductor layer 510, an intrinsic semiconductor layer 520, and a P-type semiconductor layer 530 along the direction from the substrate 100 to the first interlayer dielectric layer 700. The second interlayer dielectric layer 900 covers the source and drain electrodes 340 and the optoelectronic device structure 500. The via penetrating the second interlayer dielectric layer 900 is defined as a fifth via 910. The second electrode structure 600 is electrically connected to the P-type semiconductor structure 530 through the fifth via 910, and the N-type semiconductor layer 510 is electrically connected to the first electrode structure 400.

[0072] Optionally, in an embodiment of the present application, the material of the second interlayer dielectric layer 900 may be silicon oxide, silicon nitride, or a combination thereof, and the thickness of the second interlayer dielectric layer 900 may be 2000-5000 Å. The material of the second electrode structure 600 may be an alloy of one or more of molybdenum, aluminum, copper, and titanium, and the thickness of the second electrode structure 600 may be 2000-6000 Å. The thickness of the N-type semiconductor layer 510 may be 300-900 Å; the thickness of the intrinsic semiconductor layer 520 may be 5000-18000 Å; and the thickness of the P-type semiconductor layer 530 may be 300-900 Å. The function of the optoelectronic device structure 500 includes converting visible light into electrical signals.

[0073] Optionally, in one embodiment of the present application, Figure 1-2As shown, along the second direction, the size of the first electrode structure 400 is larger than the size of the active structure 310; the third direction is parallel to the substrate 100 and points from the active structure 310 to the first electrode structure 400, and the second direction is parallel to the substrate 100 and perpendicular to the third direction.

[0074] Optionally, in the embodiment of the present application, the dimension of the first electrode structure 400 along the third direction is greater than the dimension along the second direction. The second direction refers to the width direction of the first electrode structure 400, and the third direction refers to the length direction of the first electrode structure 400. Along the second direction, the dimension of the first electrode structure 400 is greater than the dimension of the active structure 310. The active structure 310 is separated from the first electrode structure 400 and electrically connected via the source and drain electrodes 340, which has a lower resistance than a direct connection between the active structure 310 and the first electrode structure 400. Therefore, the separation of the active structure 310 from the first electrode structure 400 and the electrical connection via the source and drain electrodes 340 can reduce the resistance of electrical signal transmission and improve the sensitivity of the array substrate.

[0075] Based on the same inventive concept, an embodiment of the present application further provides a detection device, comprising the array substrate of the first aspect.

[0076] In the embodiment of the present application, the detection device includes an X-ray flat panel detection device. Since the detection device adopts any of the array substrates provided in the above embodiments, its principles and technical effects can be referred to in the above embodiments and will not be described in detail here.

[0077] Based on the same inventive concept, the present application also provides a method for manufacturing the array substrate of the first aspect. The flow chart of the method is as follows: Figure 3 As shown, the steps include:

[0078] S301 : manufacturing a light shielding structure 200 on one side of the substrate 100 .

[0079] S302: Manufacturing an active structure 310 of the thin film transistor structure 300 on a side of the light-shielding structure 200 away from the substrate 100, and manufacturing an oxide semiconductor thin film structure located in the same layer as the active structure 310 and separated from each other on a side of the substrate not covered by the light-shielding structure 200; and conducting the oxide semiconductor thin film structure into a first electrode structure 400.

[0080] S303: manufacturing a gate 320 on a side of the active structure 310 away from the light shielding structure 200;

[0081] S304 : manufacturing a photoelectric device structure 500 on a side of the first electrode structure 400 away from the substrate 100 .

[0082] S305 : On the side of the active structure 310 and the first electrode structure 400 away from the substrate 100 , fabricate the source and drain electrodes 340 of the thin film transistor 300 , and electrically connect the source and drain electrodes 340 to the active structure 310 , the first electrode structure 400 , and the light shielding structure 200 .

[0083] An embodiment of the present application provides a method for manufacturing an array substrate, in which an active structure 310 and a first electrode structure 400 are placed in the same layer and separated from each other; the active structure 310 and the first electrode structure 400 are electrically connected through a source-drain electrode 340, thereby reducing the resistance of electrical signal transmission and improving the sensitivity of the array substrate.

[0084] In some possible implementations, in the above step S304, before manufacturing the optoelectronic device structure 500 on the side of the first electrode structure 400 away from the substrate 100, as shown in FIG. Figure 4 As shown, the steps include:

[0085] S401 : manufacturing a buffer layer 800 covering the light shielding structure 200 and the substrate 100 .

[0086] S402 : manufacturing a first interlayer dielectric layer 700 covering the gate 320 and the first electrode structure 400 .

[0087] S403: A first via hole 710 is opened in the first interlayer dielectric layer 700 at the first source / drain region 312 covering the active structure 310, a third via hole 730 is opened at the edge region covering the first electrode structure 400, a through groove 720 is opened at a partial region covering the first electrode structure 400, and a second via hole 810 is opened at the edge region of the first interlayer dielectric layer 700 and the buffer layer 800 covering the light-shielding structure 200.

[0088] S404: Prepare a source and drain electrode 340 on a side of the first interlayer dielectric layer 700 away from the substrate 100; make the first source and drain electrode 341 of the source and drain electrode 340 electrically connected to the first source and drain region 312 through the first via 710, electrically connected to the shading structure 200 through the second via 810, and electrically connected to the first electrode structure 400 through the third via 730.

[0089] Optionally, in an embodiment of the present application, the light-shielding structure 200 is conductive, and the material of the light-shielding structure 200 may be an alloy of one or more of molybdenum, aluminum, copper, and titanium. After the gate 320 is turned on, a conductive channel will be formed on the side of the active structure 310 close to the gate 320, so that a large number of electrons are gathered on the side of the active structure 310 close to the gate 320. The light-shielding structure 200 is electrically connected to the first source and drain region 312 of the active structure 310 through the source and drain electrodes 340, so there is charge on the light-shielding structure 200, and the light-shielding structure 200 will form a conductive channel on the side of the active structure 310 close to the light-shielding structure 200, so that a large number of electrons are gathered on the side of the active structure 310 close to the light-shielding structure 200. Since a large number of electrons are gathered on both sides of the active structure 310, the mobility of the carriers in the channel region 311 of the thin film transistor structure 300 is improved. Therefore, the light shielding structure 200 is electrically connected to the first source and drain region 312 of the active structure 310 through the source and drain electrodes 340 , which can effectively improve the mobility of carriers in the channel region 311 of the thin film transistor structure 300 , thereby improving the response speed of the thin film transistor 300 .

[0090] Refer to the following Figure 5a-12a and Figure 5b-12b , a specific example of the method for manufacturing the array substrate provided in an embodiment of the present application is introduced in detail:

[0091] In the top view of the embodiment of the present application, since the projections of the substrate 100, the first interlayer dielectric layer 700, the second interlayer dielectric layer 900 and the buffer layer 800 overlap with each other and cover the projections of other structures, in order to more clearly reflect the positional relationship between other structures, Figure 5a-12a The substrate 100, the first interlayer dielectric layer 700, the second interlayer dielectric layer 900 and the buffer layer 800 are omitted in the top view. Figure 5a-12a The horizontal dashed lines in are hatching lines, for example, Figure 5b yes Figure 5a The cross-sectional view obtained by cutting along the horizontal dotted line is: Figure 6b-12b Same thing.

[0092] (1) A light shielding structure 200 is manufactured on one side of the substrate 100 .

[0093] See also Figure 5a and Figure 5b As shown, an initial light-shielding structure is deposited on one side of the substrate 100 , and the initial light-shielding structure is patterned to obtain the light-shielding structure 200 .

[0094] Optionally, the material of the light shielding structure 200 may be an alloy of one or more of molybdenum, aluminum, copper, and titanium, and the thickness of the light shielding structure is within a range of 2000-6000 Å (angstroms).

[0095] (2) Patterning the active structure 310 and the first electrode structure 400 .

[0096] See also Figure 6a and Figure 6b As shown, a buffer layer 800 and an initial active layer are sequentially fabricated on the side of the light-shielding structure 200 away from the substrate 100; the buffer layer 800 covers both the light-shielding structure 200 and the substrate 100. The initial active layer is patterned using photolithography and etching processes to form an active structure 310 and an oxide semiconductor thin film structure co-located with and separated from the active structure 310. The oxide semiconductor thin film structure is then conductively fabricated to form the first electrode structure 400. Fabricating the active structure 310 and the first electrode structure co-located saves time and simplifies the process.

[0097] Optionally, the material of the buffer layer 800 may be a combination of silicon nitride and silicon oxide, and the thickness of the buffer layer 800 may be 2000-5000 Å. The material of the active structure 310 and the first electrode structure 400 may be one or a combination of indium gallium zinc oxide, indium tin zinc oxide, or indium gallium zinc tin oxide, and the thickness of the active structure 310 and the first electrode structure 400 may be 100-1000 Å.

[0098] (3) Patterning the gate 320.

[0099] See also Figure 7a and Figure 7b As shown, an initial gate insulating layer and an initial gate are sequentially fabricated on a side of the active structure 310 away from the light-shielding structure 200. The initial gate insulating layer and the initial gate are patterned using a photolithography process to obtain a gate insulating layer 330 and a gate 320. The active structure 310 not blocked by the gate insulating layer 330 is subjected to a conductorization process. After the conductorization process, the active structure 310 is divided into three parts, including a channel region 311 (the portion blocked by the gate insulating structure 330), a first source and drain region 312 on one side of the channel region 311, and a second source and drain region 313 on the other side of the channel region 311. The active structure 310, the gate insulating structure 330, and the gate 320 constitute a thin film transistor structure 300.

[0100] Optionally, the gate insulating layer 330 may be made of silicon oxide, silicon oxynitride, or a combination thereof, and may have a thickness of 1000-3000 Å. The gate 320 may be made of an alloy of one or more of molybdenum, aluminum, copper, and titanium, and may have a thickness of 2000-6000 Å.

[0101] (4) Patterning the first interlayer dielectric layer 700.

[0102] See also Figure 8a and Figure 8bAs shown, a first interlayer dielectric layer 700 is fabricated on the side of the gate 320 away from the light-shielding structure 200. The first interlayer dielectric layer 700 covers the gate 320 and the first electrode structure 400 of the thin-film crystal structure 300. The first interlayer dielectric layer 700 is patterned. A fourth via 740 is formed in the first interlayer dielectric layer 700, covering the second source / drain region 313. A first via 710 is formed in the first source / drain region 312. A third via 730 is formed in the edge region of the first electrode structure 400. A second via 810 is formed in the edge region where the first interlayer dielectric layer 700 and the buffer layer 800 cover the light-shielding structure 200. A through-groove 720 is formed in the portion of the first interlayer dielectric layer 700 covering the first electrode structure 400.

[0103] Optionally, the material of the first interlayer dielectric layer 700 may be silicon oxide, silicon oxynitride, or a combination thereof, and the thickness of the first interlayer dielectric layer 700 is within a range of 1000-3000 Å.

[0104] (5) Patterning the source and drain electrodes 340 .

[0105] See also Figure 9a and Figure 9b As shown, initial source and drain electrodes are fabricated on a side of the first interlayer dielectric layer 700 away from the gate 320 of the thin-film transistor structure 300 and the first electrode structure 400. The initial source and drain electrodes are patterned to form source and drain electrodes 340, which include a first source and drain electrode 341 and a second source and drain electrode 342. The first source and drain electrode 341 is electrically connected to the first source and drain region 312 through a first via 710, electrically connected to the light shielding structure 200 through a second via 810, and electrically connected to the first electrode structure 400 through a third via 730. The second source and drain electrode 342 is electrically connected to the second source and drain region 313 through a fourth via 740.

[0106] Optionally, the source and drain electrodes 340 may be made of an alloy of one or more of molybdenum, aluminum, copper, and titanium. The thickness of the source and drain electrodes 340 may be 2000-6000 Å.

[0107] (6) The optoelectronic device structure 500 is disposed in the through groove 720 of the first interlayer dielectric layer 700 .

[0108] See also Figure 10a and Figure 10b As shown, an N-type semiconductor layer 510, an intrinsic semiconductor layer 520, and a P-type semiconductor layer 530 are sequentially stacked in the through-grooves 720 of the first interlayer dielectric layer 700, wherein the N-type semiconductor layer 510 is electrically connected to the first electrode structure 400. The function of the optoelectronic device structure 500 includes converting visible light into electrical signals.

[0109] Optionally, the thickness of the N-type semiconductor layer 510 is 300-900 Å, the thickness of the intrinsic semiconductor layer 520 is 5000-18000 Å, and the thickness of the P-type semiconductor layer 530 is 300-900 Å.

[0110] (7) Patterning the second interlayer dielectric layer 900.

[0111] See also Figure 11a and Figure 11b As shown, an initial second interlayer dielectric layer is formed on a side of the first interlayer dielectric layer 700 away from the substrate 100. The initial second interlayer dielectric layer covers the source electrode 340 and the optoelectronic device structure 500. The initial second interlayer dielectric layer is patterned to obtain a second interlayer dielectric layer 900. A fifth via hole 910 is opened where the second interlayer dielectric layer 900 covers the P-type semiconductor layer 530.

[0112] Optionally, the material of the second interlayer dielectric layer 900 may be silicon oxide, silicon nitride, or a combination thereof, and the thickness of the second interlayer dielectric layer 900 is within a range of 2000-5000 Å.

[0113] (8) Patterning the second electrode structure 600.

[0114] See also Figure 12a and Figure 12b As shown, an initial second electrode structure is fabricated on the side of the second interlayer dielectric layer 900 away from the substrate 100 , and the initial second electrode structure is patterned to obtain a second electrode structure 600 . The second electrode structure 600 is electrically connected to the P-type semiconductor layer 530 through a fifth via 910 .

[0115] Optionally, the material of the second electrode structure 600 may be an alloy of one or more of molybdenum, aluminum, copper, and titanium, and the thickness of the second electrode structure 600 is 2000-6000 Å.

[0116] By applying the embodiments of the present application, at least the following beneficial effects can be achieved:

[0117] 1. In an array substrate provided in an embodiment of the present application, an active structure 310 of a thin-film transistor structure 300 is disposed on one side of a substrate 100, a gate 320 of the thin-film transistor structure 300 is disposed on a side of the active structure 310 away from the substrate 100, a light-shielding structure 200 is disposed between the active structure 310 and the substrate 100, and a first electrode structure 400 is disposed on one side of the substrate 100. The active structure 310 and the first electrode structure 400 are located in the same layer and separated from each other, and are electrically connected via a source and drain electrode 340. By disposing the light-shielding structure 200 on the side of the active structure 310 close to the substrate 100 and the gate 320 on the side of the active structure 310 away from the substrate 100, the photocurrent generated in the channel region 311 of the active structure 310 due to the influence of external light is reduced, thereby reducing noise signals, reducing optical leakage noise of the array substrate, and improving the stability of the array substrate. By separating the active structure 310 and the first electrode structure 400 and electrically connecting them through the source and drain electrodes 340 , the resistance of electrical signal transmission can be reduced and the sensitivity of the array substrate can be improved.

[0118] 2. When the gate 320 is turned on, a conductive channel is formed on the side of the active structure 310 near the gate 320, causing a large number of electrons to gather on the side of the active structure 310 near the gate 320. The light shielding structure 200 is electrically connected to the first source and drain region 312 of the active structure 310 through the source and drain electrodes 340. Therefore, when there is charge on the light shielding structure 200, the light shielding structure 200 forms a conductive channel on the side of the active structure 310 near the light shielding structure 200, causing a large number of electrons to gather on the side of the active structure 310 near the light shielding structure 200. Since a large number of electrons are gathered on both sides of the active structure 310, the mobility of carriers in the channel region 311 of the thin film transistor structure 300 is improved. Therefore, the light shielding structure 200 is electrically connected to the first source and drain region 312 of the active structure 310 through the source and drain electrodes 340, which can effectively improve the mobility of carriers in the channel region 311 of the thin film transistor structure 300, thereby improving the response speed of the thin film transistor 300.

[0119] 3. A buffer layer 800 and an initial active layer are sequentially fabricated on the side of the light-shielding structure 200 facing away from the substrate 100. The buffer layer 800 covers both the light-shielding structure 200 and the substrate 100. The initial active layer is patterned using photolithography and etching processes to form an active structure 310 and an oxide semiconductor thin film structure co-located with and separated from the active structure 310. The oxide semiconductor thin film structure is then conductively fabricated to form the first electrode structure 400. Fabricating the active structure 310 and the first electrode structure co-located on the same layer saves time and simplifies the process.

[0120] Those skilled in the art will appreciate that the steps, measures, and schemes in the various operations, methods, and processes discussed in this application may be interchanged, modified, combined, or deleted. Furthermore, other steps, measures, and schemes in the various operations, methods, and processes discussed in this application may also be interchanged, modified, rearranged, decomposed, combined, or deleted. Furthermore, steps, measures, and schemes in the related art that are similar to those disclosed in this application may also be interchanged, modified, rearranged, decomposed, combined, or deleted.

[0121] In the description of this application, the directions or positional relationships indicated by words such as "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", and "outside" are exemplary directions or positional relationships based on the accompanying drawings. They are intended to facilitate or simplify the description of the embodiments of this application, and do not indicate or imply that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they should not be understood as limitations on this application.

[0122] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of such features. Throughout this application, unless otherwise specified, "plurality" means two or more.

[0123] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to direct connections, indirect connections through an intermediate medium, or internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0124] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0125] It should be understood that, although the various steps in the flowchart of the accompanying drawings are displayed in sequence as indicated by the arrows, the order of implementation of these steps is not limited to the order indicated by the arrows. Unless otherwise clearly stated herein, in some implementation scenarios of the embodiments of the present application, the steps in each process can be performed in other orders as required. Moreover, some or all of the steps in each flowchart may include multiple sub-steps or multiple stages based on actual implementation scenarios. Some or all of these sub-steps or stages may be executed at the same time, or may be executed at different times in different scenarios at the execution time. The execution order of these sub-steps or stages may be flexibly configured as required, and the embodiments of the present application do not limit this.

[0126] The above is only part of the implementation methods of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the technical concept of the solution of the present application, other similar implementation methods based on the technical ideas of the present application also fall within the protection scope of the embodiments of the present application.

Claims

1. An array substrate, characterized in that: The device comprises at least one photosensitive sub-pixel, wherein the photosensitive sub-pixel comprises: substrate; a thin film transistor structure, disposed on one side of the substrate, the thin film transistor structure comprising an active structure, a gate, and a source and drain electrode, the gate being disposed on a side of the active structure away from the substrate, and the source and drain electrode being disposed on a side of the gate away from the active structure; a first electrode structure disposed on one side of the substrate; the first electrode structure and the active structure are in the same layer and separated from each other, and are electrically connected through the source and drain electrodes; a photoelectric device structure, disposed on a side of the first electrode structure away from the substrate; A light-shielding structure is provided between the thin film transistor structure and the substrate, and the light-shielding structure is electrically connected to the source and drain.

2. The array substrate according to claim 1, wherein: The oxide semiconductor material of the active structure is the same as the oxide semiconductor material of the first electrode structure, and the carrier mobility of the active structure is different from the carrier mobility of the first electrode structure.

3. The array substrate according to claim 2, wherein: Also includes: a first interlayer dielectric layer, covering the gate and the first electrode structure; The source and drain electrodes are arranged on a side of the first interlayer dielectric layer away from the active structure and the first electrode structure; The source and drain include a first source and drain; the first source and drain are electrically connected to the first source and drain region of the active structure through a first via hole in the first interlayer dielectric layer, and are electrically connected to the first electrode structure through a third via hole in the first interlayer dielectric layer.

4. The array substrate according to claim 2, wherein: The orthographic projection of the light-shielding structure on the substrate at least overlaps with the orthographic projection of the channel region of the active structure on the substrate; the light-shielding structure is electrically connected to the first source and drain region of the active structure through the source and drain electrodes.

5. The array substrate according to claim 4, wherein: The array substrate also includes: a buffer layer covering the shading structure and the base, and a first interlayer dielectric layer covering the gate and the first electrode structure; the first source and drain of the source and drain are electrically connected to the shading structure through the first interlayer dielectric layer and the second via hole of the buffer layer.

6. The array substrate according to claim 3 or 5, characterized in that: The first interlayer dielectric layer is provided with a through groove at a partial area covering the first electrode structure, and the optoelectronic device structure is arranged in the through groove of the first interlayer dielectric layer; Along a first direction, the size of the optoelectronic device structure is not larger than the size of the first interlayer dielectric layer. The first direction is a direction perpendicular to the substrate. The optoelectronic device structure is electrically connected to the first electrode structure.

7. The array substrate according to claim 6, wherein: Along the second direction, the size of the first electrode structure is larger than that of the active structure; the third direction is parallel to the substrate and points from the active structure to the first electrode structure; the second direction is parallel to the substrate and perpendicular to the third direction.

8. A detection device, characterized in that: The invention comprises an array substrate as described in any one of claims 1 to 7.

9. A method for manufacturing an array substrate according to any one of claims 1 to 7, characterized in that: include: On one side of the substrate, a light-shielding structure is manufactured; An active structure of a thin film transistor structure is fabricated on a side of the light-shielding structure away from the substrate, and an oxide semiconductor thin film structure is fabricated on a side of the substrate not covered by the light-shielding structure, the oxide semiconductor thin film structure being located in the same layer as the active structure and being separated from the active structure; and the oxide semiconductor thin film structure is conductively converted into a first electrode structure. Manufacturing a gate on a side of the active structure away from the light shielding structure; fabricating a photovoltaic device structure on a side of the first electrode structure away from the substrate; On a side of the active structure and the first electrode structure away from the substrate, a source and drain of a thin film transistor are manufactured, and the source and drain are electrically connected to the active structure, the first electrode structure, and the light shielding structure.

10. The manufacturing method according to claim 9, characterized in that: Before manufacturing a photoelectric device structure on a side of the first electrode structure away from the substrate, the method further comprises: manufacturing a buffer layer covering the light-shielding structure and the substrate; manufacturing a first interlayer dielectric layer covering the gate and the first electrode structure; A first via hole is formed in the first interlayer dielectric layer at a location covering the first source / drain region of the active structure, a third via hole is formed in an edge region covering the first electrode structure, a through groove is formed in a portion of the region covering the first electrode structure, and a second via hole is formed in an edge region of the first interlayer dielectric layer and the buffer layer covering the light shielding structure; Source and drain electrodes are prepared on the side of the first interlayer dielectric layer away from the substrate; the first source and drain electrodes are electrically connected to the first source and drain region through the first via hole, electrically connected to the shading structure through the second via hole, and electrically connected to the first electrode structure through the third via hole.

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