Metal oxide semiconductor field effect transistor layout structure

Abstract

The application provides a metal oxide semiconductor field effect transistor layout structure, comprising a first active region and a second active region arranged at intervals in a first direction; n gates located on the first active region and the second active region, all the gates are arranged in parallel with each other along a second direction, and each gate extends from the first active region to the second active region, wherein n is greater than or equal to 6. A first redundant gate is located on one side of the n gates; and a second redundant gate is located on the other side of the n gates and is arranged opposite to the first redundant gate. In this way, by reasonably arranging the active region, the gate and the redundant gate, compared with the prior art, the layout of the active region is more compact, so that the area of the layout occupied by the active region is reduced, and the number of the redundant gates is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a metal oxide semiconductor field effect transistor layout structure. BACKGROUND

[0002] With the continuous development of semiconductor technology, the improvement of integrated circuit performance is mainly realized by continuously reducing the size of integrated circuit devices to improve its speed. At present, since the semiconductor industry has progressed to the nanometer technology node in the pursuit of high device density, high performance and low cost, the preparation of semiconductor devices is limited by various physical limits.

[0003] At present, in the existing metal oxide semiconductor field effect transistor (MOSFET) layout structure, four independent active areas (AA) and three redundant gates are usually used, which leads to a larger layout area occupied by the active area. Therefore, in order to solve the above problems, it is necessary to propose a new metal oxide semiconductor field effect transistor layout structure. SUMMARY

[0004] The purpose of the present application is to provide a metal oxide semiconductor field effect transistor layout structure to reduce the layout area occupied by the active area.

[0005] To achieve the above purpose, the present application provides a metal oxide semiconductor field effect transistor layout structure, comprising:

[0006] A first layout area has a first active area for forming a first conductivity type transistor;

[0007] A second layout area has a second active area for forming a second conductivity type transistor, and the second active area is arranged apart from the first active area in a first direction;

[0008] n gates are located on the first active area and the second active area, all of the gates are arranged parallel to each other along the second direction, and each of the gates extends from the first active area to the second active area, wherein the first direction and the second direction are perpendicular to each other, n≥6; a first redundant gate is located on one side of the n gates;

[0009] A second redundant gate is located on the other side of the n gates and is arranged opposite to the first redundant gate;

[0010] The first redundant gate and the second redundant gate both extend from the first active area to the second active area, and the first redundant gate, the second redundant gate and the n gates are arranged parallel to each other.

[0011] Optionally, in the MOSFET layout structure, the first active region and the second active region are both rectangular.

[0012] Optionally, in the MOSFET layout structure, the first active region is rectangular, and the second active region is concave.

[0013] Optionally, in the MOSFET layout structure, the n gates include a first gate, a second gate, a third gate, a fourth gate, a fifth gate, and a sixth gate arranged in sequence along the second direction, the first redundant gate is located on a side of the first gate away from the second gate, and the second redundant gate is located on a side of the sixth gate away from the fifth gate.

[0014] Optionally, in the MOSFET layout structure, m active region connection layers are further included, the active region connection layers are located on the first active region or the second active region and cross the gates, and m≥3.

[0015] Optionally, in the MOSFET layout structure, the m active region connection layers include a first active region connection layer, a second active region connection layer, and a third active region connection layer, the first active region connection layer extends from a first active region between the first redundant gate and the first gate to a first active region between the sixth gate and the second redundant gate, the second active region connection layer extends from a second active region between the first redundant gate and the first gate to a second active region between the sixth gate and the second redundant gate, and the third active region connection layer extends from a second active region between the fourth gate and the fifth gate to the second active region between the fifth gate and the sixth gate.

[0016] Optionally, in the MOSFET layout structure, the first active region connection layer and the third active region connection layer are both rectangular, and the second active region connection layer is in the shape of a U.

[0017] Optionally, in the MOSFET layout structure, at least f active region contact holes are further included, each of the first active region connection layer, the second active region connection layer, and the third active region connection layer has at least one active region contact hole, f≥6, and.

[0018] Optionally, in the metal-oxide-semiconductor field effect transistor layout structure, the f active region contact holes include at least a first active region contact hole, a second active region contact hole, a third active region contact hole and a fourth active region contact hole in the first active region connection layer, and further include a fifth active region contact hole and a sixth active region contact hole in the second active region connection layer, and further include a seventh active region contact hole in the third active region connection layer.

[0019] Optionally, in the metal-oxide-semiconductor field effect transistor layout structure, the first active region contact hole is in the first active region connection layer between the first redundant gate and the first gate, the second active region contact hole is in the first active region connection layer between the second gate and the third gate, the third active region contact hole is in the first active region connection layer between the fourth gate and the fifth gate, the fourth active region contact hole is in the first active region connection layer between the sixth gate and the second redundant gate, the fifth active region contact hole is in the second active region connection layer between the first redundant gate and the first gate, the sixth active region contact hole is in the second active region connection layer between the sixth gate and the second redundant gate, and the seventh active region contact hole is in the second active region connection layer between the fifth gate and the sixth gate.

[0020] Optionally, in the metal-oxide-semiconductor field effect transistor layout structure, the metal-oxide-semiconductor field effect transistor layout structure further includes m gate connection layers on the gates between the first active region and the second active region.

[0021] Optionally, in the metal-oxide-semiconductor field effect transistor layout structure, the m gate connection layers include at least a first gate connection layer, a second gate connection layer and a third gate connection layer, the first gate connection layer is in the shape of an n-shaped, and the first gate connection layer extends from the first gate to the fourth gate, the second gate connection layer and the third gate connection layer are both in the shape of a rectangle, the second gate connection layer extends from the fifth gate to the sixth gate, the third gate connection layer extends from the second gate to the third gate, and the third gate connection layer is spaced apart from the first gate connection layer.

[0022] Optionally, in the metal-oxide-semiconductor field effect transistor layout structure, it further includes at least n gate contact holes in the first gate connection layer, the second gate connection layer and the third gate connection layer, respectively.

[0023] Optionally, in the layout structure of the metal-oxide-semiconductor field effect transistor, the n gate contact holes comprise at least a first gate contact hole and a fourth gate contact hole in the first gate connection layer, a fifth gate contact hole and a sixth gate contact hole in the second gate connection layer, and a second gate contact hole and a third gate contact hole in the third gate connection layer, wherein the first gate contact hole is aligned with the first gate, the second gate contact hole is aligned with the second gate, the third gate contact hole is aligned with the third gate, the fourth gate contact hole is aligned with the fourth gate, the fifth gate contact hole is aligned with the fifth gate, and the sixth gate contact hole is aligned with the sixth gate.

[0024] Optionally, in the layout structure of the metal-oxide-semiconductor field effect transistor, the first active region and the n gates constitute n first conductive type transistors, and the second active region and the n gates constitute n second conductive type transistors.

[0025] Optionally, in the layout structure of the metal-oxide-semiconductor field effect transistor, a well region with a first conductive type, a first source-drain implant region with the first conductive type, and a second source-drain implant region with a second conductive type are further included, the well region is located in the first layout region, the first source-drain implant region is located in the well region, the first active region is located in the first source-drain implant region, the second source-drain implant region is located in the second layout region, and the second active region is located in the second source-drain implant region.

[0026] Optionally, in the layout structure of the metal-oxide-semiconductor field effect transistor, the first conductive type is P type, and the second conductive type is N type.

[0027] Optionally, in the layout structure of the metal-oxide-semiconductor field effect transistor, a first gate cutoff layer and a second gate cutoff layer are further included, and the first gate cutoff layer and the second gate cutoff layer are respectively arranged at both ends of the gate.

[0028] In the metal oxide semiconductor field effect transistor layout structure provided by the present application, the first active region and the second active region are arranged at intervals in the first direction; n gates are arranged on the first active region and the second active region, all the gates are arranged in parallel along the second direction, and each gate extends from the first active region to the second active region, wherein n≥6. The first redundant gate is arranged on one side of the n gates; the second redundant gate is arranged on the other side of the n gates and is arranged opposite to the first redundant gate; the first redundant gate and the second redundant gate both extend from the first active region to the second active region, and the first redundant gate, the second redundant gate and the n gates are arranged in parallel. In this way, by reasonably arranging the active region, the gate and the redundant gate, only two active regions and two redundant gates are used in the layout structure, compared with the prior art, the layout of the active region is more compact, thereby reducing the area of the layout occupied by the active region and reducing the number of redundant gates. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 is a schematic diagram of the metal oxide semiconductor field effect transistor layout structure provided by the embodiment of the present application;

[0030] Figure 2 is a schematic diagram of another metal oxide semiconductor field effect transistor layout structure provided by the embodiment of the present application;

[0031] Figure 3 is a schematic diagram of the first active region of the metal oxide semiconductor field effect transistor layout structure provided by the embodiment of the present application;

[0032] Figure 4 is a schematic diagram of the first active region connection layer of the metal oxide semiconductor field effect transistor layout structure provided by the embodiment of the present application;

[0033] Figure 5 is a schematic diagram of the second active region connection layer of the metal oxide semiconductor field effect transistor layout structure provided by the embodiment of the present application;

[0034] Figure 6 is a schematic diagram of the third active region connection layer of the metal oxide semiconductor field effect transistor layout structure provided by the embodiment of the present application;

[0035] Figure 7 is a schematic diagram of the first gate connection layer of the metal oxide semiconductor field effect transistor layout structure provided by the embodiment of the present application;

[0036] Figure 8 is a schematic diagram of the second gate connection layer of the metal oxide semiconductor field effect transistor layout structure provided by the embodiment of the present application;

[0037] Figure 9is a schematic view of a third gate connecting layer of a metal oxide semiconductor field effect transistor layout structure provided by an embodiment of the present application;

[0038] Figure 10 is a circuit connection schematic view of a metal oxide semiconductor field effect transistor layout structure provided by an embodiment of the present application;

[0039] in the figure,

[0040] 101-first layout area; 102-second layout area;

[0041] 103-first active area; 104-second active area; 105-well area; 106-first source / drain implant area; 107-second source / drain implant area;

[0042] 110-gate; 111-first gate; 112-second gate; 113-third gate; 114-fourth gate; 115-fifth gate; 116-sixth gate; 117-first redundant gate; 118-second redundant gate;

[0043] 121-first active area connecting layer; 122-second active area connecting layer; 123-third active area connecting layer;

[0044] 131-first active area contact hole; 132-second active area contact hole; 133-third active area contact hole; 134-fourth active area contact hole; 135-fifth active area contact hole; 136-sixth active area contact hole; 137-seventh active area contact hole;

[0045] 141-first gate connecting layer; 142-second gate connecting layer; 143-third gate connecting layer;

[0046] 151-first gate contact hole; 152-second gate contact hole; 153-third gate contact hole; 154-fourth gate contact hole; 155-fifth gate contact hole; 156-sixth gate contact hole;

[0047] 161-first gate interruption layer; 162-second gate interruption layer. DETAILED DESCRIPTION

[0048] The metal oxide semiconductor field effect transistor layout structure proposed by the present application is further described in detail below in combination with the drawings and specific embodiments. The advantages and features of the present application will be clearer according to the following description. It should be noted that the drawings are all very simplified and all use non-precise proportions, only for the purpose of facilitating and clearly assisting the description of the embodiments of the present application.

[0049] Figure 1 is a schematic view of a metal oxide semiconductor field effect transistor layout structure provided by an embodiment of the present application;Figure 2 is a schematic view of another metal oxide semiconductor field effect transistor layout structure provided by an embodiment of the present application; Figure 3 is a schematic view of a first active area of a metal oxide semiconductor field effect transistor layout structure provided by an embodiment of the present application; Figure 4 is a schematic view of a first active area connection layer of a metal oxide semiconductor field effect transistor layout structure provided by an embodiment of the present application; Figure 5 is a schematic view of a second active area connection layer of a metal oxide semiconductor field effect transistor layout structure provided by an embodiment of the present application; Figure 6 is a schematic view of a third active area connection layer of a metal oxide semiconductor field effect transistor layout structure provided by an embodiment of the present application; Figure 7 is a schematic view of a first gate connection layer of a metal oxide semiconductor field effect transistor layout structure provided by an embodiment of the present application; Figure 8 is a schematic view of a second gate connection layer of a metal oxide semiconductor field effect transistor layout structure provided by an embodiment of the present application; Figure 9 is a schematic view of a third gate connection layer of a metal oxide semiconductor field effect transistor layout structure provided by an embodiment of the present application; Figure 10 is a schematic view of a circuit connection of a metal oxide semiconductor field effect transistor layout structure provided by an embodiment of the present application.

[0050] As shown in Figure 1 and Figure 2 , the embodiment provides a metal oxide semiconductor field effect transistor layout structure, comprising: a first layout area 101 having a first active area 103 for forming a first conductive type transistor; a second layout area 102 having a second active area 104 for forming a second conductive type transistor, the second active area 104 being arranged apart from the first active area 103 in a first direction; n gates located on the first active area 103 and the second active area 104, all of the gates being arranged parallel to each other along a second direction, and each of the gates extending from the first active area 103 to the second active area 104, wherein the first direction and the second direction are perpendicular to each other, and n≥6; a first redundant gate 117 located on one side of the n gates; a second redundant gate 118 located on the other side of the n gates and arranged opposite to the first redundant gate 117; the first redundant gate 117 and the second redundant gate 118 both extending from the first active area 103 to the second active area 104, and the first redundant gate 117, the second redundant gate 118 and the n gates being arranged parallel to each other. In this way, by reasonably arranging the active areas, the gates and the redundant gates, compared with the prior art, only two active areas and two redundant gates are used in the layout structure, which can make the layout of the active areas more compact, thereby reducing the area of the layout occupied by the active areas and reducing the number of the redundant gates.

[0051] In addition, as shown in Figure 1 and Figure 2 , the structure further comprises a well region 105 of the first conductivity type, a first source-drain implant region 106 of the first conductivity type and a second source-drain implant region 107 of the second conductivity type, the well region 105 is located in the first layout region 101, the first source-drain implant region 106 is located in the well region 105, the first active region 103 is located in the first source-drain implant region 106, the second source-drain implant region 107 is located in the second layout region 102, and the second active region 104 is located in the second source-drain implant region 107. The first source-drain implant region 106 can be a boron implant region, and the second source-drain implant region 107 can be a phosphorus implant region.

[0052] In one embodiment, as shown in Figure 1 , the shapes of the first active region 103 and the second active region 104 are both rectangular. In another embodiment, as shown in Figure 2 and Figure 3 , the shape of the first active region 103 is rectangular, and the shape of the second active region 104 is a concave shape. That is, the second active region 104 has a convex region and a concave region, and the width ratio of the convex region and the concave region satisfies the following relationship:

[0053] 1.24:1≤W1:W2≤1.32:1, where W1 represents the width of the convex region, and W2 represents the width of the concave region. In this way, the current capacity of the transistor formed by the first active region 103 and the transistor formed by the second active region 104 can be enhanced, for example, the drain saturation current can be increased.

[0054] In this embodiment, the n gates at least include a first gate 111, a second gate 112, a third gate 113, a fourth gate 114, a fifth gate 115 and a sixth gate 116 arranged in sequence along the second direction, the first redundant gate 117 is located on the side of the first gate 111 away from the second gate 112, and the second redundant gate 118 is located on the side of the sixth gate 116 away from the fifth gate 115.

[0055] In this embodiment, as shown in 1 and Figure 2 , the structure further comprises m active region connection layers, the active region connection layers are located on the first active region 103 or the second active region 104 and cross the gates, and m≥3. The active region connection layers are used to connect the active regions between the gates.

[0056] Specifically, the m active region connection layers include at least a first active region connection layer 121, a second active region connection layer 122, and a third active region connection layer 123. The first active region connection layer 121 extends from the first active region 103 between the first redundant gate 117 and the first gate 111 to the first active region 103 between the sixth gate 116 and the second redundant gate 118. The second active region 104 extends from the second active region 104 between the first redundant gate 117 and the first gate 111 to the second active region 104 between the sixth gate 116 and the second redundant gate 118. The third active region connection layer 123 extends from the second active region 104 between the fourth gate 114 and the fifth gate 115 to the second active region 104 between the fifth gate 115 and the sixth gate 116.

[0057] Furthermore, both the first active region connection layer 121 and the third active region connection layer 123 are rectangular in shape. Figure 4 As shown, the side length ratio L1:H1 of the first active region connection layer 121 satisfies the following relationship:

[0058] 1.22:1≤L1:H1≤1.30:1;

[0059] like Figure 6 As shown, the side length ratio L3:H3 of the third active region connection layer 123 satisfies the following relationship:

[0060] 0.14:1≤L3:H3≤0.24:1.

[0061] In this embodiment, the second active area connection layer 122 has a U-shaped shape, that is, the second active area connection layer 122 includes two vertical segments and two horizontal segments, which are arranged perpendicularly to each other. Figure 5 As shown, the side length ratio L2:H2 of the second active region connection layer 122 satisfies the following relationship:

[0062] 6.03:1≤L2:H2≤6.07:1, and H1:H2 is 1:3. This setting helps to reduce the layout area occupied by the active region connection layer.

[0063] In this embodiment, as Figure 1 and Figure 2 As shown, the layout also includes at least f active region contact holes, each of the first active region connection layer 121, the second active region connection layer 122 and the third active region connection layer 123 having at least one of the active region contact holes, wherein f ≥ 6.

[0064] Specifically, such as Figure 1 and Figure 2As shown, the f active region contact holes include at least a first active region contact hole 131, a second active region contact hole 132, a third active region contact hole 133, and a fourth active region contact hole 134 located in the first active region connection layer 121, and further include a fifth active region contact hole 135 and a sixth active region contact hole 136 located in the second active region connection layer 122, and further include a seventh active region contact hole 137 located in the third active region connection layer 123. Through the active region contact hole, an external signal can be introduced to the first active region 103 or the second active region 104 to realize the introduction of an external signal to the source region and / or the drain region of the first conductive type transistor or the second conductive type transistor.

[0065] Further, the first active region contact hole 131 is located in the first active region connection layer 121 between the first redundant gate 117 and the first gate 111, the second active region contact hole 132 is located in the first active region connection layer 121 between the second gate 112 and the third gate 113, the third active region contact hole 133 is located in the first active region connection layer 121 between the fourth gate 114 and the fifth gate 115, the fourth active region contact hole 134 is located in the first active region connection layer 121 between the sixth gate 116 and the second redundant gate 118, the fifth active region contact hole 135 is located in the second active region connection layer 122 between the first redundant gate 117 and the first gate 111, the sixth active region contact hole 136 is located in the second active region connection layer 122 between the sixth gate 116 and the second redundant gate 118, and the seventh active region contact hole 137 is located in the second active region connection layer 122 between the fifth gate 115 and the sixth gate 116.

[0066] In this embodiment, as shown in Figure 1 and Figure 2 As shown, the metal oxide semiconductor field effect tube layout structure further includes m gate connection layers located on the gates between the first active region 103 and the second active region 104.

[0067] Specifically, the m gate connection layers include at least a first gate connection layer 141, a second gate connection layer 142, and a third gate connection layer 143, the shape of the first gate connection layer 141 is n-shaped, and the first gate connection layer 141 extends from the first gate 111 to the fourth gate 114.

[0068] The second gate connecting layer 142 and the third gate connecting layer 143 are both rectangular in shape, the second gate connecting layer 142 extends from the fifth gate 115 to the sixth gate 116, and the third gate connecting layer 143 extends from the second gate 112 to the third gate 113, and the third gate connecting layer 143 is spaced apart from the first gate connecting layer 141.

[0069] Further, as shown in FIG. 1, the length-width ratio L4:H4 of the first gate connecting layer 141 satisfies the following relationship: Figure 7

[0070] 3.24:1≤L4:H4≤3.31:1;

[0071] As shown in FIG. 1, the length-width ratio L5:H5 of the second gate connecting layer 142 satisfies the following relationship: Figure 8 4.16:1≤L5:H5≤4.24:1, and H4:H5 is 1:3.

[0072]

[0073] As shown in FIG. 1, the length-width ratio L6:H6 of the third gate connecting layer 143 satisfies the following relationship: Figure 9 2.96:1≤L6:H6≤3.04:1, and H6:H5 is 1:3. In this way, the layout area occupied by the gate connecting layer can be reduced.

[0074] As shown in FIG. 1, and FIG. 2, at least n gate contact holes are further included, and the n gate contact holes are respectively located in the first gate connecting layer 141, the second gate connecting layer 142, and the third gate connecting layer 143. The n gate contact holes are used to introduce a gate signal to each gate.

[0075] Figure 1 Figure 2

[0076] ​​​​​In this embodiment, the n gate contact holes include at least a first gate contact hole 151 and a fourth gate contact hole 154 located in the first gate connection layer 141, a fifth gate contact hole 155 and a sixth gate contact hole 156 located in the second gate connection layer 142, and a second gate contact hole and a third gate contact hole 153 located in the third gate connection layer 143. Specifically, the first gate contact hole 151 is aligned with the first gate 111 and electrically connected to the first gate 111 to introduce an external gate signal to the first gate 111. The second gate contact hole 151 is aligned with the second gate, and the second gate contact hole 152 is electrically connected to the second gate 112 to introduce an external gate signal to the second gate 112. The third gate contact hole 153 is aligned with the third gate 113 and electrically connected to the third gate 113 to introduce an external gate signal to the third gate 113. The fourth gate contact hole 154 is aligned with the fourth gate 114 and electrically connected to the fourth gate 114 to introduce an external gate signal to the fourth gate 114. The fifth gate contact hole 155 is aligned with the fifth gate 115 and electrically connected to the fifth gate 115 to introduce an external gate signal to the second gate 112. The sixth gate contact hole 156 is aligned with the sixth gate 116 and electrically connected to the sixth gate 116 to introduce an external gate signal to the sixth gate 116.

[0077] In this embodiment, the first active region 103, the n gates, and the m gate connection layers constitute n transistors of the first conductivity type; the second active region 104, the n gates, and the m gate connection layers constitute n transistors of the second conductivity type.

[0078] Furthermore, the first conductivity type can be P-type, and the second conductivity type can be N-type. The transistor with the first conductivity type is, for example, a PMOS transistor, and the transistor with the second conductivity type is, for example, an NMOS transistor.

[0079] like Figure 10 As shown, in this embodiment, the first conductivity type transistor includes at least a first PMOS transistor PW1, a second PMOS transistor PW2, a third PMOS transistor PW3, a fourth PMOS transistor PW4, a fifth PMOS transistor PW5, and a sixth PMOS transistor PW6.

[0080] The first PMOS transistor PW1 is composed of the first active region 103, the first gate 111 and the first gate connecting layer 141, and the gate signal A is input to the first gate 111 through the first gate contact hole 151 and the first gate connecting layer 141.

[0081] The second PMOS transistor PW2 is composed of the first active region 103, the second gate 112 and the second gate connecting layer 142, and the gate signal B is input to the second gate 112 through the second gate contact hole and the second gate connecting layer 142. The source of the second PMOS transistor and the drain of the first PMOS transistor share the first active region 103.

[0082] The third PMOS transistor PW3 is composed of the first active region 103, the third gate 113 and the second gate connecting layer 142, and the gate signal B is input to the third gate 113 through the third gate contact hole and the second gate connecting layer 142. The source of the third PMOS transistor and the drain of the second PMOS transistor share the first active region 103.

[0083] The fourth PMOS transistor PW4 is composed of the first active region 103, the fourth gate 114 and the first gate connecting layer 141, and the gate signal A is input to the fourth gate 114 through the fourth gate contact hole and the first gate connecting layer 141. The source of the fourth PMOS transistor and the drain of the third PMOS transistor share the first active region 103.

[0084] The fifth PMOS transistor PW5 is composed of the first active region 103, the fifth gate 115 and the third gate connecting layer 143, and the gate signal C is input to the fifth gate 115 through the third gate contact hole and the third gate connecting layer 143. The source of the fifth PMOS transistor and the drain of the fourth PMOS transistor share the first active region 103.

[0085] The sixth PMOS transistor PW6 is composed of the first active region 103, the sixth gate 116 and the third gate connecting layer 143, and the gate signal C is input to the sixth gate 116 through the sixth gate contact hole and the third gate connecting layer 143. The source of the sixth PMOS transistor and the drain of the fifth PMOS transistor share the first active region 103. The drain of the sixth PMOS transistor, the source of the first PMOS transistor, the source of the third PMOS transistor and the source of the fifth PMOS transistor are electrically connected through the first active region connecting layer 121.

[0086] As Figure 10As shown, in this embodiment, the second conductivity type transistors at least include a first NMOS transistor NW1, a second NMOS transistor NW2, a third NMOS transistor NW3, a fourth NMOS transistor NW4, a fifth NMOS transistor NW5, and a sixth NMOS transistor NW6.

[0087] The first NMOS transistor NW1 is composed of the second active region 104, the first gate 111, and the first gate connecting layer 141, and the gate signal A is input to the first gate 111 through the first gate contact hole 151 and the first gate connecting layer 141.

[0088] The second NMOS transistor NW2 is composed of the second active region 104, the second gate 112, and the second gate connecting layer 142, and the gate signal B is input to the second gate 112 through the second gate contact hole and the second gate connecting layer 142. The source of the second NMOS transistor and the drain of the first NMOS transistor share the second active region 104.

[0089] The third NMOS transistor NW3 is composed of the second active region 104, the third gate 113, and the second gate connecting layer 142, and the gate signal B is input to the third gate 113 through the third gate contact hole and the second gate connecting layer 142. The source of the third NMOS transistor and the drain of the second NMOS transistor share the second active region 104.

[0090] The fourth NMOS transistor NW4 is composed of the second active region 104, the fourth gate 114, and the first gate connecting layer 141, and the gate signal A is input to the fourth gate 114 through the fourth gate contact hole and the first gate connecting layer 141. The source of the fourth NMOS transistor and the drain of the third NMOS transistor share the second active region 104.

[0091] The fifth NMOS transistor NW5 is composed of the second active region 104, the fifth gate 115, and the third gate connecting layer 143, and the gate signal C is input to the fifth gate 115 through the third gate contact hole and the third gate connecting layer 143. The source of the fifth NMOS transistor and the drain of the fourth NMOS transistor share the second active region 104.

[0092] The sixth NMOS transistor NW6 is composed of the second active region 104, the sixth gate 116, and the third gate connecting layer 143, and the gate signal C is input to the sixth gate 116 through the sixth gate contact hole and the third gate connecting layer 143. The source of the sixth NMOS transistor and the drain of the fifth NMOS transistor share the second active region 104. The drain of the sixth NMOS transistor and the source of the first NMOS transistor are electrically connected through the second active region connecting layer 122.

[0093] In the embodiment, the layout structure further comprises a first gate cut layer 161 and a second gate cut layer 162, the first gate cut layer 161 extends at least from the end of the first redundant gate 117 of the first layout area 101 to the end of the second redundant gate 118, and the second gate cut layer 162 extends at least from the end of the first redundant gate 117 of the second layout area 102 to the end of the second redundant gate 118. The middle line L of the first gate cut layer 161 is aligned with the boundary line of the end of the first redundant gate 117, the first gate 111 to the sixth gate 116 of the first layout area 101, and the middle line L of the second gate cut layer 162 is aligned with the boundary line of the end of the first redundant gate 117, the first gate 111 to the sixth gate 116 of the second layout area 102. The signals of all the gates can be cut off through the first gate cut layer 161 and the second gate cut layer 162, so as to introduce different signals to different parts of the gate.

[0094] As can be seen from the above, in the layout structure of the metal oxide semiconductor field effect tube provided by the application, the layout structure comprises a first active area and a second active area arranged at intervals in a first direction; n gates located on the first active area and the second active area, all the gates are arranged in parallel along the second direction, and each gate extends from the first active area to the second active area, wherein n≥6 first redundant gates are located on the first active area on one side of the gate; the first redundant gate located on the first active area on one side of the gate, and the second redundant gate located on the first active area on the other side of the gate. In this way, by reasonably arranging the active area, the gate and the redundant gate, only two active areas and two redundant gates are used in the layout structure, compared with the prior art, the layout of the active area is more compact, thereby reducing the area of the layout occupied by the active area and reducing the number of redundant gates.

[0095] The above description is only a description of the preferred embodiments of the application, and does not limit the scope of the application in any way. Any modification or change made by a person skilled in the art according to the above disclosure is within the protection scope of the claims.

Claims

1. A metal-oxide-semiconductor field-effect transistor layout structure, characterized in that, include: Two active regions, namely a first active region and a second active region; The first layout area has the first active region for forming a transistor of the first conductivity type; The second pattern area has a second active region for forming a transistor of a second conductivity type. The second active region is spaced apart from the first active region in a first direction. The shape of the second active region is U-shaped. The second active region has a raised region and a recessed region. The width ratio of the raised region and the recessed region satisfies the following relationship: 1.24:1≤W1:W2≤1.32:1, where W1 represents the width of the raised region and W2 represents the width of the recessed region. n gates are located on the first active region and the second active region. All the gates are arranged parallel to each other along the second direction, and each gate extends from the first active region to the second active region. The first direction and the second direction are perpendicular to each other, and n≥6. Two redundant gates, namely a first redundant gate and a second redundant gate, wherein the first redundant gate is located on one side of the n gates and the second redundant gate is located on the other side of the n gates and is disposed opposite to the first redundant gate; Both the first redundant gate and the second redundant gate extend from the first active region to the second active region, and the first redundant gate, the second redundant gate, and the n gates are arranged in parallel to each other.

2. The metal-oxide-semiconductor field-effect transistor layout structure as described in claim 1, characterized in that, The first active region is rectangular in shape.

3. The metal-oxide-semiconductor field-effect transistor layout structure as described in claim 1, characterized in that, The n gates include at least a first gate, a second gate, a third gate, a fourth gate, a fifth gate, and a sixth gate arranged sequentially along the second direction. The first redundant gate is located on the side of the first gate away from the second gate, and the second redundant gate is located on the side of the sixth gate away from the fifth gate.

4. The metal-oxide-semiconductor field-effect transistor layout structure as described in claim 3, characterized in that, It also includes m active region connection layers, which are located on the first active region or the second active region and span the gate, wherein m≥3.

5. The metal-oxide-semiconductor field-effect transistor layout structure as described in claim 4, characterized in that, The m active region connection layers include at least a first active region connection layer, a second active region connection layer, and a third active region connection layer. The first active region connection layer extends from the first active region between the first redundant gate and the first gate to the first active region between the sixth gate and the second redundant gate. The second active region connection layer extends from the second active region between the first redundant gate and the first gate to the second active region between the sixth gate and the second redundant gate. The third active region connection layer extends from the second active region between the fourth gate and the fifth gate to the second active region between the fifth gate and the sixth gate.

6. The metal-oxide-semiconductor field-effect transistor layout structure as described in claim 5, characterized in that, The first active region connection layer and the third active region connection layer are both rectangular in shape, while the second active region connection layer is shaped like a zigzag.

7. The metal-oxide-semiconductor field-effect transistor layout structure as described in claim 5, characterized in that, It also includes at least f active region contact holes, each of the first active region connection layer, the second active region connection layer and the third active region connection layer having at least one of the active region contact holes, wherein f≥6.

8. The metal-oxide-semiconductor field-effect transistor layout structure as described in claim 7, characterized in that, The f active region contact holes include at least a first active region contact hole, a second active region contact hole, a third active region contact hole, and a fourth active region contact hole located in the first active region connection layer, as well as a fifth active region contact hole and a sixth active region contact hole located in the second active region connection layer, and a seventh active region contact hole located in the third active region connection layer.

9. The metal-oxide-semiconductor field-effect transistor layout structure as described in claim 8, characterized in that, The first active region contact hole is located in the first active region connection layer between the first redundant gate and the first gate; the second active region contact hole is located in the first active region connection layer between the second gate and the third gate; the third active region contact hole is located in the first active region connection layer between the fourth gate and the fifth gate; the fourth active region contact hole is located in the first active region connection layer between the sixth gate and the second redundant gate; the fifth active region contact hole is located in the second active region connection layer between the first redundant gate and the first gate; the sixth active region contact hole is located in the second active region connection layer between the sixth gate and the second redundant gate; and the seventh active region contact hole is located in the second active region connection layer between the fifth gate and the sixth gate.

10. The metal-oxide-semiconductor field-effect transistor layout structure as described in claim 3, characterized in that, The metal-oxide-semiconductor field-effect transistor layout structure further includes m gate connection layers, which are located on the gate between the first active region and the second active region.

11. The metal-oxide-semiconductor field-effect transistor layout structure as described in claim 10, characterized in that, The m gate connection layers include at least a first gate connection layer, a second gate connection layer, and a third gate connection layer. The first gate connection layer is n-shaped and extends from the first gate to the fourth gate. The second gate connection layer and the third gate connection layer are both rectangular. The second gate connection layer extends from the fifth gate to the sixth gate, and the third gate connection layer extends from the second gate to the third gate. The third gate connection layer is spaced apart from the first gate connection layer.

12. The metal-oxide-semiconductor field-effect transistor layout structure as described in claim 11, characterized in that, It also includes at least n gate contact holes, which are respectively located in the first gate connection layer, the second gate connection layer and the third gate connection layer.

13. The metal-oxide-semiconductor field-effect transistor layout structure as described in claim 12, characterized in that, The n gate contact holes include at least a first gate contact hole and a fourth gate contact hole located in the first gate connection layer, a second gate contact hole and a third gate contact hole located in the second gate connection layer, and a fifth gate contact hole and a sixth gate contact hole located in the third gate connection layer, wherein the first gate contact hole is aligned with the first gate, the second gate contact hole is aligned with the second gate, the third gate contact hole is aligned with the third gate, the fourth gate contact hole is aligned with the fourth gate, the fifth gate contact hole is aligned with the fifth gate, and the sixth gate contact hole is aligned with the sixth gate.

14. The metal-oxide-semiconductor field-effect transistor layout structure as described in claim 10, characterized in that, The first active region, the n gates, and the m gate connection layers constitute n transistors of the first conductivity type; The second active region, the n gates, and the m gate connection layers constitute n transistors of the second conductivity type.

15. The metal-oxide-semiconductor field-effect transistor layout structure as described in claim 1, characterized in that, It also includes a well region having a first conductivity type, a first source / drain injection region having a first conductivity type, and a second source / drain injection region having a second conductivity type. The well region is located in the first layout area, the first source / drain injection region is located in the well region, the first active region is located in the first source / drain injection region, the second source / drain injection region is located in the second layout area, and the second active region is located in the second source / drain injection region.

16. The metal-oxide-semiconductor field-effect transistor layout structure as described in claim 15, characterized in that, The first conductivity type is P-type, and the second conductivity type is N-type.

17. The metal-oxide-semiconductor field-effect transistor layout structure as described in claim 1, characterized in that, It also includes a first gate cutoff layer and a second gate cutoff layer located on the n gates, wherein the first gate cutoff layer extends at least from the first redundant gate in the first layout area to the second redundant gate, and the second gate cutoff layer extends at least from the first redundant gate in the second layout area to the second redundant gate.

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