Time synchronization system, learning device, reasoning device and time synchronization device

Abstract

The model learning unit (401) performs a learning process for estimating the time of the base host based on the time synchronization information of the sub-base host. The inference unit (402) estimates the time of the base host based on the time synchronization information of the sub-base host using the learned model obtained by the learning process. The synchronization control unit (204) performs time synchronization according to the acquired time when the time is obtained from the base host, and performs time synchronization according to the time estimated by the inference unit (402) when the time is not obtained from the base host.

Description

Technical Field

[0001] The invention relates to a time synchronization system, a learning device, a reasoning device and a time synchronization device. Background Art

[0002] In a network where multiple devices are connected, in order to achieve high-precision synchronization control and distributed control between devices, high-precision time synchronization between devices is required. As a representative method for achieving time synchronization between devices connected to a network, PTP (Precision Time Protocol) specified in IEEE Std 1588-2008 is known (see Non-Patent Document 1).

[0003] In PTP, a master device that publishes a time and a slave device that is subordinate to the published time are defined. In addition, the delay time from when the time synchronization packet published from the master device reaches the slave device is measured, and the slave device is synchronized with the master device in consideration of the delay time. In this way, time synchronization is achieved while suppressing the influence of the delay caused by the physical distance between the master device and the slave device and the relay device (switches, etc.).

[0004] In PTP, there can be only one main master device (hereinafter sometimes referred to as "base host") that serves as a time reference for one domain, but multiple domains are allowed to exist in one network. Thus, multiple masters can be provided for one network.

[0005] When a fault occurs in the transmission path (line or relay device, etc.) of the master device or the network and the time synchronization packet cannot be exchanged between the master device and the slave device, the synchronization accuracy of the time deteriorates. In PTP, when a fault occurs and the slave device cannot receive the time synchronization packet from the master device, a step of selecting a replacement master device from the slave devices connected to the network is implemented. Specifically, after a certain period of time has passed since the exchange of the slave packets was interrupted, the network structure is detected again, and the master device is selected from the slave devices connected to the network according to the prescribed steps. Then, each other slave device synchronizes with the selected master device.

[0006] In this method, it may take several seconds from the occurrence of a failure to synchronization with the replacement master device. During the period before synchronization with the replacement master device, each slave device operates using its own local time, so the synchronization accuracy deteriorates.

[0007] Therefore, there is a known method of operating multiple master devices simultaneously in one network, and switching to a backup master device when a master device or a transmission path fails, thereby suppressing the degradation of synchronization accuracy. For example, Japanese Patent No. 5495323 discloses a method of calculating the congestion of a line corresponding to each master device in advance, and selecting a base host from multiple master devices according to a priority given according to the congestion (see Patent Document 1).

[0008] Prior art literature

[0009] Patent Literature

[0010] Patent Document 1: Japanese Patent No. 5495323

[0011] Non-patent literature

[0012] Non-patent document 1: IEEE Std 1588-2008 (Revision of IEEE Std 1588-2002) "IEEEStandard for a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems", IEEE Instrumentation and Measurement Society, July 24, 2008 Summary of the invention

[0013] Problems to be solved by the invention

[0014] As described above, a plurality of master devices are operated simultaneously, and when a master device or a transmission path fails, the backup master device is switched to continue synchronization with the master device.

[0015] However, if a plurality of master devices are not synchronized with each other with high precision, when a slave device switches the master device, an error between the master devices is reflected in the slave device, resulting in the possibility that synchronization precision may be degraded.

[0016] In order to ensure high-precision synchronization between master devices, it is also conceivable to connect multiple master devices directly to each other or to connect them to a common high-precision time source. However, in the former case, it is preferable to physically separate multiple master devices from the perspective of redundancy, so it is sometimes difficult to connect multiple master devices to each other. In the latter case, it is sometimes difficult to connect to a common high-precision time source depending on the location of the master device.

[0017] The present invention has been made to solve such a problem, and an object of the present invention is to suppress degradation of synchronization accuracy associated with switching of a master device in a time synchronization system in which a plurality of master devices exist in a network.

[0018] Means for solving problems

[0019] The time synchronization system of the present invention comprises a first master device and a second master device, a slave device, a learning unit, and an inference unit. The first master device and the second master device publish the time through a network. The learning unit uses learning data including the time synchronization information of the first master device (sub-base host) and the time of the second master device (base host) to perform a learning process for estimating the time of the second master device based on the time synchronization information of the first master device. The inference unit uses a learned model obtained through the learning process to estimate the time of the second master device based on the time synchronization information of the first master device. When the slave device obtains the time from the second master device, it synchronizes the time according to the obtained time, and when it does not obtain the time from the second master device, it synchronizes the time according to the time estimated by the inference unit.

[0020] Effects of the Invention

[0021] According to the time synchronization system of the present invention, when the master device is switched from the second master device (root master) to the first master device (sub-root master), it is possible to suppress the degradation of synchronization accuracy associated with the switching. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 This is a diagram showing the overall configuration of a time synchronization system according to Embodiment 1 of the present invention.

[0023] Figure 2 This is a diagram showing an example of the hardware configuration of each device constituting the time synchronization system.

[0024] Figure 3 This is a diagram showing an example of the functional configuration of each device constituting the time synchronization system.

[0025] Figure 4 It is a diagram showing an example of the configuration of a clock control unit.

[0026] Figure 5 It is a diagram showing an example of the configuration of the synchronization time inference unit.

[0027] Figure 6 This is a diagram showing an example of the configuration of a model learning unit.

[0028] Figure 7 This is a diagram showing an example of a neural network model.

[0029] Figure 8This is a flowchart showing an example of the procedure of the process executed by the model learning unit of the synchronization time inference unit.

[0030] Fig. 9 This is a diagram showing an example of the configuration of the inference unit.

[0031] Fig.10 This is a flowchart showing an example of the procedure of the process executed by the inference unit of the synchronization time inference unit.

[0032] Fig.11 This is a flowchart showing an example of a processing procedure of the time synchronization control executed by the synchronization control unit.

[0033] Fig.12 It is a diagram showing an example of the configuration of the synchronization time inference unit.

[0034] Fig.13 It is a diagram for explaining the reliability calculation unit.

[0035] Fig.14 This is a diagram showing an example of the configuration of a model learning unit.

[0036] Fig.15 This is a diagram showing an example of the configuration of the inference unit. DETAILED DESCRIPTION

[0037] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In addition, in the drawings, the same or corresponding parts are denoted by the same reference numerals and their description is omitted.

[0038] Implementation Method 1

[0039] Reference Figure 1 The overall structure of the time synchronization system according to Embodiment 1 of the present invention is described. The time synchronization system 10 includes master devices 101 and 103, a plurality of slave devices 102, and a plurality of switch devices 104. The master devices 101 and 103, the plurality of slave devices 102, and the plurality of switch devices 104 form a network and are configured to be able to communicate with other devices through the network.

[0040] The master devices 101 and 103 issue the time that becomes the reference in the time synchronization system 10. The master device 101 is a master device selected as the best master device by the BMC (Best Master Clock) algorithm specified in IEEE Std 1588-2008 (the above-mentioned non-patent document 1) among the multiple master devices 101 and 103, and acts as the "base master" of the network. On the other hand, the master device 103 is a master device that is not selected as the best master device by the BMC algorithm, and is sometimes referred to as a "sub-base master" below.

[0041] The master device 103 operates as a slave device synchronized with the master device 101 (base host) and also publishes the time as a master device. In this way, as a method for making multiple master devices 101 and 103 operate simultaneously in one network, for example, the method of replacing the master specified in IEEE Std 1588-2008 can be adopted. In this method, the alternateMasterFlag (flag) included in the time synchronization packet can be used to make the master device (sub-base host) that is not selected as the base host by the BMC algorithm operate as a master device without affecting the relationship between the base host and the slave device.

[0042] Alternatively, the following method may be adopted: a domain (referred to as "domain 1") in which the master device 101 is set as the time reference and a domain (referred to as "domain 2") in which the master device 103 is set as the time reference are formed, and the domains are multiplexed. Each device connected to the network synchronizes with the master device 101 in domain 1 and synchronizes with the master device 103 in domain 2. This method can also make the master device 103 (sub-base host) that is not selected as the base host by the BMC algorithm operate like a master device in domain 2 without affecting the time synchronization in domain 1.

[0043] By using the above-described method, the master device 103 (sub-base master) operating as a slave device using the BMC algorithm can also issue a time, and a plurality of master devices 101 and 103 can be operated simultaneously in one network.

[0044] In addition, Figure 1 In the figure, two master devices 101 and 103 are shown, but the time synchronization system 10 may have three or more master devices. That is, there is one master device 101 of the base host, but there may be multiple master devices 103 of the sub-base hosts.

[0045] Each slave device 102 sends and receives packets for time synchronization (hereinafter referred to as "time synchronization packets") with the master device 101 (base host) through the network, thereby synchronizing with the time of the master device 101. Specifically, according to the PTP of IEEE Std1588-2008, in each slave device 102, the delay time from the time synchronization packet issued from the master device 101 to the arrival of the slave device 102 is measured, and the time of the slave device 102 and the master device 101 are synchronized in consideration of the delay time.

[0046] Furthermore, each slave device 102 also sends and receives time synchronization packets with the master device 103 (sub-base master) via the network, and also obtains time synchronization information (described later) related to the master device 103 .

[0047] Each switch device 104 is a relay device installed in the transmission line. The time synchronization packet issued from the master device 101, 103 is delayed in the transmission line and the switch device 104 before reaching each slave device 102. In addition, each switch device 104 itself also sends and receives the time synchronization packet with the master device 101 (base host) through the network, thereby synchronizing with the time of the master device 101. In addition, each switch device 104 also sends and receives the time synchronization packet with the master device 103 (sub-base host) through the network, and obtains the time synchronization information related to the master device 103.

[0048] In addition, Figure 1 2 slave devices 102 and 3 switch devices 104 are shown in the figure, but the number of slave devices 102 and switch devices 104 is not limited thereto.

[0049] Thus, the time synchronization system 10 includes a plurality of master devices 101 and 103. Thus, when a failure occurs in the master device 101 (base host) or a transmission path to the master device 101, the time synchronization destination can be switched from the master device 101 to the master device 103.

[0050] In this case, when the master devices 101 and 103 are not synchronized with each other with high precision, the following problem occurs: that is, when each slave device 102 and each switch device 104 (hereinafter sometimes collectively referred to as "slave device, etc.") switches the time synchronization from the master device 101 to the master device 103, the error between the master devices 101 and 103 is reflected in the slave devices, etc., and as a result, the synchronization precision may be deteriorated.

[0051] In order to ensure high-precision synchronization between the master devices 101 and 103, it is also conceivable to connect the master devices 101 and 103 directly or to connect them to a common high-precision time source. However, with regard to the former, from the perspective of redundancy, it is preferable that the master devices 101 and 103 are physically separated, so it may be difficult to directly connect the master devices 101 and 103. With regard to the latter, depending on the installation location of the master devices 101 and 103, it may be difficult to connect them to a common high-precision time source.

[0052] In addition, in the normal operation of the master device 101 (base host), the master device 103 (sub-base host) synchronizes with the master device 101 as a slave of the master device 101. However, the synchronization accuracy between the master device 103, which is a substitute host of the master device 101, and the master device 101 (synchronization accuracy between hosts) is required to be higher than the synchronization accuracy between the master and the slave. That is, the synchronization accuracy between the master and the slave varies depending on the connection relationship and load conditions of the nodes. Even if the synchronization accuracy between the master device 103 and the master device 101 is within the allowable range when the master device 103 operates as a slave, the synchronization accuracy between the master device 103 and the master device 101 may not be allowed when the master device 103 operates as a master.

[0053] Therefore, in the time synchronization system 10 of the present embodiment 1, a learning process is performed to estimate the time of the master device 101 (base host) based on the time synchronization information of the master device 103 (sub-base host). Then, the time of the master device 101 (base host) is estimated based on the time synchronization information of the master device 103 (sub-base host) using the learned model obtained by the learning process, and when a switch from the master device 101 to the master device 103 occurs, the time synchronization is performed according to the estimated time of the master device 101 (base host). As a result, even if a switch from the master device 101 to the master device 103 occurs, the degradation of the synchronization accuracy associated with the switch can be suppressed.

[0054] Next, each device (master device 101, 103, slave device 102, switch device 104) constituting the time synchronization system 10 will be described. Figure 2 An example of the hardware structure of each device is shown. Each device is composed of a CPU (Central Processing Unit) 111, an I / F (Interface) device 112, a RAM (Random Access Memory) 113, and a ROM (Read Only Memory) 114. The I / F device 112, RAM 113, and ROM 114 are connected to the CPU 111 via a bus 115.

[0055] CPU111 expands and executes the program stored in ROM114 in RAM113. The program stored in ROM114 is a program that describes the steps of various processes performed in each device. According to the program, various processes for time synchronization are performed in each device. In addition, it is not limited to the processing based on software as described above, and it can also be processed using dedicated hardware (electronic circuit).

[0056] Figure 3 An example of the functional configuration of each device constituting the time synchronization system 10 is shown. Figure 3, the structure of each device having a common time synchronization function is shown. That is, in addition to each slave device 102 and each switch device 104 having Figure 3 In addition to the structure shown, the master device 101, 103 capable of operating as a slave device also has Figure 3 Hereinafter, each device having a structure for realizing the time synchronization function is referred to as a "time synchronization device 200".

[0057] The time synchronization device 200 includes a network interface unit 201 , a time stamp processing unit 202 , a protocol stack processing unit 203 , a synchronization control unit 204 , a clock control unit 205 , and a synchronization time inference unit 206 .

[0058] The network interface section 201 , the time stamp processing section 202 , and the protocol stack processing section 203 have the same functions as those specified by IEEE Std 1588-2008.

[0059] Reference Figure 4 right Figure 3 1 and 2 will be described with reference to an example of the structure of the clock control unit 205 shown in FIG. The clock control unit 205 includes a local clock 301 and a master clock 302. The local clock 301 and the master clock 302 are driven by an RC (Resistance Capacitance) oscillator, a quartz oscillator, a rubidium transmitter, an oscillator with a temperature compensation function, an oscillator with a temperature control function, etc., respectively, according to the required clock accuracy.

[0060] The local clock 301 generates the local time in the time synchronization device 200. The time generated by the local clock 301 is basically not synchronized with the time of the master device 101 (infrastructure host).

[0061] On the other hand, the master clock 302 is synchronized with the time of the master device 101 (base host). The time of the master clock 302 reflects the time of the master device 101 (base host) calculated by the synchronization control unit 204 (described later), the clock frequency deviation amount of the clock frequency of the master device 101 (base host) for adjusting the clock frequency of the master device 101 (base host), etc. In addition, when the clock is increased according to the output of the oscillator, for example, the increase amount can be adjusted to achieve the speed adjustment of the clock frequency.

[0062] Refer again Figure 3, the synchronization control unit 204 performs various processes related to the time synchronization with the main device 101 (basic host). Specifically, the synchronization control unit 204 controls the sending and receiving of the time synchronization packet with the main device 101. Then, the synchronization control unit 204 sends and receives the time synchronization packet with the main device 101, thereby obtaining the time synchronization information of the main device 101 (basic host). In detail, the synchronization control unit 204 collects the sending and receiving time of the time synchronization packet and the field information in the packet, and calculates the time of the main device 101 based on this information. In addition, the synchronization control unit 204 also obtains the time required for the time synchronization packet sent from the main device 101 to propagate in the transmission path, the time required for the switch device 104 on the transmission path to forward the time synchronization packet, etc. as the time synchronization information of the main device 101.

[0063] Furthermore, the synchronization control unit 204 also controls the transmission and reception of the time synchronization packet with the master device 103 (sub-base host). Then, the synchronization control unit 204 transmits and receives the time synchronization packet with the master device 103, thereby acquiring the time synchronization information of the master device 103 (sub-base host).

[0064] Next, refer to Figures 5 to 10 right Figure 3 The synchronization time inference unit 206 shown will be described. Figure 5 The following is an example of the configuration of the synchronization time inference unit 206. The synchronization time inference unit 206 includes a model learning unit 401, an inference unit 402, and a learned model storage unit 403.

[0065] Figure 6 An example of the structure of the model learning unit 401 is shown. The model learning unit 401 includes a learning data acquisition unit 501 and a model generation unit 502. The learning data acquisition unit 501 acquires the time synchronization information of the main device 101 (base host) and the time synchronization information of the main device 103 (sub-base host) from the synchronization control unit 204, and generates learning data that associates the time synchronization information of the main device 103 (sub-base host) with the time of the main device 101 (base host).

[0066] Regarding the association of data, for example, data whose acquisition times are close to each other can be associated. Alternatively, the master device 103 (sub-base host) is also synchronized with the master device 101 (base host), so the synchronization cycle with the master device 103 and the synchronization cycle with the master device 101 can also be synchronized, and the data can be associated using the sequenceId specified in IEEE Std 1588-2008. In addition, the sequenceId is an ID that is sequentially assigned according to the cycle of executing the time synchronization in order to obtain the matching of the time sequence of the time synchronization group.

[0067] Alternatively, the learning data acquisition unit 501 may sequentially generate learning data each time the learning data is acquired in a synchronization cycle with the master device, or may generate learning data based on time-series time synchronization information acquired within a predetermined period.

[0068] The model generation unit 502 uses the learning data acquired by the learning data acquisition unit 501 to perform a learning process for estimating the time of the main device 101 (base host) based on the time synchronization information of the main device 103 (sub-base host), thereby generating a learned model.

[0069] That is, the model generation unit 502 performs learning processing using learning data including the time synchronization information of the main device 103 (sub-base host) and the time of the main device 101 (base host), and generates a model that estimates the time of the main device 101 (base host) based on the time synchronization information of the main device 103 (sub-base host) even if the time of the main device 101 (base host) is not obtained. In addition, regarding the learning data, the time synchronization information of the main device 103 (sub-base host) is the data input to the model, and the time of the main device 101 (base host) is the supervision data.

[0070] Regarding learning, learning can be performed repeatedly each time the learning data acquisition unit 501 successively acquires time synchronization information, or when the learning data acquisition unit 501 acquires time synchronization information of a time series within a specified period, learning can be performed through a one-time learning based on the time synchronization information of the time series.

[0071] The time synchronization information includes not only the time of the master device, but also the time required for the time synchronization packet sent from the master device to propagate in the transmission path, the time required for the switch device 104 on the transmission path to forward the time synchronization packet, etc. As an example, the time synchronization information includes the sending time of the Sync message, the CorrectionField value obtained by adding the delay time when the Sync message is relayed, the propagation delay time between the master and the slave obtained by the Peer to Peer Delay Mechanism or the Request-Response Mechanism, etc. By using this time synchronization information as learning data, the accuracy of the learned model (the time estimation accuracy of the master device 101 (base host) based on the learned model) can be improved. In particular, the above-mentioned information often changes over time, so by using it as time series data for learning, further improvement in accuracy can be expected.

[0072] In addition, part of the time synchronization information (transmission delay time, etc.) of the master device 101 (base host) can also be used as input data for learning data. Basically, in order to prevent failures related to the master device 101 (base host), the time of the master device 101 is calculated based on the time synchronization information of the master device 103 (sub-base host), but the time synchronization information of the master device 101 is also related to the time of the master device 101, so part of the time synchronization information of the master device 101 (transmission delay time, etc.) can also be used for learning.

[0073] The learning algorithm of the model generation unit 502 can adopt a known supervised learning algorithm. Supervised learning refers to a method in which a set of input and result (label) data is provided to a learning device, the features in these learning data are learned, and the result is inferred based on the input. As an example, the case of using a neural network model in the learning algorithm is described.

[0074] A neural network is composed of an input layer containing multiple neurons, an intermediate layer (hidden layer) containing multiple neurons, and an output layer containing multiple neurons. The intermediate layer can be one layer or two or more layers.

[0075] For example, in Figure 7 In the case of the three-layer neural network shown, when multiple input values ​​are input to the input layer 410 (X1-X3), the value obtained by multiplying the output of the input layer 410 by the weight W1 (w11-w16) is provided to the intermediate layer 411 (Y1-Y2). Then, the value obtained by multiplying the output of the intermediate layer 411 by the weight W2 (w21-w26) is provided to the output layer 412 (Z1-Z3), and multiple output values ​​are output from the output layer 412. The output values ​​change according to the values ​​of the weights W1 and W2.

[0076] In the first embodiment, the neural network learns the time of the main device 101 (base host) using the learning data including the time synchronization information of the main device 103 (sub-base host) and the time of the main device 101 (base host) acquired by the learning data acquisition unit 501. More specifically, the time synchronization information of the main device 103 (sub-base host) is provided to the input layer, and the weights W1 and W2 are adjusted so that the output from the output layer approaches the time (supervisory data) of the main device 101 (base host).

[0077] In addition, the learning algorithm used in the model generation unit 502 is not limited to the above-mentioned neural network model algorithm. For example, deep learning algorithms that also extract feature quantities, genetic programming, functional logic programming, support vector machine algorithms, etc. can also be used.

[0078] The model generation unit 502 performs the above-mentioned learning to generate a learned model. Then, the learned model generated by the model generation unit 502 is stored in the learned model storage unit 403 ( Figure 6 ).

[0079] Reference Figure 8 An example of the steps of the processing performed by the model learning unit 401 of the synchronization time inference unit 206 is described. The model learning unit 401 obtains the time synchronization information of the master device 101 (base host) and the time synchronization information of the master device 103 (sub-base host) from the synchronization control unit 204 (step S10). In addition, the timing of obtaining the two time synchronization information from the synchronization control unit 204 may be simultaneous or different.

[0080] Next, the model learning unit 401 associates the time synchronization information of the main device 103 (sub-base host) with the time of the main device 101 (base host) to generate learning data (step S20). As described above, the data can be associated by making the acquisition times close to each other, or by using the sequenceId specified in IEEE Std 1588-2008.

[0081] Then, the model learning unit 401 uses the learning data generated in step S20 to perform a learning process for estimating the time of the main device 101 (base host) based on the time synchronization information of the main device 103 (sub-base host) (step S30). Specifically, the model learning unit 401 uses the time synchronization information of the main device 103 (sub-base host) as input data and the time of the main device 101 (base host) as supervision data, and generates a model for estimating the time of the main device 101 (base host) based on the time synchronization information of the main device 103 (sub-base host).

[0082] After executing the learning process, the model learning unit 401 stores the generated learned model in the learned model storage unit 403 (step S40 ).

[0083] In addition, for example, the above method may be repeatedly executed each time the time synchronization information is acquired in the synchronization cycle with the master device. Figure 8 The series of processing shown in the figure may be performed every time the prescribed period elapses, when learning is performed based on the time synchronization information of the time series within the prescribed period. Figure 8 A series of processing shown.

[0084] Next, Figure 5 The inference unit 402 shown will be described. Fig. 9An example of the structure of the inference unit 402 is shown. The inference unit 402 includes an inference data acquisition unit 601 and an inference control unit 602. The inference data acquisition unit 601 acquires the time synchronization information of the main device 103 (sub-base host) from the synchronization control unit 204. The inference data acquisition unit 601 may acquire the time synchronization information in the synchronization cycle with the main device 103 (sub-base host), or may acquire the time synchronization information as time series data acquired within a predetermined period.

[0085] The inference control unit 602 obtains the learned model generated by the model learning unit 401 from the learned model storage unit 403, and estimates the time of the main device 101 (base host) using the learned model. Specifically, the inference control unit 602 inputs the time synchronization information of the main device 103 (sub-base host) obtained by the inference data acquisition unit 601 into the learned model, and outputs the output of the learned model to the synchronization control unit 204 as the estimated time of the main device 101 (base host).

[0086] Reference Fig.10 An example of the steps of the processing performed by the inference unit 402 of the synchronization time inference unit 206 is described. The inference unit 402 obtains the time synchronization information of the master device 103 (sub-base host) for inferring the time of the master device 101 (base host) from the synchronization control unit 204 (step S110). In addition, the time synchronization information obtained from the synchronization control unit 204 may be, for example, information obtained according to the synchronization cycle with the master device 103, or may be time synchronization information of a time series within a predetermined period.

[0087] Next, the inference unit 402 obtains the learned model generated by the model learning unit 401 from the learned model storage unit 403, and inputs the time synchronization information of the main device 103 (sub-base host) obtained in step S110 into the learned model (step S120). Then, the inference unit 402 uses the learned model to perform inference processing for estimating the time of the main device 101 (base host), and outputs the output result of the learned model as the estimated time of the main device 101 (base host) to the synchronization control unit 204 (step S130).

[0088] Thus, even when the time synchronization device 200 cannot receive a time synchronization packet from the master device 101 (root host), the time synchronization device 200 can continue to synchronize with the time equivalent to the time of the master device 101 (root host).

[0089] In addition, for example, the above operation may be repeatedly executed each time the time synchronization information is acquired in the synchronization cycle with the master device 103. Fig.10 The series of processing shown in the figure may also be executed according to the prescribed period when inference is performed based on the time synchronization information of the time series within the prescribed period. Fig.10 A series of processing shown.

[0090] Next, refer to Fig.11 An example of the processing steps of the time synchronization control performed by the synchronization control unit 204 is described. The synchronization control unit 204 transmits and receives time synchronization packets with each master device, thereby obtaining the time synchronization information of each master device (step S210). Then, the synchronization control unit 204 determines whether the time synchronization information of the master device 101 (base host) can be obtained in step S210 (step S220).

[0091] When the time synchronization information of the master device 101 (base host) can be obtained (step S220: Yes), the synchronization control unit 204 synchronizes the time synchronization device 200 with the time of the master device 101 (base host) (step S230). Then, the synchronization control unit 204 notifies the synchronization time inference unit 206 of the obtained time of the master device 101 (base host) (step S240). In addition, the time of the master device 101 (base host) is used as supervision data for learning processing in the synchronization time inference unit 206.

[0092] On the other hand, when it is determined in step S220 that the time synchronization information of the master device 101 (base host) cannot be obtained (step S220: No), the synchronization control unit 204 obtains the estimated time of the master device 101 (base host) from the synchronization time inference unit 206 (step S250). Then, the synchronization control unit 204 synchronizes the time synchronization device 200 with the estimated time of the master device 101 (base host) obtained from the synchronization time inference unit 206 (step S260).

[0093] In addition, although not specifically described above, regardless of the result of determining whether the time synchronization information of the main device 101 (base host) can be obtained in step S220, the synchronization control unit 204 sends the obtained time synchronization information of the main device 103 (sub-base host) to the synchronization time inference unit 206.

[0094] In addition, when a plurality of master devices 103 (sub-base hosts) are provided in the time synchronization system 10, the model generation unit 502 ( Figure 6 ) can also generate a model using learning data containing time synchronization information obtained from multiple main devices 103 (sub-base hosts), and can also generate a model based on the time synchronization information obtained for each main device 103 (sub-base host).

[0095] In this case, for example, learning may be performed on the reliability of the inference result, and a model may be selected based on the reliability. In addition, regarding the reliability, for example, the reliability may be calculated based on the difference between the time obtained from the time synchronization information of the main device 101 (base host) and the estimated time of the main device 101 (base host), and the relationship between the input data and the reliability may be learned, thereby estimating the reliability based on the input data.

[0096] In addition, the model learning unit 401 can obtain learning data collected from devices constituting multiple networks used in the same area, and can also use learning data collected from devices constituting multiple networks operating independently in different areas to learn the time of the main device 101 (basic host).

[0097] Furthermore, the learning device in a certain time synchronization device 200 may be applied to the time synchronization device 200 in another network so that the time synchronization device 200 in the network can relearn and update the time of the master device (base host).

[0098] In addition, in the above, the learned model generated by the model generation unit 502 of the time synchronization device 200 is used to output the time of the main device 101 (base host), but the learned model can also be obtained from the time synchronization device 200 and the learned model can be used to output the time of the main device 101 (base host).

[0099] In the above, the synchronization time inference unit 206 is used to learn the time of the master device 101 (base host) used by the time synchronization device 200 for time synchronization, but the synchronization time inference unit 206 may be provided in a device independent of the time synchronization device 200. The synchronization time inference unit 206 may exist on a cloud server, or part of the learning process and the inference process may be provided in a cloud server or an independent device.

[0100] As described above, in the first embodiment, a learning process is performed to estimate the time of the master device 101 (base host) based on the time synchronization information of the master device 103 (sub-base host). Then, the time of the master device 101 (base host) is estimated based on the time synchronization information of the master device 103 (sub-base host) using the generated learned model, and when a switch from the master device 101 to the master device 103 occurs, the time synchronization is performed according to the estimated time of the master device 101 (base host). Therefore, according to the first embodiment, even if a switch from the master device 101 to the master device 103 occurs, the degradation of the synchronization accuracy associated with the switch can be suppressed.

[0101] Furthermore, according to this embodiment 1, not only the moment of the main unit 103 (sub-base host) but also the moment synchronization information of the main unit 103 (sub-base host) (including information such as the delay time associated with the release moment) is used for learning and reasoning, thereby improving the accuracy of the learned model (the accuracy of the time estimation of the main unit 101 (base host) based on the learned model).

[0102] Implementation Method 2

[0103] In the first embodiment, when a failure occurs in the master device 101 (base host) or in the transmission path between the master device 101 and the master device 101, the time of the master device 101 (base host) is estimated using the time synchronization information of the master device 103 (sub-base host) from the time when the failure occurs. However, since learning is not performed from that time, the estimated time of the master device 101 (base host) by the inference unit 402 may deviate from the time that the master device 101 (base host) should have issued as time passes.

[0104] Therefore, in the case where there are multiple master devices 103 (sub-base hosts), in this second embodiment, when a failure occurs in the master device 101 (base host) or the transmission path, the master-slave relationship between the devices constituting the network is reconstructed, and the base host is re-selected from the multiple master devices 103 (sub-base hosts). Then, the other devices synchronize with the selected master device (base host).

[0105] In addition, as a condition for re-selecting the base host, for example, it can be set as a case where the time synchronization packet is not received from the main device 101 (base host) for a specified time (a case where a failure occurs), or it can be set as a case where the reliability of the synchronization time estimated based on the time synchronization information of the main device 103 (sub-base host) is lower than a specified level, etc. In addition, as a method for re-selecting the base host, the BMC algorithm specified in IEEE Std 1588-2008 can be used.

[0106] Implementation 3

[0107] In this third embodiment, the reliability of the time of the main device 101 (base host) estimated from the time synchronization information of the main device 103 (sub-base host) is calculated. In addition, the calculated reliability is taken into the learning data, and the learning process for estimating the reliability is performed, and the reliability is estimated using the learned model.

[0108] Reference Figure 12 to Figure 15 The synchronization time inference unit in the third embodiment will be described. Fig.12 An example of the structure of the synchronization time inference unit 206A is shown. Figure 5The configuration of the synchronization time inference unit 206 shown further includes a reliability calculation unit 404 , and includes a model learning unit 401A and an inference unit 402A instead of the model learning unit 401 and the inference unit 402 .

[0109] Reference Fig.13 The reliability calculation unit 404 is described. The reliability calculation unit 404 calculates the reliability of the estimated time of the master device 101 using the time synchronization information of the master device 101 (base host) received from the synchronization control unit 204 and the time of the master device 101 estimated by the inference unit 402A based on the time synchronization information of the master device 103 (sub-base host).

[0110] For example, the reliability calculation unit 404 calculates the reliability based on the difference between the time synchronization information of the main device 101 (base host) and the time of the main device 101 estimated by the inference unit 402A. Alternatively, the reliability can also be calculated based on the change in the weight coefficient updated when the model learning unit 401A performs the learning process. As the learning progresses, the higher the accuracy of the estimated synchronization time, the smaller the change.

[0111] Fig.14 FIG. 4 shows an example of the structure of the model learning unit 401A. The model learning unit 401A includes a learning data acquisition unit 501A and a model generation unit 502A. The learning data acquisition unit 501A is Figure 6 Based on the functions of the learning data acquisition unit 501 described in the above, the reliability information of the estimated synchronization time is acquired from the reliability calculation unit 404, and learning data is generated by associating the time synchronization information of the main device 103 (sub-base host) with the reliability information of the estimated synchronization time. The association and generation timing of the learning data are the same as those in the first embodiment.

[0112] The model generation unit 502A uses the learning data acquired by the learning data acquisition unit 501A to perform the same learning process as in the first embodiment to generate a learned model. In addition, differently from this, the model generation unit 502A performs a learning process for estimating the reliability of the synchronization time based on the time synchronization information of the main device 103 (sub-base host) to generate a learned model. In addition, when the reliability is calculated based on the change amount of the weight coefficient of the model learning unit 401A in the reliability calculation unit 404, the model generation unit 502A outputs the change amount of the weight coefficient updated when the learning process is executed to the reliability calculation unit 404.

[0113] Fig.15 FIG. 4 shows an example of the structure of the inference unit 402A. The inference unit 402A includes an inference data acquisition unit 601 and an inference control unit 602A. Fig. 9The same situation as described in .

[0114] The inference control unit 602A obtains the learned model generated by the model learning unit 401A from the learned model storage unit 403, estimates the time of the main device 101 (base host) using the learned model, and estimates the reliability of the estimated time. Specifically, the inference control unit 602A inputs the time synchronization information of the main device 103 (sub-base host) obtained by the inference data acquisition unit 601 into the learned model, and outputs the output of the learned model as the estimated time of the main device 101 (base host) and the reliability of the estimated time to the synchronization control unit 204.

[0115] When the synchronization control unit 204 cannot obtain the time synchronization information of the main device 101 (base host), it obtains the time of the main device 101 (base host) estimated by the inference control unit 602A and the reliability of the estimated time from the inference control unit 602A (synchronization time inference unit 206A).

[0116] When the reliability of the time of the master device 101 (base host) obtained is lower than a predetermined reference, the synchronization control unit 204 may perform a process of reselecting a base host from a plurality of master devices 103 (sub-base hosts) as exemplified in Embodiment 2. Alternatively, the synchronization control unit 204 may perform time synchronization based on the most reliable time among the reliabilities estimated for each master device 103 (sub-base host).

[0117] As described above, in this embodiment 3, the reliability of the time of the main device 101 (base host) estimated from the time synchronization information of the main device 103 (sub-base host) is calculated. Therefore, according to this embodiment 3, for example, when the reliability is lower than the reference, the base host can be re-selected or the time synchronization can be performed according to the time with the highest reliability.

[0118] It should be understood that the embodiments disclosed this time are illustrative in all aspects and are not restrictive. The technical scope of the present invention is not shown by the description of the above embodiments, but by the claims, and is intended to include all changes within the meaning and scope equivalent to the claims.

[0119] Industrial Applicability

[0120] The time synchronization system 10 of the present invention can be used in, for example, a FA (Factory Automation) network, a base station network, an in-vehicle network, and the like.

[0121] Description of symbols

[0122] 10: time synchronization system; 101: master device (base host); 102: slave device; 103: master device (sub-base host); 104: switch device; 111: CPU; 112: I / F device; 113: RAM; 114: ROM; 115: bus; 200: time synchronization device; 201: network interface unit; 202: time stamp processing unit; 203: protocol stack processing unit; 204: synchronization control unit; 205: clock control unit; 206, 206A : Synchronous time inference unit; 210: Network; 301: Local clock; 302: Master clock; 401, 401A: Model learning unit; 402, 402A: Inference unit; 403: Learned model storage unit; 404: Reliability calculation unit; 410: Input layer; 411: Middle layer; 412: Output layer; 501, 501A: Learning data acquisition unit; 502, 502A: Model generation unit; 601: Inference data acquisition unit; 602, 602A: Inference control unit.

Claims

1. A time synchronization system, the time synchronization system comprising: The first master device and the second master device publish the time through the network; a learning unit that uses learning data including the time synchronization information of the first master device and the time of the second master device to perform a learning process for estimating the time of the second master device based on the time synchronization information of the first master device; an inference unit that estimates the time of the second master device based on the time synchronization information of the first master device using the learned model obtained by the learning process; and a slave device that performs time synchronization according to the acquired time when the time is acquired from the second master device, and performs time synchronization according to the time estimated by the inference unit when the time is not acquired from the second master device; in, The time synchronization information includes the time of the first master device and information on a delay time associated with the time being distributed from the first master device via the network.

2. The time synchronization system according to claim 1, wherein: The learning unit and the inference unit are provided in the slave device.

3. The time synchronization system according to claim 1 or 2, wherein: The time synchronization system further includes a reliability calculation unit that calculates the reliability of the estimated time of the second master device based on the time synchronization information of the second master device and the time of the second master device estimated by the inference unit.

4. The time synchronization system according to claim 3, wherein: The learning data further includes the reliability calculated by the reliability calculation unit. The learning unit generates a learned model for estimating the reliability based on the time synchronization information of the first master device by executing a learning process using the learning data.

5. The time synchronization system according to claim 4, wherein: The inference unit further estimates the reliability based on the time synchronization information of the first master device using the learned model.

6. The time synchronization system according to claim 5, wherein: When the slave device has not obtained the time from the second master device and the reliability estimated by the inference unit is lower than a reference, the slave device performs a process of reselecting a master device to replace the second master device.

7. The time synchronization system according to claim 5, wherein: In the case where a plurality of the first main devices are provided, The inference unit estimates the reliability for each of the first master devices. When the slave device has not obtained the time from the second master device, the slave device performs time synchronization according to the most reliable time.

8. A learning device, comprising: a data acquisition unit that acquires learning data including the time synchronization information of the first master device and the time of the second master device based on the time synchronization information of each of the first master device and the second master device that publish the time via the network; and a model generating unit that performs a learning process using the learning data to generate a learned model for estimating the time of the second master device based on the time synchronization information of the first master device; in, The time synchronization information includes the time of the first master device and information on a delay time associated with the time being distributed from the first master device via the network.

9. The learning device according to claim 8, wherein: The time synchronization information of the first master device includes the time of the first master device and information on a delay time associated with the time being distributed from the first master device via the network.

10. An inference device, comprising: a data acquisition unit that acquires time synchronization information of a first master device that distributes time via a network; and an inference control unit that estimates the time of the second master device based on the time synchronization information acquired by the data acquisition unit, using a learned model for estimating the time of the second master device that issues the time via a network based on the time synchronization information of the first master device, The learned model is a model obtained by learning using learning data including the time synchronization information of the first master device and the time of the second master device; in, The time synchronization information includes the time of the first master device and information on a delay time associated with the time being distributed from the first master device via the network.

11. The inference device according to claim 10, wherein: The time synchronization information of the first master device includes the time of the first master device and information on a delay time associated with the time being distributed from the first master device via the network.

12. A time synchronization device, comprising: The inference device according to claim 10 or 11; and A synchronization control unit performs time synchronization according to the acquired time when the time is acquired from the second master device, and performs time synchronization according to the time estimated by the inference device when the time is not acquired from the second master device.

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