A dynamic zero-point compensation sampling circuit and low-dropout linear voltage regulator

Abstract

The application provides a dynamic zero compensation sampling circuit and low dropout linear voltage regulator, comprising: a first amplifier, which compares a feedback voltage and a reference voltage and outputs a first comparison signal; a power tube unit, which processes an input voltage and outputs an output voltage to an output end; a sampling unit, which comprises a sampling branch and samples a voltage under the action of the first comparison signal; an error amplifier, which compares the output voltage and the sampling voltage and outputs a first control signal; a load current sampling branch, which samples to obtain a load sampling current under the action of the first control signal; a second comparison unit, which is used for comparing the load sampling current and a reference current and outputs a second comparison signal; and a frequency compensation unit, which compensates the sampling unit in frequency under the action of the second comparison signal. Beneficial effects: the load current is sampled, a dynamic zero point is generated to compensate an output pole under light load and no load, and the phase margin of the circuit is ensured.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit technology, and in particular to a dynamic zero point compensation sampling circuit and a low dropout linear regulator. BACKGROUND

[0002] A low dropout linear regulator (LDO) is a kind of linear regulator, which uses a transistor or a field effect transistor (FET) operating in its saturation region to subtract excess voltage from the input voltage of the application to generate an adjusted output voltage.

[0003] With the rapid development of integrated circuits and the trend of the integration of computer, communication and multimedia technologies, more and more functions are integrated into chips. The performance of the power supply circuit directly affects the precision, stability and reliability of the entire electronic product. The phase margin of the existing LDO chip under light load and no load is poor, which cannot meet the current application requirements. SUMMARY

[0004] In order to solve the above technical problems, the present application provides a dynamic zero point compensation sampling circuit and a low dropout linear regulator.

[0005] The technical problems solved by the present application can be realized by the following technical solutions:

[0006] A dynamic zero point compensation sampling circuit applied to a low dropout linear regulator, comprising:

[0007] A first amplifier for comparing a feedback voltage and a reference voltage and outputting a first comparison signal;

[0008] A power tube unit for processing an input voltage under the action of the first comparison signal and outputting an output voltage to an output terminal;

[0009] A sampling unit including a sampling branch for sampling under the action of the first comparison signal and outputting a sampling voltage; an error amplifier for comparing the output voltage and the sampling voltage and outputting a first control signal;

[0010] A load current sampling branch for sampling the load under the action of the first control signal to obtain a load sampling current;

[0011] A second comparison unit for comparing the load sampling current and a reference current and outputting a second comparison signal;

[0012] A frequency compensation unit for frequency compensating the sampling unit under the action of the second comparison signal.

[0013] Preferably, the positive input terminal of the first amplifier is connected to the reference voltage, and the negative input terminal of the first amplifier is connected to the feedback terminal of the low dropout linear regulator.

[0014] Preferably, the power tube unit comprises:

[0015] a first NMOS tube, a gate of the first NMOS tube is connected to the output terminal of the first amplifier, a drain of the first NMOS tube is connected to the power supply terminal, and a source of the first NMOS tube is connected to the output terminal of the low dropout linear regulator;

[0016] a third NMOS tube, a gate of the third NMOS tube is connected to the first bias voltage, a drain of the third NMOS tube is connected to the source of the first NMOS tube, and a source of the third NMOS tube is connected to the ground terminal.

[0017] Preferably, the sampling branch comprises:

[0018] a second NMOS tube, a gate of the second NMOS tube is connected to the output terminal of the first amplifier, a drain of the second NMOS tube is connected to the power supply terminal, and a source of the second NMOS tube outputs the sampling voltage;

[0019] a fourth NMOS tube, a gate of the fourth NMOS tube is connected to the first control signal, a drain of the fourth NMOS tube is connected to the source of the second NMOS tube, and a source of the fourth NMOS tube is connected to the ground terminal.

[0020] Preferably, the error amplifier comprises:

[0021] a first PMOS tube, a gate of the first PMOS tube is connected to a second bias voltage, and a source of the first PMOS tube is connected to the power supply terminal;

[0022] a second PMOS tube, a gate of the second PMOS tube is connected to the output voltage, and a source of the second PMOS tube is connected to the drain of the first PMOS tube;

[0023] a third PMOS tube, a gate of the third PMOS tube is connected to the sampling voltage, a source of the third PMOS tube is connected to the drain of the first PMOS tube, and a drain of the third PMOS tube outputs the first control signal;

[0024] a fifth NMOS tube, a gate and a drain of the fifth NMOS tube are connected to the drain of the second PMOS tube, and a source of the fifth NMOS tube is connected to the ground terminal;

[0025] a sixth NMOS transistor, a gate of the sixth NMOS transistor is connected to a gate of the fifth NMOS transistor, a drain of the sixth NMOS transistor is connected to a drain of the third PMOS transistor, and a source of the sixth NMOS transistor is connected to the ground terminal.

[0026] Preferably, the frequency compensation unit comprises:

[0027] a seventh NMOS transistor, a gate of the seventh NMOS transistor is connected to the second comparison signal, a drain of the seventh NMOS transistor is connected to the first control signal, and a source of the seventh NMOS transistor is connected in parallel with a first resistor;

[0028] a first capacitor, an anode of the first capacitor is connected to the first resistor through a second resistor, and a cathode of the first capacitor is connected to the ground terminal.

[0029] Preferably, the load current sampling branch comprises:

[0030] an eighth NMOS transistor, a gate of the eighth NMOS transistor is connected to a third bias voltage;

[0031] a ninth NMOS transistor, a gate of the ninth NMOS transistor is connected to the first control signal, a drain of the ninth NMOS transistor is connected to a source of the eighth NMOS transistor, and a source of the ninth NMOS transistor is connected to the ground terminal.

[0032] Preferably, the circuit further comprises:

[0033] a fourth PMOS transistor, a gate and a drain of the fourth PMOS transistor are connected to the drain of the eighth NMOS transistor, and a source of the fourth PMOS transistor is connected to the power supply terminal.

[0034] Preferably, the circuit further comprises:

[0035] a fifth PMOS transistor, a source of the fifth PMOS transistor is connected to the power supply terminal, and a gate of the fifth PMOS transistor is connected to a gate of the fourth PMOS transistor.

[0036] a tenth NMOS transistor, a gate and a drain of the tenth NMOS transistor are connected to the drain of the fourth PMOS transistor.

[0037] an eleventh NMOS transistor, a gate and a drain of the eleventh NMOS transistor are connected to a source of the tenth NMOS transistor, and a source of the eleventh NMOS transistor is connected to the ground terminal.

[0038] Preferably, the second comparison unit comprises:

[0039] a twelfth NMOS transistor, a gate of the twelfth NMOS transistor is connected to a drain of the tenth NMOS transistor, a drain of the twelfth NMOS transistor is connected to a power supply terminal;

[0040] a thirteenth NMOS transistor, a gate of the thirteenth NMOS transistor is connected to a fourth bias voltage, a drain of the thirteenth NMOS transistor is connected to a source of the twelfth NMOS transistor, a source of the thirteenth NMOS transistor is connected to a ground terminal;

[0041] a sixth PMOS transistor, a gate of the sixth PMOS transistor is connected to a gate of the fourth PMOS transistor, a source of the sixth PMOS transistor is connected to the power supply terminal, and the second comparison signal is output from a drain of the sixth PMOS transistor;

[0042] a fourteenth NMOS transistor, a gate of the fourteenth NMOS transistor is connected to a fifth bias voltage, a drain of the fourteenth NMOS transistor is connected to a drain of the sixth PMOS transistor, and a source of the fourteenth NMOS transistor is connected to the ground terminal.

[0043] The application also provides a low-dropout linear voltage regulator comprising the dynamic zero compensation sampling circuit.

[0044] The application has the following advantages or beneficial effects:

[0045] The application samples the load current, generates a dynamic zero point to compensate for the output pole under light load or no load, and ensures the phase margin of the loop. BRIEF DESCRIPTION OF DRAWINGS

[0046] Figure 1 The application has the following advantages or beneficial effects:

[0047] Figure 2 The application has the following advantages or beneficial effects: DETAILED DESCRIPTION

[0048] The technical solutions in the embodiments of the application will be described clearly and completely below with reference to the drawings in the embodiments of the application. Obviously, the described embodiments are only part of the embodiments of the application, rather than all the embodiments of the application. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the application.

[0049] It should be noted that the embodiments in the application and the features in the embodiments can be combined with each other without conflict.

[0050] The application will be further described in connection with the drawings and specific embodiments, but not as a limitation of the application.

[0051] In the preferred embodiment of the application, in view of the above problems existing in the prior art, a dynamic zero point compensation sampling circuit is provided, which is applied to a low dropout linear regulator and belongs to the technical field of integrated circuits, as shown in the accompanying drawings, comprising: Figure 1

[0052] a first amplifier EA for comparing a feedback voltage V FB and a reference voltage V REF and outputting a first comparison signal;

[0053] a power tube unit for processing an input voltage V IN under the action of the first comparison signal and outputting an output voltage V OUT to an output terminal;

[0054] a sampling unit comprising a sampling branch for sampling under the action of the first comparison signal and outputting a sampling voltage V sap ; an error amplifier for comparing the output voltage V OUT and the sampling voltage V sap and outputting a first control signal V s ;

[0055] a load current sampling branch for sampling the load under the action of the first control signal V s to obtain a load sampling current;

[0056] a second comparison unit for comparing the load sampling current and a reference current and outputting a second comparison signal;

[0057] a frequency compensation unit for frequency compensating the sampling unit under the action of the second comparison signal.

[0058] In the embodiment of the application, the load current is sampled, the dynamic zero point is generated to compensate the output pole under light load and no load, the phase margin of the loop is ensured, and the stability of the circuit under light load and no load is ensured.

[0059] As a preferred embodiment, wherein the positive input terminal of the first amplifier EA is connected to the reference voltage V REF , and the negative input terminal of the first amplifier EA is connected to the feedback terminal of the low dropout linear regulator.

[0060] As a preferred embodiment, wherein the power tube unit comprises:

[0061] ​a first NMOS transistor NM1, a gate of the first NMOS transistor NM1 is connected to an output of the first amplifier EA, a drain of the first NMOS transistor NM1 is connected to a power supply terminal, and a source of the first NMOS transistor NM1 is connected to an output of the low dropout linear regulator;

[0062] a third NMOS transistor NM3, a gate of the third NMOS transistor NM3 is connected to a first bias voltage Vbias1, a drain of the third NMOS transistor NM3 is connected to the source of the first NMOS transistor NM1, and a source of the third NMOS transistor NM3 is connected to a ground terminal.

[0063] As a preferred embodiment, the sampling branch comprises:

[0064] a second NMOS transistor NM2, a gate of the second NMOS transistor NM2 is connected to the output of the first amplifier EA, a drain of the second NMOS transistor NM2 is connected to the power supply terminal, and a source of the second NMOS transistor NM2 outputs a sampling voltage V sap ;

[0065] a fourth NMOS transistor NM4, a gate of the fourth NMOS transistor NM4 is connected to a first control signal V s , a drain of the fourth NMOS transistor NM4 is connected to the source of the second NMOS transistor NM2, and a source of the fourth NMOS transistor NM4 is connected to the ground terminal.

[0066] As a preferred embodiment, the error amplifier comprises:

[0067] a first PMOS transistor PM1, a gate of the first PMOS transistor PM1 is connected to a second bias voltage Vbias2, and a source of the first PMOS transistor PM1 is connected to the power supply terminal;

[0068] a second PMOS transistor PM2, a gate of the second PMOS transistor PM2 is connected to the output voltage, and a source of the second PMOS transistor PM2 is connected to a drain of the first PMOS transistor PM1;

[0069] a third PMOS transistor PM3, a gate of the third PMOS transistor PM3 is connected to the sampling voltage, a source of the third PMOS transistor PM3 is connected to the drain of the first PMOS transistor PM1, and a drain of the third PMOS transistor PM3 outputs the first control signal V s ;

[0070] a fifth NMOS transistor NM5, a gate and a drain of the fifth NMOS transistor NM5 are connected to the drain of the second PMOS transistor PM2, and a source of the fifth NMOS transistor NM5 is connected to the ground terminal;

[0071] A sixth NMOS transistor NM6, a gate of the sixth NMOS transistor NM6 is connected with a gate of the fifth NMOS transistor NM5, a drain of the sixth NMOS transistor NM6 is connected with a drain of the third PMOS transistor PM3, and a source of the sixth NMOS transistor NM6 is connected with a ground terminal.

[0072] As a preferred implementation, the frequency compensation unit comprises:

[0073] A seventh NMOS transistor NM7, a gate of the seventh NMOS transistor NM7 is connected with a second comparison signal, a drain of the seventh NMOS transistor NM7 is connected with a first control signal V s , and a source of the seventh NMOS transistor NM7 is connected in parallel with a drain of the seventh NMOS transistor NM7 through a first resistor R1.

[0074] A first capacitor C1, an anode of the first capacitor C1 is connected with the first resistor through a second resistor R2, and a cathode of the first capacitor C1 is connected with a ground terminal.

[0075] As a preferred implementation, the load current sampling branch comprises:

[0076] An eighth NMOS transistor NM8, a gate of the eighth NMOS transistor NM8 is connected with a third bias voltage Vbias3;

[0077] A ninth NMOS transistor NM9, a gate of the ninth NMOS transistor NM9 is connected with a first control signal V s , a drain of the ninth NMOS transistor NM9 is connected with a source of the eighth NMOS transistor NM8, and a source of the ninth NMOS transistor NM9 is connected with a ground terminal.

[0078] As a preferred implementation, further comprising:

[0079] A fourth PMOS transistor PM4, a gate and a drain of the fourth PMOS transistor PM4 are connected with a drain of the eighth NMOS transistor NM8, and a source of the fourth PMOS transistor PM4 is connected with a power supply terminal.

[0080] As a preferred implementation, further comprising:

[0081] A fifth PMOS transistor PM5, a source of the fifth PMOS transistor PM5 is connected with a power supply terminal, and a gate of the fifth PMOS transistor PM5 is connected with a gate of the fourth PMOS transistor PM4.

[0082] A tenth NMOS transistor NM10, a gate and a drain of the tenth NMOS transistor NM10 are connected with a drain of the fourth PMOS transistor PM4.

[0083] A eleventh NMOS transistor NM11, a gate and a drain of the eleventh NMOS transistor NM11 are connected to a source of the tenth NMOS transistor NM10, and a source of the eleventh NMOS transistor NM11 is connected to a ground terminal.

[0084] As a preferred embodiment, the second comparison unit comprises:

[0085] A twelfth NMOS transistor NM12, a gate of the twelfth NMOS transistor NM12 is connected to a drain of the tenth NMOS transistor NM10, and a drain of the twelfth NMOS transistor NM12 is connected to a power terminal.

[0086] A thirteenth NMOS transistor NM13, a gate of the thirteenth NMOS transistor NM13 is connected to a fourth bias voltage Vbias4, a drain of the thirteenth NMOS transistor NM13 is connected to a source of the twelfth NMOS transistor NM12, and a source of the thirteenth NMOS transistor NM13 is connected to the ground terminal.

[0087] A sixth PMOS transistor PM6, a gate of the sixth PMOS transistor PM6 is connected to a gate of the fourth PMOS transistor PM4, a source of the sixth PMOS transistor PM6 is connected to the power terminal, and a drain of the sixth PMOS transistor PM6 outputs a second comparison signal.

[0088] A fourteenth NMOS transistor NM14, a gate of the fourteenth NMOS transistor NM14 is connected to a fifth bias voltage Vbias5, a drain of the fourteenth NMOS transistor NM14 is connected to a drain of the sixth PMOS transistor PM6, and a source of the fourteenth NMOS transistor NM14 is connected to the ground terminal.

[0089] Further, the first bias voltage Vbias1, the second bias voltage Vbias2, the third bias voltage Vbias3, the fourth bias voltage Vbias4, and the fifth bias voltage Vbias5 are bias voltages inside the LDO, and provide gate voltages for the third NMOS transistor NM3, the first PMOS transistor PM1, the eighth NMOS transistor NM8, the thirteenth NMOS transistor NM13, and the fourteenth NMOS transistor NM14, respectively.

[0090] In the preferred embodiment, the working process of the embodiment of the present application is as follows:

[0091] The first NMOS transistor NM1 and the third NMOS transistor NM3 are power transistor stages, the second NMOS transistor NM2 and the fourth NMOS transistor NM4 are sampling current branches, and the first PMOS transistor PM1, the second PMOS transistor PM2, the third PMOS transistor PM3, the fifth NMOS transistor NM5, and the sixth NMOS transistor NM6 form an operational amplifier clamping, forming a negative feedback loop, so that the gate voltages of the second PMOS transistor PM2 and the third PMOS transistor PM3 remain consistent, and the sampling accuracy of the sampling unit is ensured.

[0092] The ninth NMOS NM9 samples the load to obtain a load sampling current, and the load sampling current passes through the ninth NMOS NM9, the eighth NMOS NM8 and the fourth PMOS PM4 to generate bias at the tenth NMOS NM10, and then passes through the twelfth NMOS NM12 to perform level shifting, and the VZ signal output by the source of the twelfth NMOS NM12 controls the dynamic zero point in the control loop.

[0093] The seventh NMOS NM7, the first resistor R1 and the second resistor R2 and the first capacitor C1 perform frequency compensation on the sampling unit, the load sampling current sampled by the ninth NMOS NM9 is compared with a reference current at the sixth PMOS PM6 and the twelfth NMOS NM12 to control the switching state of the seventh NMOS NM7 in the frequency compensation unit, and then whether the first resistor R1 is connected is controlled to ensure the stability of the sampling loop.

[0094] The application further provides a low-dropout linear voltage regulator comprising the dynamic zero point compensation sampling circuit as described above. Figure 2 As shown in the figure, the low-dropout linear voltage regulator comprises an input terminal V IN , an enable terminal EN, a feedback terminal V FB , an output terminal V OUT and a ground terminal GND, further comprising an input capacitor C IN connected between the input terminal V IN and the ground terminal; the enable terminal EN receives an enable signal Enable; an output capacitor C OUT connected between the LDO output terminal V OUT and the ground terminal; a third resistor connected between the output terminal V OUT and the feedback terminal V FB ; and a fourth resistor connected between the feedback terminal V FB and the ground terminal.

[0095] The above technical solution has the following advantages or beneficial effects: the application samples the load current, generates a dynamic zero point to compensate for the output pole under light load and no load, and ensures the phase margin of the loop.

[0096] The above description is only the preferred embodiments of the application, and does not limit the implementation and protection scope of the application; those skilled in the art should realize that any equivalent replacement and obvious changes made according to the content of the specification and the drawings should be included in the protection scope of the application.

Claims

1. A dynamic zero-point compensation sampling circuit applied in a low-dropout linear regulator, characterized in that, The application relates to a low-dropout linear voltage regulator, comprising: a first amplifier for comparing a feedback voltage and a reference voltage and outputting a first comparison signal; a power tube unit for processing an input voltage under the action of the first comparison signal and outputting an output voltage to an output end; a sampling unit comprising a sampling branch for sampling under the action of the first comparison signal and outputting a sampling voltage; and an error amplifier for comparing the output voltage and the sampling voltage and outputting a first control signal; a load current sampling branch for sampling a load under the action of the first control signal to obtain a load sampling current; a second comparison unit for comparing the load sampling current and a reference current and outputting a second comparison signal; a frequency compensation unit for frequency compensating the sampling unit under the action of the second comparison signal. The load current sampling branch comprises: an eighth NMOS tube, the gate of the eighth NMOS tube being connected to a third bias voltage; a ninth NMOS tube, the gate of the ninth NMOS tube being connected to the first control signal, the drain of the ninth NMOS tube being connected to the source of the eighth NMOS tube, and the source of the ninth NMOS tube being connected to a ground end; a fourth PMOS tube, the gate and the drain of the fourth PMOS tube being connected to the drain of the eighth NMOS tube, and the source of the fourth PMOS tube being connected to a power supply end; a fifth PMOS tube, the source of the fifth PMOS tube being connected to the power supply end, and the gate of the fifth PMOS tube being connected to the gate of the fourth PMOS tube; a tenth NMOS tube, the gate and the drain of the tenth NMOS tube being connected to the drain of the fourth PMOS tube; an eleventh NMOS tube, the gate and the drain of the eleventh NMOS tube being connected to the source of the tenth NMOS tube, and the source of the eleventh NMOS tube being connected to the ground end.

2. The dynamic zero-compensated sampling circuit of claim 1, wherein, The positive input end of the first amplifier is connected to the reference voltage, and the negative input end of the first amplifier is connected to the feedback end of the low-dropout linear voltage regulator.

3. The dynamic zero-compensated sampling circuit of claim 1, wherein, The power tube unit comprises: a first NMOS tube, the gate of the first NMOS tube being connected to the output end of the first amplifier, the drain of the first NMOS tube being connected to the power supply end, and the source of the first NMOS tube being connected to the output end of the low-dropout linear voltage regulator; a third NMOS tube, the gate of the third NMOS tube being connected to a first bias voltage, the drain of the third NMOS tube being connected to the source of the first NMOS tube, and the source of the third NMOS tube being connected to the ground end.

4. The dynamic zero-compensated sampling circuit of claim 1, wherein, The sampling branch comprises: a second NMOS tube, the gate of the second NMOS tube being connected to the output end of the first amplifier, the drain of the second NMOS tube being connected to the power supply end, and the sampling voltage being output from the source of the second NMOS tube; a fourth NMOS tube, the gate of the fourth NMOS tube being connected to the first control signal, the drain of the fourth NMOS tube being connected to the source of the second NMOS tube, and the source of the fourth NMOS tube being connected to the ground end.

5. The dynamic zero-compensated sampling circuit of claim 1, wherein, The error amplifier comprises: a first PMOS transistor, a gate of the first PMOS transistor is connected to a second bias voltage, a source of the first PMOS transistor is connected to a power supply terminal; a second PMOS transistor, a gate of the second PMOS transistor is connected to the output voltage, a source of the second PMOS transistor is connected to a drain of the first PMOS transistor; a third PMOS transistor, a gate of the third PMOS transistor is connected to the sampling voltage, a source of the third PMOS transistor is connected to the drain of the first PMOS transistor, the first control signal is output from a drain of the third PMOS transistor; a fifth NMOS transistor, a gate and a drain of the fifth NMOS transistor are connected to a drain of the second PMOS transistor, a source of the fifth NMOS transistor is connected to a ground terminal; a sixth NMOS transistor, a gate of the sixth NMOS transistor is connected to the gate of the fifth NMOS transistor, a drain of the sixth NMOS transistor is connected to the drain of the third PMOS transistor, a source of the sixth NMOS transistor is connected to the ground terminal.

6. The dynamic zero-compensated sampling circuit of claim 1, wherein, The frequency compensation unit comprises: a seventh NMOS transistor, a gate of the seventh NMOS transistor is connected to the second comparison signal, a drain of the seventh NMOS transistor is connected to the first control signal, a source and the drain of the seventh NMOS transistor are connected in parallel to a first resistor; a first capacitor, an anode of the first capacitor is connected to the first resistor through a second resistor, a cathode of the first capacitor is connected to a ground terminal.

7. The dynamic zero-compensated sampling circuit of claim 1, wherein, The second comparison unit comprises: a twelfth NMOS transistor, a gate of the twelfth NMOS transistor is connected to a drain of the tenth NMOS transistor, a drain of the twelfth NMOS transistor is connected to a power supply terminal; a thirteenth NMOS transistor, a gate of the thirteenth NMOS transistor is connected to a fourth bias voltage, a drain of the thirteenth NMOS transistor is connected to a source of the twelfth NMOS transistor, a source of the thirteenth NMOS transistor is connected to a ground terminal; a sixth PMOS transistor, a gate of the sixth PMOS transistor is connected to a gate of the fourth PMOS transistor, a source of the sixth PMOS transistor is connected to the power supply terminal, the second comparison signal is output from a drain of the sixth PMOS transistor; a fourteenth NMOS transistor, a gate of the fourteenth NMOS transistor is connected to a fifth bias voltage, a drain of the fourteenth NMOS transistor is connected to the drain of the sixth PMOS transistor, a source of the fourteenth NMOS transistor is connected to the ground terminal.

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