An amplification circuit applied to MRAM

Abstract

The application provides an amplification circuit applied to MRAM. The amplification circuit comprises a basic amplification circuit and a current difference increasing circuit; the basic amplification circuit comprises two load MOS tubes; the current difference increasing circuit comprises two MOS tubes; the two MOS tubes in the current difference increasing circuit are symmetrically arranged between the two load MOS tubes of the basic amplification circuit, and the signal ports of the two MOS tubes are respectively connected with the ports of the two load MOS tubes, so that the current difference between the two load MOS tubes is increased by the two MOS tubes of the current difference increasing circuit, and the voltage difference between the drain signal ports of the two load MOS tubes is increased.

Description

TECHNICAL FIELD

[0001] The application provides an amplification circuit applied to MRAM and belongs to the technical field of circuits. BACKGROUND

[0002] In the MRAM circuit of the 1T1M architecture, during the read operation, the current of the cell and the current of the reference cell are converted into voltages through the load MOS tube and are sent to the sensitive amplifier for comparison, and the state of the cell is determined according to the result of the sensitive amplifier. In the 1T1M architecture, the difference between the current of the cell and the current of the reference cell is small, and with the decrease of the power supply voltage, the resistance of the load MOS tube cannot be made very large, the voltage difference generated by the difference between the current of the cell and the current of the reference cell is small, and when the sensitive amplifier is mismatched, the sensitive amplifier has a high probability of reading error. SUMMARY

[0003] The application provides an amplification circuit applied to MRAM, which is used to solve the problem of high sensitive amplification reading error rate of the amplification circuit in the existing MRAM, and adopts the technical scheme as follows.

[0004] An amplification circuit applied to MRAM, the amplification circuit comprising a basic amplification circuit and a current difference increasing circuit; the basic amplification circuit comprising two load MOS tubes; the current difference increasing circuit comprising two MOS tubes; the two MOS tubes in the current difference increasing circuit are symmetrically and mirror-imaged arranged between the two load MOS tubes of the basic amplification circuit, and each signal port of the two MOS tubes is electrically connected with each port of the two load MOS tubes, respectively, the current difference between the two load MOS tubes is increased through the two MOS tubes of the current difference increasing circuit, so that the difference between the voltages output by the drain signal ends of the two load MOS tubes is increased.

[0005] Further, the current difference increasing circuit comprises MOS transistor MP1 and MOS transistor MP2; the basic amplification circuit comprises load MOS transistor MP0 and load MOS transistor MP3; the gate of the MOS transistor MP1 is connected with the gate of the load MOS transistor MP0 of the basic amplification circuit; the source of the MOS transistor MP1 is connected with the current signal input end; the drain of the MOS transistor MP1 is connected with the drain of the load MOS transistor MP3 of the basic amplification circuit; the gate of the MOS transistor MP2 is connected with the gate of the load MOS transistor MP3 of the basic amplification circuit; the source of the MOS transistor MP2 is connected with the current signal input end; the drain of the MOS transistor MP2 is connected with the drain of the load MOS transistor MP0 of the basic amplification circuit; the drain of the MOS transistor MP1 is connected with the connection line between the gate of the MOS transistor MP2 and the gate of the load MOS transistor MP3; the drain of the MOS transistor MP2 is connected with the connection line between the gate of the MOS transistor MP0 and the gate of the MOS transistor MP1.

[0006] Further, the MOS transistor MP0 contained in the basic amplification circuit and the MOS transistor MP1 contained in the current difference increasing circuit are mirror-symmetrically distributed.

[0007] Further, the load MOS transistor MP3 contained in the basic amplification circuit and the MOS transistor MP2 contained in the current difference increasing circuit are mirror-symmetrically distributed.

[0008] Further, the W / L ratio of the load MOS transistor MP0 contained in the basic amplification circuit and the MOS transistor MP1 contained in the current difference increasing circuit is 1:N, wherein W represents the width value of the MOS transistor, L represents the length value of the MOS transistor, and N is a constant less than 1.

[0009] Further, the W / L ratio of the load MOS transistor MP3 contained in the basic amplification circuit and the MOS transistor MP2 contained in the current difference increasing circuit is 1:N, wherein W represents the width value of the MOS transistor, L represents the length value of the MOS transistor, and N is a constant less than 1.

[0010] Further, the currents flowing through the MOS transistor MP1 and the MOS transistor MP2 contained in the current difference increasing circuit are respectively I2=N×I1 and I3=N×I4, wherein I2 and I3 respectively represent the currents flowing through the MOS transistor MP1 and the MOS transistor MP2, I1 and I4 respectively represent the currents flowing through the load MOS transistor MP0 and the load MOS transistor MP3 contained in the basic amplification circuit, and N represents a constant value less than 1.

[0011] Further, the current flowing through the MOS transistor MP1 and the MOS transistor MP2 and the current flowing through the load MOS transistor MP0 and the load MOS transistor MP3 satisfy the following relationship:

[0012] I1+I3=I cell

[0013] I2+I4=I ref

[0014] Wherein, I cell represents the current flowing through the cell storing data in the MRAM memory; I ref represents the current flowing through the cell as a reference in the MRAM memory.

[0015] Further, the difference between the current flowing through the load MOS transistor MP0 and the MOS transistor MP1 is obtained by the following formula:

[0016] I1-I4=(I cell -I ref ) / (1-N) and has |(I cell -I ref ) / (1-N)|> |I cell -I ref |

[0017] Wherein, I ref represents the current flowing through the cell as a reference in the MRAM memory; I cell represents the current flowing through the cell storing data in the MRAM memory.

[0018] Further, the voltage signal QC outputted by the drain signal end of the load MOS transistor MP0 contained in the basic amplification circuit and the voltage signal QR outputted by the drain signal end of the load MOS transistor MP3 contained in the basic amplification circuit satisfy the following formula:

[0019] U=|(I cell -I ref ) / (1-N)|×R

[0020] Wherein, U represents the voltage signal QC outputted by the drain signal end of the load MOS transistor MP0 contained in the basic amplification circuit and the voltage signal QR outputted by the drain signal end of the load MOS transistor MP3 contained in the basic amplification circuit; R represents the resistance value of the load MOS transistor MP0 and the load MOS transistor MP3 contained in the basic amplification circuit.

[0021] The present application has the following advantages:

[0022] The application provides an amplification circuit applied to MRAM, which increases the current difference between a load MOS tube MP0 and a load MOS tube MP3 through the action of MP1 and MP2, so as to increase the voltage difference between the output voltage signals QC and QR of the load MOS tube MP0 and the load MOS tube MP3, and when the increased voltage difference is input into the second-stage amplifier of the amplification circuit, the sensitivity reading of the amplification circuit can be improved, and the error rate of the sensitivity reading can be effectively reduced. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 The circuit structure schematic diagram of the basic amplification circuit is shown in the figure.

[0024] Figure 2 The circuit structure schematic diagram of the amplification circuit applied to MRAM is shown in the figure. DETAILED DESCRIPTION

[0025] The preferred embodiments of the application are described below in combination with the drawings, and it should be understood that the preferred embodiments described herein are only used for describing and explaining the application, and are not used for limiting the application.

[0026] The application provides an amplification circuit applied to MRAM, which increases the current difference between a load MOS tube MP0 and a load MOS tube MP3 through the action of MP1 and MP2, so as to increase the voltage difference between the output voltage signals QC and QR of the load MOS tube MP0 and the load MOS tube MP3, and when the increased voltage difference is input into the second-stage amplifier of the amplification circuit, the sensitivity reading of the amplification circuit can be improved, and the error rate of the sensitivity reading can be effectively reduced. Figure 2 As shown in the figure, the amplification circuit comprises a basic amplification circuit and a current difference increasing circuit; the basic amplification circuit comprises two load MOS tubes; the current difference increasing circuit comprises two MOS tubes; the two MOS tubes in the current difference increasing circuit are symmetrically and mirror-imaged arranged between the two load MOS tubes of the basic amplification circuit, and the signal ports of the two MOS tubes are respectively connected with the ports of the two load MOS tubes in circuit, so that the current difference between the two load MOS tubes is increased through the two MOS tubes of the current difference increasing circuit, and the voltage difference between the drain signal ends of the two load MOS tubes is increased.

[0027] The current difference increasing circuit comprises MOS tubes MP1 and MP2; the basic amplification circuit comprises load MOS tubes MP0 and MP3; the gate of the MOS tube MP1 is connected with the gate of the load MOS tube MP0 of the basic amplification circuit; the source of the MOS tube MP1 is connected with the current signal input end; the drain of the MOS tube MP1 is connected with the drain of the load MOS tube MP3 of the basic amplification circuit; the gate of the MOS tube MP2 is connected with the gate of the load MOS tube MP3 of the basic amplification circuit; the source of the MOS tube MP2 is connected with the current signal input end; the drain of the MOS tube MP2 is connected with the drain of the load MOS tube MP0 of the basic amplification circuit; the drain of the MOS tube MP1 is connected with the connecting line between the gate of the MOS tube MP2 and the gate of the load MOS tube MP3; the drain of the MOS tube MP2 is connected with the connecting line between the gate of the MOS tube MP0 and the gate of the MOS tube MP1.

[0028] As shown in FIG. 1, the MOS tube MP0 contained in the basic amplification circuit and the MOS tube MP1 contained in the current difference increasing circuit are mirror-symmetrically distributed, and the load MOS tube MP3 contained in the basic amplification circuit and the MOS tube MP2 contained in the current difference increasing circuit are mirror-symmetrically distributed. Figure 2 As shown in FIG. 1, the MOS tube MP0 contained in the basic amplification circuit and the MOS tube MP1 contained in the current difference increasing circuit are mirror-symmetrically distributed, and the load MOS tube MP3 contained in the basic amplification circuit and the MOS tube MP2 contained in the current difference increasing circuit are mirror-symmetrically distributed.

[0029] In the circuit setting of the amplification circuit, the W / L ratio of the load MOS tube MP0 contained in the basic amplification circuit and the MOS tube MP1 contained in the current difference increasing circuit is set as 1:N, wherein W represents the width value of the MOS tube, L represents the length value of the MOS tube, and N is a constant less than 1. The W / L ratio of the load MOS tube MP3 contained in the basic amplification circuit and the MOS tube MP2 contained in the current difference increasing circuit is set as 1:N, wherein W represents the width value of the MOS tube, L represents the length value of the MOS tube, and N is a constant less than 1.

[0030] In the case that the W / L ratio of the load MOS tube MP0 and the MOS tube MP1 is 1:N, and the W / L ratio of the MOS tube MP2 is 1:N, the currents flowing through the MOS tube MP1 and the MOS tube MP2 contained in the current difference increasing circuit of the load MOS tube MP3 are I2=N×I1 and I3=N×I4, respectively, wherein I2 and I3 represent the currents flowing through the MOS tube MP1 and the MOS tube MP2, respectively; I1 and I4 represent the currents flowing through the load MOS tube MP0 and the load MOS tube MP3 contained in the basic amplification circuit, respectively; and N represents a constant value less than 1.

[0031] At this time, the current flowing through the MOS transistor MP1 and the MOS transistor MP2 and the current flowing through the load MOS transistor MP0 and the load MOS transistor MP3 satisfy the following relationship:

[0032] I1+I3=I cell

[0033] I2+I4=I ref

[0034] Wherein, I cell represents the current flowing through the cell storing data in the MRAM memory; I ref represents the current flowing through the cell as a reference in the MRAM memory.

[0035] The current difference between the load MOS transistor MP0 and the MOS transistor MP1 can be calculated by the current flowing through the MOS transistor MP1 and the MOS transistor MP2 and the current flowing through the load MOS transistor MP0 and the load MOS transistor MP3. Specifically, the current difference between the load MOS transistor MP0 and the MOS transistor MP1 is obtained by the following formula:

[0036] I1-I4=(I cell -I ref ) / (1-N) and |(I cell -I ref ) / (1-N)|> |I cell -I ref |

[0037] Wherein, I ref represents the current flowing through the cell as a reference in the MRAM memory; I cell represents the current flowing through the cell storing data in the MRAM memory.

[0038] When the current difference between the load MOS transistor MP0 and the MOS transistor MP1 is obtained by calculation, the voltage difference between the voltage signal QC output by the drain signal end of the load MOS transistor MP0 included in the basic amplification circuit and the voltage signal QR output by the drain signal end of the load MOS transistor MP3 included in the basic amplification circuit can be calculated by the current difference between the load MOS transistor MP0 and the MOS transistor MP1. Specifically, the voltage difference between the voltage signal QC output by the drain signal end of the load MOS transistor MP0 included in the basic amplification circuit and the voltage signal QR output by the drain signal end of the load MOS transistor MP3 included in the basic amplification circuit is obtained by the following formula:

[0039] U=|(I cell -Iref ) / (1-N)|xR

[0040] Wherein, U represents the voltage difference between the voltage signal QC outputted by the drain signal end of the load MOS tube MP0 contained in the basic amplification circuit and the voltage signal QR outputted by the drain signal end of the load MOS tube MP3 contained in the basic amplification circuit; R represents the resistance value of the load MOS tube MP0 and the load MOS tube MP3 contained in the basic amplification circuit.

[0041] The working principle of the above technical solution is as follows: Figure 1 As shown in the figure, the voltage difference between the output voltage signals QC and QR of the load MOS tube MP0 and the load MOS tube MP3 of the basic amplification circuit is amplified by the second-stage amplifier cmp and then outputted as a voltage reading via the output end OUT of the second-stage amplifier cmp. However, since the amplification circuit applied in the MRAM is a sensitive amplification circuit, the voltage difference between QC and QR is very small. In the case that the voltage difference between QC and QR is small, even if the voltage difference is amplified by the second-stage amplifier cmp, the amplified voltage difference signal is still small due to the limitation of the amplified signal, which may cause the problem of detection reading error.

[0042] Therefore, by electrically connecting the corresponding MOS tubes MP1 and MP2 (i.e. current difference increasing circuit) between the load MOS tube MP0 and the load MOS tube MP3, the current difference between the load MOS tube MP0 and the load MOS tube MP3 is amplified, and the voltage difference between the output voltage signals QC and QR of the load MOS tube MP0 and the load MOS tube MP3 is proportionally increased. When the proportionally increased voltage difference between the output voltage signals QC and QR of the load MOS tube MP0 and the load MOS tube MP3 is amplified again by the second-stage amplifier cmp, the accuracy of the reading of the amplified voltage difference signal can be effectively improved.

[0043] In the operation process of the amplification circuit applied in the MRAM proposed in the embodiment, as shown in the figure, Figure 2 The current of the load MOS tube MP0 is I1, the current of the load MOS tube MP3 is I4, the W / L ratio of the load MOS tube MP0 and the MOS tube MP1 is set to 1:N; the W / L ratio of the load MOS tube MP3 and the MOS tube MP2 is set to 1:N; the current I3 flowing through the MOS tube MP2 is N×I4; the current I2 flowing through the MOS tube MP1 is N×I1; I1+I3=I cell , I cell is the current I2+I4 flowing through the marinarray ref , I ref is the current flowing through the refcell. According to the above formula, it can be calculated that:

[0044] I1=(N×I ref -I cell ) / (N×N-1)

[0045] I4-(N×I cell -I rell ) / (N×N-1)

[0046] I1-I4=(I cell -I ref ) / (1-N)

[0047] Since the value of N is set to be less than 1, therefore, Figure 2 In the context I1-I2=(I cell -I rell ) / (1-N)>|I cell -I ref |; Through comparison Figure 1 The voltage difference between the output voltage signals QC and QR of the load MOSFET MP0 and the load MOSFET MP3 is (I cell -I ref )×R; R is the resistance of MP0 and MP3. Figure 2 The voltage difference between the output voltage signals QC and QR of the load MOSFET MP0 and the load MOSFET MP3 is |(I cell -I ref ) / (1-N)|×R; R is the resistance of MP0 and MP3. Clearly, Figure 1 The voltage difference between the output voltage signals QC and QR of the load MOSFETs MP0 and MP3 in the basic amplifier circuit without the added current difference increase circuit is significantly smaller than that between the output voltage signals QC and QR of the load MOSFETs MP0 and MP3 with the added current difference increase circuit. Through the above settings and calculations, the current difference between the load MOSFETs MP0 and MP3 can be increased without increasing the resistance R of the load MOSFETs MP0 and MP3, thereby increasing the voltage difference between the output voltage signals QC and QR of the load MOSFETs MP0 and MP3.

[0048] The application has the advantages that the amplification circuit applied to the MRAM increases the current difference between the load MOS MP0 and the load MOS MP3 through the MP1 and MP2, so as to increase the voltage difference between the output voltage signals QC and QR between the load MOS MP0 and the load MOS MP3, and when the increased voltage difference is input to the second amplifier of the amplification circuit, the sensitivity reading of the amplification circuit is improved, and the error rate of the sensitivity reading is effectively reduced. Meanwhile, the resistance R of the original load MOS MP0 and MP3 in the basic amplification circuit is not required to be changed, the change of the basic amplification circuit itself is completely eliminated, the interference and influence on the performance of the basic amplification circuit are greatly reduced, and the performance stability of the basic amplification circuit is effectively ensured.

[0049] Obviously, various modifications and changes can be made to the present application by those skilled in the art without departing from the spirit and scope of the present application. Thus, if these modifications and changes are within the scope of the present application and its equivalents, the present application is intended to include these modifications and changes.

Claims

1. An amplifier circuit used in MRAM, characterized in that, The amplifier circuit includes a basic amplifier circuit and a current difference amplification circuit; The basic amplifier circuit includes a load MOSFET MP0 and a load MOSFET MP3; The current difference increasing circuit includes MOSFET MP1 and MOSFET MP2; The gate of the MOS transistor MP1 is connected to the gate of the load MOS transistor MP0 of the basic amplifier circuit; the source of the MOS transistor MP1 is connected to the current signal input terminal; and the drain of the MOS transistor MP1 is connected to the drain of the load MOS transistor MP3 of the basic amplifier circuit. The gate of the MOS transistor MP2 is connected to the gate of the load MOS transistor MP3 of the basic amplifier circuit; the source of the MOS transistor MP2 is connected to the current signal input terminal; and the drain of the MOS transistor MP2 is connected to the drain of the load MOS transistor MP0 of the basic amplifier circuit. The drain signal output terminal of the MOS transistor MP1 is connected to the connection line between the gate of the MOS transistor MP2 and the gate of the load MOS transistor MP3; the drain signal output terminal of the MOS transistor MP2 is connected to the connection line between the gate of the MOS transistor MP0 and the gate of the MOS transistor MP1. The current difference increasing circuit increases the current difference between the load MOSFETs MP0 and MP3 by using MOSFETs MP1 and MP2, thereby increasing the voltage difference between the drain signal terminals of the load MOSFETs MP0 and MP3.

2. The amplifier circuit according to claim 1, characterized in that, The MOS transistor MP0 in the basic amplifier circuit and the MOS transistor MP1 in the current difference increasing circuit are mirror images of each other.

3. The amplifier circuit according to claim 1, characterized in that, The load MOSFET MP3 in the basic amplifier circuit and the MOSFET MP2 in the current difference increasing circuit are mirror images of each other.

4. The amplifier circuit according to claim 1, characterized in that, The load MOSFET MP0 included in the basic amplifier circuit and the MOSFET MP1 included in the current difference increasing circuit both have a W / L ratio of 1:N, where W represents the width value of the MOSFET, L represents the length value of the MOSFET, and N is a constant less than 1.

5. The amplifier circuit according to claim 1, characterized in that, The W / L ratio of the load MOSFET MP3 in the basic amplifier circuit and the MOSFET MP2 in the current difference increasing circuit is 1:N, where W represents the width of the MOSFET, L represents the length of the MOSFET, and N is a constant less than 1.

6. The amplifier circuit according to claim 1, characterized in that, The currents flowing through the MOS transistors MP1 and MP2 in the current difference increasing circuit are: I2 = N × I1; I3 = N × I4; where I2 and I3 represent the currents flowing through the MOS transistors MP1 and MP2, respectively; I1 and I4 represent the currents flowing through the load MOS transistors MP0 and MP3 in the basic amplifier circuit, respectively; and N is a constant value and is less than 1.

7. The amplifier circuit according to claim 6, characterized in that, The currents flowing through MOSFETs MP1 and MP2 and the currents flowing through load MOSFETs MP0 and MP3 satisfy the following relationship: I1+I3=I cell ; I2+I4=I ref ; Among them, I cell This represents the current flowing through the cell storing data in the MRAM memory; I ref This represents the current flowing through the cell that serves as a reference in the MRAM memory.

8. The amplifier circuit according to claim 6, characterized in that, The difference between the currents on the load MOSFET MP0 and the MOSFET MP1 is obtained by the following formula: I1-I4=(I cell -I ref ) / (1-N)and have|(I cell -I ref ) / (1-N)|>|I cell -I ref |; Among them, I ref This represents the current flowing through the reference cell in the MRAM memory; I cell This represents the current flowing through the cell storing data in the MRAM memory.

9. The amplifier circuit according to claim 1, characterized in that, The voltage difference between the voltage signal QC output from the drain signal terminal of the load MOSFET MP0 included in the basic amplifier circuit and the voltage signal QR output from the drain signal terminal of the load MOSFET MP3 included in the basic amplifier circuit is obtained by the following formula: U=|(I cell -I ref ) / (1-N)|×R; Wherein, U represents the voltage difference between the voltage signal QC output from the drain signal terminal of the load MOS transistor MP0 included in the basic amplifier circuit and the voltage signal QR output from the drain signal terminal of the load MOS transistor MP3 included in the basic amplifier circuit; R represents the resistance values ​​of the load MOS transistors MP0 and MP3 included in the basic amplifier circuit.

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