High-precision timing generation circuit and chip

Abstract

This invention discloses a high-precision timing generation circuit and chip. The circuit includes a current source bias circuit and a delay circuit. The current source bias circuit generates a bias current and a clamping voltage. The delay circuit receives a clock signal as input and delays the clock signal by charging and discharging a capacitor using the bias current, controlling the flip level of the output delayed signal to be the clamping voltage. Using this invention, a precise clock signal can be generated, satisfying the precise control of the internal read timing of ultra-high-speed flash memory.

Description

Technical Field

[0001] This invention relates to the field of circuits, and more specifically to a high-precision timing generation circuit and chip. Background Technology

[0002] In recent years, the application market has seen an increasing demand for ultra-high-speed embedded flash memory (eFlash), which typically requires flash memory to achieve high-speed read speeds of 7ns to 10ns. How to achieve precise control of the internal read timing has become the key to designing ultra-high-speed flash memory.

[0003] The flash memory read process is mainly divided into two parts: bit line pre-charging and bit line differentiation, which are usually controlled by internal timing. The read speed of ultra-high-speed flash memory needs to be within 10ns. If the timing deviation is large, it will directly lead to the failure of the read operation. Therefore, high-precision timing control is a necessary requirement for realizing ultra-high-speed flash memory. However, the existing RC charge and discharge timing generation circuits cannot meet the requirements of high-precision timing control. Summary of the Invention

[0004] This invention provides a high-precision timing generation circuit and chip to generate accurate clock signals, thereby achieving precise control over the internal read timing of ultra-high-speed flash memory.

[0005] Therefore, the embodiments of the present invention provide the following technical solutions:

[0006] On one hand, embodiments of the present invention provide a high-precision timing generation circuit, the circuit comprising: a current source bias circuit and a delay circuit;

[0007] The current source bias circuit is used to generate bias current and clamping voltage;

[0008] The delay circuit is used to input a clock signal, delay the clock signal by charging and discharging the capacitor through the bias current, and control the flip level of the output delayed signal to be the clamping voltage.

[0009] Optionally, the current source biasing circuit includes:

[0010] A bias current source is used to generate the bias current;

[0011] A clamping circuit is used to generate the clamping voltage based on the bias current.

[0012] Optionally, the clamping circuit includes:

[0013] A threshold voltage generation module is used to generate a threshold voltage based on the bias current;

[0014] A clamping voltage generation module is used to generate a clamping voltage that is the same as the threshold voltage.

[0015] Optionally, the delay circuit includes: a mirror current generation module, a charge / discharge control module, a capacitor, and a guiding module;

[0016] The mirror current generation module is used to generate a mirror current based on the bias current;

[0017] The charge / discharge control module is used to charge and discharge the capacitor according to the clock signal and the mirror current;

[0018] The guiding module is used to output the voltage on the capacitor as the output signal and control the flip level of the output signal to be the clamping voltage.

[0019] Optionally, the charge / discharge control module includes:

[0020] The system includes a falling edge delay unit, a first transmission unit, and a second transmission unit connected to the falling edge delay unit and the first transmission unit, respectively; the connection point between the first transmission unit and the second transmission unit serves as the output terminal of the charge / discharge control module.

[0021] The falling edge delay unit is used to delay the falling edge of the clock signal and output a delayed signal;

[0022] The first transmission unit and the second transmission unit are configured to generate control signals for controlling the charging and discharging of the capacitor based on the clock signal and the delay signal.

[0023] Optionally, the first transmission unit is a PMOS transistor, and the second transmission unit is an NMOS transistor.

[0024] Optionally, the threshold voltage generation module includes: a first NMOS transistor; the drain of the first NMOS transistor is connected to the bias current source, the source of the first NMOS transistor is grounded, and the gate of the first NMOS transistor is connected to the clamping voltage generation module.

[0025] Optionally, the clamping voltage generation module includes: a second NMOS transistor and a resistor; the resistor is connected between the gate of the first NMOS transistor and ground; the gate of the second NMOS transistor is connected to the drain of the first NMOS transistor, the source of the second NMOS transistor is connected to the gate of the first NMOS transistor, and the drain of the second NMOS transistor is connected to the bias current source.

[0026] Optionally, the guiding module includes: a third NMOS transistor and a first PMOS transistor; the source of the first PMOS transistor is connected to the mirror current generation module, the gate of the third NMOS transistor is connected to the gate of the first PMOS transistor and connected to the capacitor, the source of the third NMOS transistor is grounded, the drain of the third NMOS transistor is connected to the drain of the first PMOS transistor, and the connection node serves as the output terminal of the guiding module; the third NMOS transistor is matched with the first NMOS transistor.

[0027] Optionally, the delay circuit further includes an inverter, the input terminal of which is connected to the output terminal of the guiding module, and the output terminal of which serves as the output terminal of the delay circuit to output a delay signal.

[0028] On the other hand, embodiments of the present invention also provide a chip, including the high-precision timing generation circuit described above.

[0029] The high-precision timing generation circuit and chip provided in this invention utilize a current source bias circuit to generate bias current and clamping voltage. By delaying the input clock signal through capacitor charging and discharging, the switching level of the output signal is controlled to be the clamping voltage. This ensures that the generated delayed signal is independent of the power supply voltage, preventing the accumulated charge of parasitic capacitors within the circuit from affecting the output signal timing. This effectively reduces timing deviations and improves convergence under different voltage, temperature, and process angle deviations. Furthermore, the high-precision timing generation circuit provided in this invention can be combined with a charge elimination method to eliminate the non-ideal charging stage dominated by accumulated charge, ensuring timing accuracy. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of a traditional timing generation circuit;

[0031] Figure 2 yes Figure 1 The diagram shows the signal timing sequence in the timing generation circuit.

[0032] Figure 3A This is a schematic diagram illustrating the effect of accumulated charge on charging in traditional sequential circuits.

[0033] Figure 3B This is a schematic diagram illustrating another effect of accumulated charge on charging in traditional sequential circuits;

[0034] Figure 4 This is a schematic block diagram of the high-precision timing generation circuit provided in the embodiment of the present invention;

[0035] Figure 5 This is a schematic diagram of a high-precision timing generation circuit provided in an embodiment of the present invention;

[0036] Figure 6 This is a schematic diagram of a specific application structure of the high-precision timing generation circuit provided in an embodiment of the present invention;

[0037] Figure 7 This is a schematic diagram of the charging timing based on charge elimination in the high-precision timing generation circuit of this invention. Detailed Implementation

[0038] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0039] The following is a brief explanation of traditional timing generation circuits.

[0040] Traditional timing generation circuit structures, such as Figure 1 As shown, the circuit includes a current source bias circuit and a delay circuit. The current source bias circuit provides a precise current source Iref, which is typically a reference current generated by a bandgap reference. In the delay circuit, the mirrored current source P1 charges capacitor C0; CLK is an externally input clock signal. When CLK is low, PMOS transistor P0 is turned on, NMOS transistor N0 is turned off, and the mirrored current source P1 charges capacitor C0. When the voltage Vc on the upper plate of capacitor C0 reaches 1 / 2 × Vdd, the output signal VO flips from low to high. The timing waveform is shown below. Figure 2 As shown. The delay td between the falling edge of the clock signal CLK and the rising edge of the output signal VO is determined by the charging current I0 of the mirror current source P1, the capacitor C0, and the voltage Vc of the upper plate of the capacitor C0, i.e., td = vdd × C0 / 2I0, where vdd is the operating voltage of the delay circuit, which will be referred to as the power supply voltage below.

[0041] Figure 1The traditional timing generation circuit shown works by charging a capacitor with a reference current, thus creating a delay at the edge of the input clock signal. The accuracy of this delay determines the accuracy of the generated timing (i.e., the output signal VO). Traditional timing generation circuits cannot meet the requirements of high-precision timing, mainly for the following two reasons. First, as the previous analysis shows, the timing generated by a traditional timing generation circuit is determined by the voltage flip threshold, the capacitor value, and the charging current. The capacitor value is a fixed value, the charging current is the reference current, and the voltage flip threshold is 1 / 2 × vdd. Therefore, the generated timing is related to the power supply voltage vdd; changes in the power supply voltage vdd will cause timing deviations. Second, when the timing circuit is in standby mode, the input clock signal CLK is high. At this time, PMOS transistor P0 is off, NMOS transistor N0 is on, and the voltage Vc on the upper plate of capacitor C0 is low. The current mirror P1 is on, continuously charging the parasitic capacitance of node Vs until the level stabilizes. When the falling edge of CLK arrives, NMOS transistor N0 is turned off, while PMOS transistor P0 is turned on. At this time, the charge accumulated at node Vs will form a large instantaneous current to charge capacitor C0. This current is much greater than the reference current Iref provided by the current source, so the potential of the upper plate of capacitor C0 will be rapidly increased during this stage. After the accumulated charge is completely discharged, the charging current is equal to the reference current provided by the current source P1.

[0042] The impact of accumulated charge on timing has two main aspects, such as Figure 3A As shown, stage t0 is the charging stage dominated by accumulated charge. When the accumulated charge is completely discharged, if Vc < 1 / 2 × Vdd, charging continues by the reference current. t1 is the charging stage of the reference current source. Since the instantaneous discharge current is much larger than the reference current, the charging slope of stage t0 is much greater than that of stage t1, resulting in an actual delay that is less than the theoretical value. Figure 3B As shown, if the instantaneous current generated by the discharge of accumulated charge has already caused Vc to reach 1 / 2×vdd in the t0 stage, it will cause a false flip and generate an incorrect timing sequence.

[0043] As can be seen from the above analysis, accumulated charge can not only cause timing deviations, but may even cause incorrect timing.

[0044] To address the aforementioned issues, this invention provides a high-precision timing generation circuit and chip. It utilizes a current source bias circuit to generate bias current and clamping voltage. By charging and discharging a capacitor to delay the input clock signal, the flip-flop level of the output signal is controlled to be the clamping voltage. This ensures that the generated delayed signal is independent of the power supply voltage, preventing the accumulated charge of parasitic capacitors within the circuit from affecting the timing of the output signal.

[0045] like Figure 4The diagram shown is a schematic block diagram of the high-precision timing generation circuit provided in an embodiment of the present invention.

[0046] The high-precision timing generation circuit 400 includes: a current source bias circuit 401 and a delay circuit 402, wherein:

[0047] The current source bias circuit 401 is used to generate bias current and clamping voltage;

[0048] The delay circuit 402 is used to delay the input clock signal by charging and discharging the capacitor, and to control the flip level of the output signal to be the clamping voltage.

[0049] like Figure 5 As shown, in one non-limiting embodiment, the current source bias circuit 401 may include: a bias current source 411 and a clamping circuit 412. The bias current source 411 is used to generate the bias current; the clamping circuit 412 is used to generate the clamping voltage based on the bias current.

[0050] In this embodiment, the delay circuit 402 includes: a mirror current generation module 421, a charge / discharge control module 422, a capacitor C0, and a guiding module 423. Wherein:

[0051] The mirror current generation module 421 is used to generate a mirror current according to the bias current;

[0052] The charge / discharge control module 422 is used to charge and discharge the capacitor according to the clock signal and the mirror current;

[0053] The guiding module 423 is used to output the voltage Vc on capacitor C0 as the output signal, and control the flip level of the output signal to be the clamping voltage.

[0054] In one specific application example, the clamping circuit 412 may include the following modules:

[0055] A threshold voltage generation module is used to generate a threshold voltage based on the bias current;

[0056] A clamping voltage generation module is used to generate a clamping voltage that is the same as the threshold voltage.

[0057] The charge / discharge control module 422 may include the following units: a falling edge delay unit, a first transmission unit, and a second transmission unit connected to the falling edge delay unit and the first transmission unit respectively; the connection point between the first transmission unit and the second transmission unit serves as the output terminal of the charge / discharge control module. Wherein:

[0058] The falling edge delay unit is used to delay the falling edge of the clock signal and output a delayed signal.

[0059] The first transmission unit and the second transmission unit are used to generate control signals for controlling the charging and discharging of the capacitor based on the clock signal and the delay signal. For example, the first transmission unit can be a PMOS transistor, and the second transmission unit can be an NMOS transistor.

[0060] Reference Figure 6 , Figure 6 This is a schematic diagram of a specific application structure of the high-precision timing generation circuit provided in an embodiment of the present invention.

[0061] In this embodiment, Figure 5 The clamping circuit 412 includes a threshold voltage generation module and a clamping voltage generation module. The threshold voltage generation module is implemented using a first NMOS transistor MN0, and the clamping voltage generation module is implemented using a second NMOS transistor MN1 and a resistor R.

[0062] In this embodiment, Figure 5 The bias current source 411 includes a fourth NMOS transistor MN3, a second PMOS transistor MP1, and a third PMOS transistor MP2.

[0063] like Figure 6 As shown, the gate of the third PMOS transistor MP2 is biased by a voltage pbias, the source of the third PMOS transistor MP2 is connected to the operating power supply vdd, the drain of the third PMOS transistor MP2 is connected to the drain of the fourth NMOS transistor MN3, the gate of the fourth NMOS transistor MN3 is biased by a voltage v1p2, and the source of the fourth NMOS transistor NM3 is connected to the drain of the first NMOS transistor MN0. The gate and drain of the second PMOS transistor MP1 are connected together and connected to the drain of the second NMOS transistor MN1. The source and gate of the second PMOS transistor MP1 are connected to the delay circuit 402.

[0064] It should be noted that, Figure 6 The operating voltage of the fourth NMOS transistor MN3 shown is vdd12. The value of vdd12 can be the same as or different from the operating power supply voltage vdd. Additionally... Figure 6 The bias current source shown, consisting of the fourth NMOS transistor MN3, the second PMOS transistor MP1, and the third PMOS transistor MP2, is merely an illustrative example. In practical applications, other structures are possible, and this embodiment of the invention does not limit the specific structure.

[0065] Continue to refer to Figure 6In this embodiment, the drain of the first NMOS transistor MN0 is connected to the source of the fourth NMOS transistor NM3. The source of the first NMOS transistor MN0 is grounded, and the gate of the first NMOS transistor MN0 is connected to a resistor R and the source of the second NMOS transistor. The connection node is denoted as Va. The resistor R is connected between the gate of the first NMOS transistor MN0 and ground. The gate of the second NMOS transistor MN1 is connected to the source of the fourth NMOS transistor MN3. The connection node is denoted as Vb.

[0066] Depend on Figure 6 It can be seen that the voltage value of node Va is the gate-source voltage of the first NMOS transistor MN0. When a suitable bias current I0 is set and the width-to-length ratio of the first NMOS transistor MN0 is set to the inverse ratio, the voltage of node Va will be approximately equal to the threshold voltage of the first NMOS transistor MN0. The second NMOS transistor MN1 clamps the potential of node Va to the threshold voltage value of the first NMOS transistor MN0 through negative feedback. The bias current I0 generated by the current bias circuit 401 flowing through MP1 can be expressed as I0 = Vt / R, where Vt is the threshold voltage of the first NMOS transistor MN0.

[0067] Figure 6 In the illustrated embodiment, Figure 5 The mirror current generation module 421 shown is implemented by the fourth PMOS transistor MP3, which generates a mirror current I1. The relationship between I1 and the bias current I0 generated by the current source bias circuit 401 can be expressed as I1 = m * I0, where m is a proportionality coefficient, which is determined by the size of the fourth PMOS transistor MP3 and the second PMOS transistor MP1.

[0068] Continue to refer to Figure 6 , Figure 5 The first transmission unit and the second transmission unit in the charge and discharge control module 422 shown are respectively implemented by the fifth PMOS transistor MP4 and the fifth NMOS transistor MN4. The source of the fifth PMOS transistor MP4 is connected to the drain of the fourth PMOS transistor MP3, the drain of the fifth PMOS transistor MP4 is connected to the drain of the fifth NMOS transistor MN4, and the source of the fifth NMOS transistor MN4 is grounded.

[0069] The gate of the fifth PMOS transistor MP4 receives the clock signal CLK. After being delayed by the falling edge delay unit 4221, the clock signal CLK is used to obtain the delayed clock signal CLKD, which is then input to the gate of the fifth NMOS transistor MN4.

[0070] Figure 6 In the illustrated embodiment, Figure 5The guiding module 423 shown includes a third NMOS transistor MN2 and a first PMOS transistor MP0. The source of the first PMOS transistor MP0 is connected to the source of a fourth PMOS transistor MP3. The gate of the third NMOS transistor MN2 is connected to the gate of the first PMOS transistor MP0 and to the upper plate of capacitor C0. The voltage across the upper plate of capacitor C0 is denoted as Vc. The source of the third NMOS transistor MN2 is grounded, and the drain of the third NMOS transistor MN2 is connected to the drain of the first PMOS transistor MP0. The connection node serves as the output terminal of the guiding module 423.

[0071] Reference Figure 6 When the clock signal CLK is low, the mirror current I1 charges the capacitor C0. The switching level of Vc is designed to be the threshold voltage Vt' of the third NMOS transistor MN2. Therefore, the resulting delay td = Vt'*C0 / I1 = Vt'*C0*R / (m*Vt). Here, "*" indicates multiplication.

[0072] When the first NMOS transistor MN0 and the third NMOS transistor MN2 are perfectly matched, Vt = Vt', then td = C0*R / m.

[0073] As can be seen from the above formula, the delay td is only related to the capacitor C0, the resistor R, and the current mirror scaling factor m. By configuring C0, the resistor R, and the current according to the design specifications, a timing signal independent of the power supply voltage can be obtained.

[0074] In practical applications, the resistor R can be a polysilicon resistor with a very small temperature coefficient, the temperature coefficient of the capacitor C0 can be ignored, and m has no temperature coefficient. Therefore, temperature changes will not have a significant impact on the timing signal. Therefore, in this embodiment of the invention, the third NMOS transistor MN2 and the first NMOS transistor MN0 are two matched NMOS transistors. "Matched" means that the two NMOS transistors have the same device type and aspect ratio.

[0075] Continue to refer to Figure 6 In this invention, the current source bias circuit 401 operates in the vdd voltage domain, the delay circuit operates in the vdd12 voltage domain, and the third NMOS transistor MN2 needs to be matched with the first NMOS transistor MN0. In this invention, both can be selected as the same type of vdd12 voltage domain device. Therefore, it is necessary to apply a bias voltage v1p2 to the gate of the fourth NMOS transistor MN3 to clamp the voltage of node Vb in the vdd12 domain.

[0076] Of course, if the voltages vdd and vdd12 are the same, clamping is not required, which means the fourth NMOS transistor MN3 can be omitted.

[0077] It should be noted that the voltages vdd, vdd12, v1p2, and pbias mentioned above can be determined based on the actual operating and performance parameters of the selected device, and this embodiment of the invention does not limit this.

[0078] The high-precision timing generation circuit provided in this invention utilizes a current source bias circuit to generate bias current and clamping voltage. By delaying the input clock signal through capacitor charging and discharging, the switching level of the output signal is controlled to be the clamping voltage. This ensures that the generated delayed signal is independent of the power supply voltage, avoiding the influence of accumulated charge from parasitic capacitors on the output signal timing. Therefore, this invention utilizes threshold compensation of the MOSFET to make the output signal timing independent of the power supply voltage, thereby improving the convergence of the output signal under voltage, temperature, and process angle deviations.

[0079] like Figure 6 As shown, in the high-precision timing generation circuit of the present invention, the delay circuit 402 may further include an inverter 424. The input terminal of the inverter 424 is connected to the output terminal of the guiding module, and the output terminal of the inverter 424 serves as the output terminal of the delay circuit, outputting a delay signal. Of course, the inverter 424 can also be independent of the delay circuit 402, and this embodiment of the present invention does not limit this.

[0080] The high-precision timing generation circuit provided in this embodiment of the invention can also be used in conjunction with a charge elimination method to discharge accumulated charge through a ground path, thereby eliminating the non-ideal charging stage dominated by accumulated charge, avoiding timing deviations and false flips caused by this stage, and ensuring the accuracy and convergence of the timing.

[0081] The charging timing using charge elimination in the high-precision timing generation circuit of this invention is as follows: Figure 7 As shown below, in conjunction with Figure 6 and Figure 7 The principles behind it will be explained in detail.

[0082] when Figure 6 When the high-precision timing generation circuit shown is in standby mode, the clock signal CLK is high, the fifth PMOS transistor MP4 is turned off, and due to the parasitic capacitance of node Vs, charge accumulates at node Vs. At this time, the delayed clock signal CLKD is in phase with the clock signal CLK and remains high. The fifth NMOS transistor MN4 is turned on, pulling the voltage Vc on the upper plate of capacitor C0 to a low level.

[0083] When the falling edge of the clock signal CLK arrives, the delayed clock signal CLKD will not immediately become low due to the falling edge delay unit. Instead, the level will change after a delay of ts.

[0084] During the ts phase, since the clock signal CLK is low and the delayed clock signal CLKD is high, the fifth PMOS transistor MP4 and the fifth NMOS transistor MN4 are turned on simultaneously, forming a path to ground. The charge accumulated at node Vs is completely discharged to ground during this phase.

[0085] When the delayed clock signal CLKD goes low, the fifth NMOS transistor MN4 is turned off. At this time, the bias current I1 charges the capacitor C0. When the voltage Vc on the upper plate of the capacitor C0 reaches the threshold voltage of the third NMOS transistor MN2, the output signal VO of the inverter 424 flips.

[0086] The delay time td, relative to the clock signal flip time, when the output signal VO flips, is td = ts + t1 = ts + C0*R / m, where ts is the delay of the delayed clock signal CLKD relative to the falling edge of the clock signal CLK, typically designed to be around 0.1ns to 0.3ns, which is negligible compared to the t1 stage time. Therefore, the delay time td is approximately equal to C0*R / m.

[0087] Therefore, it can be seen that the high-precision timing generation circuit provided by the embodiments of the present invention, compared with the traditional timing circuit, not only eliminates the non-ideal influence of accumulated charge on the charging process and avoids the occurrence of false flips, ensuring the accuracy of timing, but also effectively reduces timing deviation and improves its convergence under different voltages, temperatures and process angle deviations, since the timing is only related to the capacitor, resistor and current coefficient.

[0088] Compared with existing conventional timing circuits, the high-precision timing generation circuit provided in this embodiment of the invention has the following advantages:

[0089] 1) Suitable for precise control of internal read timing in high-speed embedded flash memory. Compared with traditional timing circuit structures, the timing circuit structure designed in this invention utilizes threshold compensation to obtain a timing circuit generation structure that is independent of the power supply voltage. The generated timing is only related to the capacitor, resistor, and current coefficient, effectively reducing timing deviation and improving its convergence under different voltages, temperatures, and process angle deviations.

[0090] 2) The high-precision timing generation circuit provided in this embodiment of the invention can effectively eliminate the non-ideal charging stage dominated by accumulated charge, avoiding the occurrence of timing errors caused by accumulated charge. The charge elimination method designed in this invention discharges the accumulated charge through a ground path in the initial stage of capacitor charging, so that the capacitor charging process is completely dominated by the bias current source, effectively ensuring the accuracy of the timing.

[0091] Accordingly, embodiments of the present invention also provide a chip including the high-precision timing generation circuit and chip of the above embodiments.

[0092] It should be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article indicates that the preceding and following related objects have an "or" relationship.

[0093] In the embodiments of this invention, "multiple" refers to two or more.

[0094] The descriptions of "first," "second," etc., appearing in the embodiments of this invention are for illustrative purposes and to distinguish the objects being described. They do not indicate any particular order and do not imply any special limitation on the number of devices in the embodiments of this invention. They do not constitute any limitation on the embodiments of this invention.

[0095] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A high-precision timing generation circuit, characterized in that, The circuit includes: a current source bias circuit and a delay circuit; The current source bias circuit is used to generate a bias current and a clamping voltage; the current source bias circuit includes: a bias current source and a clamping circuit; the bias current source is used to generate the bias current; the clamping circuit is used to generate the clamping voltage according to the bias current; the clamping circuit includes: a threshold voltage generation module and a clamping voltage generation module. The threshold voltage generation module is used to generate a threshold voltage according to the bias current; the threshold voltage generation module includes: a first NMOS transistor; the drain of the first NMOS transistor is connected to the bias current source, the source of the first NMOS transistor is grounded, and the gate of the first NMOS transistor is connected to the clamping voltage generation module. The clamping voltage generation module is used to generate a clamping voltage that is the same as the threshold voltage; The delay circuit is used to input a clock signal, delay the clock signal by charging and discharging the capacitor through the bias current, and control the flip level of the output delayed signal to be the clamping voltage; the delay circuit includes: a mirror current generation module, a charging and discharging control module, a capacitor, and a guiding module; The mirror current generation module is used to generate a mirror current based on the bias current; The charge / discharge control module is used to charge and discharge the capacitor according to the clock signal and the mirror current; The guiding module is used to output the voltage on the capacitor as an output signal and control the flip level of the output signal to be the clamping voltage. The guiding module includes a third NMOS transistor and a first PMOS transistor. The source of the first PMOS transistor is connected to the mirror current generation module, the gate of the third NMOS transistor is connected to the gate of the first PMOS transistor and connected to the capacitor, the source of the third NMOS transistor is grounded, the drain of the third NMOS transistor is connected to the drain of the first PMOS transistor, and the connection node serves as the output terminal of the guiding module. The third NMOS transistor is matched with the first NMOS transistor.

2. The high-precision timing generation circuit according to claim 1, characterized in that, The charge / discharge control module includes: The system includes a falling edge delay unit, a first transmission unit, and a second transmission unit connected to the falling edge delay unit and the first transmission unit, respectively; the connection point between the first transmission unit and the second transmission unit serves as the output terminal of the charge / discharge control module. The falling edge delay unit is used to delay the falling edge of the clock signal and output a delayed signal. The first transmission unit inputs the clock signal, and the second transmission unit inputs the delay signal; the first transmission unit and the second transmission unit generate control signals for controlling the charging and discharging of the capacitor based on the clock signal and the delay signal.

3. The high-precision timing generation circuit according to claim 2, characterized in that, The first transmission unit is a PMOS transistor, and the second transmission unit is an NMOS transistor.

4. The high-precision timing generation circuit according to claim 1, characterized in that, The clamping voltage generation module includes: a second NMOS transistor and a resistor; the resistor is connected between the gate of the first NMOS transistor and ground; the gate of the second NMOS transistor is connected to the drain of the first NMOS transistor, the source of the second NMOS transistor is connected to the gate of the first NMOS transistor, and the drain of the second NMOS transistor is connected to the bias current source.

5. The high-precision timing generation circuit according to claim 1, characterized in that, The delay circuit further includes an inverter, the input terminal of which is connected to the output terminal of the guiding module, and the output terminal of which serves as the output terminal of the delay circuit to output a delay signal.

6. A chip, characterized in that, Includes the high-precision timing generation circuit as described in any one of claims 1 to 5.

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