A method for fabricating a gallium nitride transistor, a gallium nitride transistor and a chip.

Abstract

This invention discloses a method for fabricating a gallium nitride (GaN) transistor, a GaN transistor, and a chip. The method for fabricating the GaN transistor includes: providing a semiconductor substrate; forming multiple semiconductor layers on the semiconductor substrate; forming a composite layer on the multiple semiconductor layers; wherein the composite layer is a composite structure containing silicon nitride, and in the composite structure, the proportion of silicon nitride closer to the multiple semiconductor layers is less than the proportion of silicon nitride farther from the multiple semiconductor layers; a source, a gate, and a drain are disposed on the composite layer, spaced apart from each other; the source, gate, and drain respectively penetrate the composite layer and contact the multiple semiconductor layers. The method for fabricating the GaN transistor of this application forms a composite layer containing a silicon nitride composite structure, which has better sealing properties, effectively avoids corrosion of the barrier layer by the passivation layer, and makes the interface and surface between the passivation layer and the barrier layer smooth, improving the passivation effect and thus improving the performance of the GaN transistor.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for fabricating a gallium nitride transistor, a gallium nitride transistor, and a chip. Background Technology

[0002] In the fabrication and application of integrated circuits, the performance of various devices is affected by the concentration of two-dimensional electron gas. In order to reduce the impact of the concentration of two-dimensional electron gas during the fabrication process, a passivation layer is generally deposited on the semiconductor surface to achieve passivation of the surface states.

[0003] In practice, the inventors of this application have discovered that current gallium nitride transistor fabrication methods typically employ PECVD (Plasma Enhanced Chemical Vapor Deposition) and LPCVD (Low Pressure Chemical Vapor Deposition) to prepare passivation layers. However, oxygen impurities are readily present at the interface between the passivation layer and the aluminum gallium nitride barrier layer. Furthermore, during the transfer of the passivation layer, it is easily exposed to oxygen and other impurities in the air, resulting in a rough passivation layer surface, increased gate leakage current, and the introduction of trapped energy levels into the device layer, thereby compromising the passivation effect and affecting device performance. Summary of the Invention

[0004] The main technical problem solved by this invention is to provide a method for fabricating gallium nitride transistors, gallium nitride transistors and chips, which can effectively avoid the corrosion of the barrier layer by the passivation layer, and make the interface and surface between the passivation layer and the barrier layer smooth, thereby improving the passivation effect and improving the performance of gallium nitride transistors.

[0005] To solve the above-mentioned technical problems, this application adopts the following technical solution: a method for fabricating a gallium nitride transistor, comprising: providing a semiconductor substrate; forming multiple semiconductor layers on the semiconductor substrate; and forming a composite layer on the multiple semiconductor layers. The composite layer is a composite structure containing silicon nitride, and in the composite structure, the proportion of silicon nitride near the multiple semiconductor layers is less than the proportion of silicon nitride away from the multiple semiconductor layers, so that the surface of the composite layer away from the multiple semiconductor layers is flat; a source, a gate, and a drain are disposed on the composite layer, the source, the gate, and the drain being spaced apart from each other; the source, the gate, and the drain respectively penetrate the composite layer and contact the multiple semiconductor layers.

[0006] To solve the above-mentioned technical problems, another technical solution adopted in this application is: providing a gallium nitride transistor, comprising: a semiconductor substrate; multiple semiconductor layers disposed on the semiconductor substrate; and a composite layer disposed on the multiple semiconductor layers. The composite layer is a composite structure containing silicon nitride, and in the composite structure, the proportion of silicon nitride closer to the multiple semiconductor layers is smaller than the proportion of silicon nitride farther from the multiple semiconductor layers; a source, a gate, and a drain are disposed on the composite layer at intervals, and respectively penetrate the composite layer and contact the multiple semiconductor layers.

[0007] To solve the above-mentioned technical problems, another technical solution adopted in this application is to provide a chip including the above-mentioned gallium nitride transistor.

[0008] Unlike current technologies, the gallium nitride (GaN) transistor fabrication method, GaN transistor, and chip provided in this application directly form a composite layer containing a silicon nitride (Si) composite structure on a multilayer semiconductor layer. During the formation of the SiN composite layer, the proportion of SiN gradually increases, so that the proportion of SiN near the multilayer semiconductor layer is less than the proportion of SiN far from the multilayer semiconductor layer. This results in better sealing of the formed SiN composite layer, effectively preventing the passivation layer from corroding the barrier layer. It also makes the interface and surface between the passivation layer and the barrier layer smooth, and prevents other impurities from being introduced into the passivation layer, thereby improving the passivation effect and thus improving the performance of the gallium nitride transistor. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:

[0010] Figure 1 This is a schematic flowchart of the first embodiment of the method for fabricating gallium nitride transistors in this application;

[0011] Figure 2 This is a schematic diagram of the structure of an embodiment of the semiconductor substrate in this application;

[0012] Figure 3 This is a schematic diagram of the structure in this application in which multiple semiconductor layers are formed on a semiconductor substrate;

[0013] Figure 4 This is a schematic diagram of the structure in this application where a composite layer is formed on a multilayer semiconductor layer;

[0014] Figure 5 This is a schematic diagram of the island-like structure formed by silicon nitride in the composite layer of this application;

[0015] Figure 6 This is a schematic diagram of the structure in this application in which the source, gate and drain are formed on the composite layer;

[0016] Figure 7 This is a schematic flowchart of the second embodiment of the method for fabricating gallium nitride transistors in this application;

[0017] Figure 8 This is a schematic diagram of the structure of forming a multilayer composite layer on a multilayer semiconductor layer in this application;

[0018] Figure 9 This is a schematic diagram of the structure in this application in which the source, gate and drain are disposed on a multilayer composite layer;

[0019] Figure 10 This is a schematic diagram of the structure in this application where a passivation layer is formed on the composite layer.

[0020] Explanation of reference numerals in the attached figures:

[0021] Semiconductor substrate 100, multilayer semiconductor layer 200, first semiconductor layer 210, second semiconductor layer 220, third semiconductor layer 230, fourth semiconductor layer 240, fifth semiconductor layer 250, composite layer 300, first composite layer 310, second composite layer 320, source 400, gate 500, drain 600, passivation layer 700. Detailed Implementation

[0022] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0023] The terms "first," "second," and "third" in this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0024] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0025] The present application will now be described in detail with reference to the accompanying drawings and embodiments.

[0026] In current gallium nitride (GaN) transistor fabrication, passivation layers are typically deposited using PECVD and LPCVD methods. However, oxygen impurities are highly likely to be present at the interface between the passivation layer and the semiconductor layer during fabrication. Furthermore, when depositing the passivation layer using equipment such as PECVD and LPCVD, the epitaxial wafer must be removed from the epitaxial equipment and transferred to the PECVD or LPCVD equipment. This process inevitably exposes the wafer to oxygen and other impurities from the air. Even with cleaning, it is difficult to completely eliminate residual impurities. These impurities not only increase gate leakage current but also introduce trapped levels back into the device layer, compromising the passivation effect and affecting the performance of the GaN transistor.

[0027] Therefore, a method for fabricating gallium nitride transistors is proposed to avoid corrosion of the barrier layer by the passivation layer, and to make the interface and surface between the passivation layer and the barrier layer smooth, while preventing other impurities from being introduced into the passivation layer, thereby improving the passivation effect and thus improving the performance of gallium nitride transistors.

[0028] Please see Figure 1 , Figure 1 This is a schematic flowchart of the first embodiment of the method for fabricating gallium nitride transistors in this application.

[0029] like Figure 1 As shown, the method for fabricating a gallium nitride transistor in this embodiment includes:

[0030] S11, Provide semiconductor substrate.

[0031] Specifically, please refer to Figure 2 , Figure 2 This is a schematic diagram of the structure of a semiconductor substrate according to an embodiment of this application. It can be understood that, as Figure 2 As shown, the semiconductor substrate 100 includes a substrate. The substrate can be one of various substrates, such as a silicon substrate, a silicon carbide substrate, a gallium nitride substrate, a germanium substrate, or an SOI (Semiconductor on Insulator, such as silicon on insulator, germanium on insulator, or silicon-germanium on insulator) substrate. Those skilled in the art will understand that the substrate is not limited in any way, but can be selected according to the actual application.

[0032] In other embodiments, the semiconductor substrate 100 may also include device structures, isolation structures, dielectric layers, or interconnect structures disposed in or on the substrate (not shown in the figures). Those skilled in the art will understand that the device structures, isolation structures, dielectric layers, or interconnect structures are not limited in any way, but can be selected according to the actual application.

[0033] S12. Forming multiple semiconductor layers on a semiconductor substrate.

[0034] Please see Figure 3 , Figure 3 This is a schematic diagram illustrating a structure in which multiple semiconductor layers are formed on a semiconductor substrate, according to an embodiment of this application. Figure 3 As shown, a gallium nitride transistor includes a semiconductor substrate 100 and a multilayer semiconductor layer 200 formed on the semiconductor substrate 100. The multilayer semiconductor layer 200 can be three layers, five layers, ten layers, etc., and can be set according to the actual gallium nitride transistor.

[0035] Specifically, in this embodiment, a five-layer semiconductor layer is used as an example for illustration. A first semiconductor layer 210, a second semiconductor layer 220, a third semiconductor layer 230, a fourth semiconductor layer 240, and a fifth semiconductor layer 250 are sequentially formed on a semiconductor substrate 100.

[0036] In some embodiments, the first semiconductor layer 210 can be a buffer layer, made of semi-insulating, high-resistivity, high-quality gallium nitride (GaN), with a thickness of 3-4 μm; the second semiconductor layer 220 can be a channel layer, made of high-quality gallium nitride (GaN), with a thickness of 150-250 nm, such as 200 nm; the third semiconductor layer 230 can be an insertion layer, made of aluminum nitride (AlN), with a thickness of 0.1-1 nm; the fourth semiconductor layer 240 can be a barrier layer, made of aluminum gallium nitride (AlGaN), with a thickness of 15-30 nm; and the fifth semiconductor layer 250 can be a capping layer, made of gallium nitride (GaN), also known as an intrinsic GaN layer, with a thickness of 1-5 nm.

[0037] Specifically, in this embodiment, the multilayer semiconductor layer 200 is deposited using MOCVD (Metal Organic Chemical Vapor Deposition). For example, a gallium nitride (GaN) buffer layer is grown on the semiconductor substrate 100 using MOCVD; a gallium nitride (GaN) channel layer is grown on the gallium nitride (GaN) buffer layer using MOCVD; an AlN insertion layer is grown on the gallium nitride (GaN) channel layer using MOCVD; an AlGaN barrier layer is grown on the AlN insertion layer using MOCVD; and a GaN capping layer is grown on the AlGaN barrier layer using MOCVD.

[0038] S13. A composite layer is formed on the multilayer semiconductor layer. The composite layer is a composite structure containing silicon nitride, and in the composite structure, the proportion of silicon nitride close to the multilayer semiconductor layer is smaller than the proportion of silicon nitride far from the multilayer semiconductor layer, so that the surface of the composite layer far from the multilayer semiconductor layer is flat.

[0039] Please see Figure 4 , Figure 4 This is a schematic diagram of a structure in which a composite layer is formed on a multilayer semiconductor layer, according to an embodiment of this application. Figure 5 This is a schematic diagram of the island-like structure formed by silicon nitride in composite layer 300. (Example) Figure 4 As shown, a gallium nitride transistor includes a semiconductor substrate 100, a multilayer semiconductor layer 200 formed on the semiconductor substrate 100, and a composite layer 300 formed on the multilayer semiconductor layer 200.

[0040] Specifically, the composite layer 300 is grown in situ using MOCVD. That is, a first semiconductor layer 210, a second semiconductor layer 220, a third semiconductor layer 230, a fourth semiconductor layer 240, and a fifth semiconductor layer 250 are sequentially grown on the semiconductor substrate 100 using MOCVD, and the composite layer 300 is grown accordingly; and during the growth of the composite layer 300, such as... Figure 5 As shown, the proportion of silicon nitride closer to the multilayer semiconductor layer 200 is less than that farther away from the multilayer semiconductor layer 200. That is, the distribution of silicon nitride in the composite layer 300 gradually increases from bottom to top, so that the island-like structure formed by silicon nitride is filled by other materials in the composite layer 300. In other words, the discontinuous porous film formed by silicon nitride during the deposition process is filled by other materials in the composite layer 300, which can effectively prevent the lower multilayer semiconductor layer 200 from being corroded, so that the interface between the composite layer 300 and the multilayer semiconductor layer 200 and the corresponding surface are flat, thus protecting the lower multilayer semiconductor layer 200.

[0041] In some embodiments, such as Figure 5 As shown, the island-like structure formed by silicon nitride (SiN) in the composite layer 300 can be called SiNx islands, that is, countless SiNx are formed in the composite layer 300, and the gaps between SiNx become smaller and smaller from bottom to top.

[0042] S14. A source, a gate, and a drain are disposed on the composite layer, with the source, gate, and drain spaced apart from each other; the source, gate, and drain respectively penetrate the composite layer and contact the multilayer semiconductor layer.

[0043] Please see Figure 6 , Figure 6 This is a schematic diagram illustrating the structure of forming a source, gate, and drain on a composite layer according to an embodiment of this application. Figure 6 As shown, a gallium nitride transistor includes a semiconductor substrate 100, a multilayer semiconductor layer 200 formed on the semiconductor substrate 100, a composite layer 300 formed on the multilayer semiconductor layer 200, and a source 400, a gate 500, and a drain 600 disposed on the composite layer.

[0044] Specifically, in this embodiment, a first semiconductor layer 210, a second semiconductor layer 220, a third semiconductor layer 230, and a composite layer 300 are sequentially grown on a semiconductor substrate 100 using MOCVD, and a corresponding source 400, gate 500, and drain 600 are disposed on the composite layer 300.

[0045] The composite layer 300 needs to be etched to form source contact holes, gate contact holes and drain contact holes; and a source 400 is formed in the source contact hole, a gate 500 is formed in the gate contact hole and a drain 600 is formed in the drain contact hole; the source 400, gate 500 and drain 600 are spaced apart from each other, and the gate 500 is located between the source 400 and the drain 600.

[0046] Alternatively, dry etching can be used to etch the composite layer.

[0047] In this embodiment, during the formation of the composite layer 300 using MOCVD, the composite layer 300 is formed by gradually increasing silicon nitride (SiN). This allows the silicon nitride (SiN) to form a discontinuous porous film during deposition, which is then filled by other materials in the composite layer. This effectively prevents the underlying multilayer semiconductor layer 200 from being corroded, resulting in a smooth interface and surface between the composite layer 300 and the multilayer semiconductor layer 200. This protects the underlying multilayer semiconductor layer 200 and effectively improves the electrical performance of the gallium nitride transistor.

[0048] Please see Figure 7 , Figure 7 This is a schematic flowchart of the second embodiment of the method for fabricating gallium nitride transistors according to this application.

[0049] like Figure 7 As shown, the method for fabricating a gallium nitride transistor in this embodiment includes:

[0050] S21, Provide semiconductor substrate.

[0051] S22. Forming multiple semiconductor layers on a semiconductor substrate.

[0052] S23. A first composite layer is formed on a multilayer semiconductor layer.

[0053] In this process, a first dielectric layer is formed on a multilayer semiconductor layer using silicon nitride, and a second dielectric layer with a first ratio is formed on the first dielectric layer. The second dielectric layer fills the gaps in the first dielectric layer to form a first composite layer.

[0054] S24. A second composite layer is formed on the first composite layer.

[0055] In this process, a third dielectric layer is formed on the first composite layer using silicon nitride, and a fourth dielectric layer with a second ratio is formed on the third dielectric layer. The fourth dielectric layer fills the gaps in the third dielectric layer to form a second composite layer.

[0056] Please see Figure 8 , Figure 8 This is a schematic diagram of a structure in which a multilayer composite layer is formed on a multilayer semiconductor layer, according to an embodiment of this application. Figure 8 As shown, a gallium nitride transistor includes a semiconductor substrate 100, a multilayer semiconductor layer 200 formed on the semiconductor substrate 100, and a composite layer 300 formed on the multilayer semiconductor layer 200. The composite layer 300 includes a first composite layer 310 and a second composite layer 320; that is, the first composite layer 310 is formed on the multilayer semiconductor layer 200, and the second composite layer 320 is formed on the first composite layer 310. In other words, the first composite layer 310 is disposed on the multilayer semiconductor layer 200, and the second composite layer 320 is disposed on the first composite layer 310.

[0057] The composite layer 300 can be a silicon nitride (SiN) / gallium nitride (GaN) composite layer; wherein the proportion of silicon nitride (SiN) in the first composite layer 310 is less than the proportion of silicon nitride (SiN) in the second composite layer 320; that is, the distribution of silicon nitride (SiN) in the silicon nitride (SiN) / gallium nitride (GaN) composite layer gradually increases from bottom to top.

[0058] The first dielectric layer is a silicon nitride (SiN) layer, the second dielectric layer is a gallium nitride (GaN) layer, and the gallium nitride (GaN) layer, which serves as the second dielectric layer, fills the gaps in the silicon nitride (SiN) layer, which serves as the first dielectric layer, thereby forming a first composite layer 310; the third dielectric layer is a silicon nitride (SiN) layer, the fourth dielectric layer is a gallium nitride (GaN) layer, and the gallium nitride (GaN) layer, which serves as the third dielectric layer, fills the gaps in the silicon nitride (SiN) layer, which serves as the fourth dielectric layer, thereby forming a second composite layer 320.

[0059] Specifically, in this embodiment, the multilayer semiconductor layers are deposited using MOCVD (Metal-Organic Chemical Vapor Deposition). For example: a gallium nitride (GaN) buffer layer is grown on the semiconductor substrate 100 using MOCVD; a gallium nitride (GaN) channel layer is grown on the GaN buffer layer using MOCVD; an AlN insertion layer is grown on the GaN channel layer using MOCVD; an AlGaN barrier layer is grown on the AlN insertion layer using MOCVD; a GaN capping layer is grown on the AlGaN barrier layer using MOCVD; after growing the GaN capping layer, a small amount of SiN is grown on the GaN capping layer. SiNx1 islands, i.e., the first dielectric layer, are grown. GaN is then grown on the SiNx1 islands, i.e., the second dielectric layer is grown. GaN fills the gaps between the SiNx1 islands to form the first composite layer 310. SiNx2 islands, i.e., the third dielectric layer, are grown on the first composite layer 310. The gaps between the grown SiNx2 islands are smaller than those between the SiNx2 islands. GaN is then grown on the SiNx2 islands, i.e., the fourth dielectric layer is grown. GaN fills the gaps between the SiNx2 islands to form the second composite layer 320.

[0060] In some embodiments, SiN is further grown on the second composite layer 320, that is, a fifth dielectric layer is grown on the second composite layer 320, so that the surface of the composite layer 300 is a flat thin film; that is, the thickness of the composite layer 300 can be 2-3 nm. The composite layer 300 includes: a first composite layer 310 formed by a first dielectric layer and a second dielectric layer, a second composite layer 320 formed by a third dielectric layer and a fourth dielectric layer, and a fifth dielectric layer; wherein, the first dielectric layer, the third dielectric layer and the fifth dielectric layer can be silicon nitride (SiN) layers, and the second dielectric layer and the fourth dielectric layer can be gallium nitride (GaN) layers.

[0061] In another embodiment, the composite layer 300 may include multiple composite layers, such as four or six composite layers, which can be set according to actual conditions. Taking four composite layers as an example, the composite layer 300 may include a first composite layer, a second composite layer, a third composite layer, and a fourth composite layer stacked sequentially. The proportion of silicon nitride (SiN) in the first composite layer is less than that in the second composite layer, the proportion of silicon nitride (SiN) in the second composite layer is less than that in the third composite layer, and the proportion of silicon nitride (SiN) in the third composite layer is less than that in the fourth composite layer. That is, from bottom to top, the proportion of silicon nitride (SiN) in the composite layers increases sequentially. For example, during the growth of silicon nitride (SiN), SiH4 / NH3 is used for growth, with a SiH4 / NH3 ratio of 0.2*10^6 to 90*10^6. Within this range, the Si / N ratio is increased layer by layer, increasing by approximately 10-30 each time, and can be increased proportionally.

[0062] In another embodiment, multiple sets of composite structures are grown on the GaN capping layer before growing the SiN dielectric layer. The composite structure is a SiNx / GaN composite structure with gradually increasing SiNx content. Its thickness and structure can be arranged in a proportional periodic manner. The epitaxial structure containing the composite structure GaN-based HEMT (High Electron Mobility Transistor) can also effectively solve the corrosion problem of SiH4 on group III nitrides during SiNx growth while avoiding particle contamination introduced by the secondary deposited dielectric layer.

[0063] S25. A source, a gate, and a drain are disposed on the second composite layer, with the source, gate, and drain spaced apart from each other; the source, gate, and drain respectively penetrate the second composite layer and the first composite layer and contact the multilayer semiconductor layer.

[0064] See Figure 9 , Figure 9 This is a schematic diagram illustrating a structure in which a source, gate, and drain are disposed on a multilayer composite layer, according to an embodiment of this application. Figure 9 As shown, a gallium nitride transistor includes a semiconductor substrate 100, a multilayer semiconductor layer 200 formed on the semiconductor substrate 100, and a composite layer 300 formed on the multilayer semiconductor layer 200. A source 400, a gate 500, and a drain 600 are disposed on the composite layer 300. The composite layer 300 includes a first composite layer 310 and a second composite layer 320, i.e., the first composite layer 310 is formed on the multilayer semiconductor layer 200, the second composite layer 320 is formed on the first composite layer 310, and the source 400, the gate 500, and the drain 600 are disposed on the second composite layer 320.

[0065] Specifically, using MOCVD, a gallium nitride (GaN) buffer layer is grown on a semiconductor substrate 100; a gallium nitride (GaN) channel layer is grown on the GaN buffer layer; an AlN insertion layer is grown on the GaN channel layer; an AlGaN barrier layer is grown on the AlN insertion layer; a GaN capping layer is grown on the AlGaN barrier layer; after growing the GaN capping layer, a small number of SiNx1 islands are grown on the GaN capping layer, i.e., the first dielectric layer is grown; GaN continues to grow on the SiNx1 island layers, i.e., the first dielectric layer is grown. The second dielectric layer is formed by filling the gaps between SiNx1 islands with GaN to form a first composite layer 310. SiNx2 islands are then grown on the first composite layer 310, forming a third dielectric layer. The gaps between the grown SiNx2 islands are smaller than those between the SiNx2 islands. GaN is then grown on the SiNx2 islands, forming a fourth dielectric layer. GaN fills the gaps between the SiNx2 islands to form a second composite layer 320. A source 400, a gate 500, and a drain 600 are disposed on the second composite layer 320. The composite layer 300 needs to be etched to form source contact holes, gate contact holes, and drain contact holes. A source 400 is formed in the source contact hole, a gate 500 is formed in the gate contact hole, and a drain 600 is formed in the drain contact hole. The source 400, gate 500, and drain 600 are spaced apart from each other, with the gate 500 located between the source 400 and the drain 600.

[0066] In one embodiment, please refer to Figure 10 , Figure 10 This is a schematic diagram of a structure in which a passivation layer is formed on a composite layer 300, according to an embodiment of this application. Figure 10 As shown, a gallium nitride transistor includes a semiconductor substrate 100, a multilayer semiconductor layer 200 formed on the semiconductor substrate 100, and a composite layer 300 formed on the multilayer semiconductor layer 200. The composite layer 300 includes a first composite layer 310 and a second composite layer 320. Specifically, the first composite layer 310 is formed on the multilayer semiconductor layer 200, the second composite layer 320 is formed on the first composite layer 310, and a sixth dielectric layer is formed on the second composite layer 320. A passivation layer 700 is also formed on the second composite layer 320. A source 400, a gate 500, and a drain 600 are disposed on the passivation layer 700. This process involves etching the passivation layer 700 and the composite layer 300 to form a source contact hole, a gate contact hole, and a drain contact hole that penetrate the passivation layer 700 and the composite layer 300. A source 400 is formed in the source contact hole, a gate 500 is formed in the gate contact hole, and a drain 600 is formed in the drain contact hole. The source 400, the gate 500, and the drain 600 are spaced apart from each other, with the gate 500 located between the source 400 and the drain 600.

[0067] The sixth dielectric layer can be a silicon nitride (SiN) layer, meaning that silicon nitride (SiN) is grown on the second composite layer 320 to form a passivation layer composed of silicon nitride (SiN), with a thickness of 3–5 nm. To suppress the surface electronic states of high electron mobility transistors, a SiNx passivation layer is often deposited to passivate the surface states of aluminum gallium nitride (AlGaN) / gallium nitride (GaN). The SiNx passivation layer not only suppresses surface states but also isolates impurity atoms and molecules, mitigating the current collapse effect in AlGaN / gallium nitride (GaN) high electron mobility transistors. In the commonly used method of directly growing SiNx, the source gas SiH4 corrodes the underlying group III nitride, and SiNx deposition easily forms discontinuous porous films, leading to subsequent SiH4 corrosion of the underlying group III nitride. This results in an uneven interface and surface between the two, ultimately damaging the device's barrier layer. This application utilizes in-situ MOCVD growth of SiNx / GaN composite layers, using the SiNx / GaN composite layer as a transition layer before SiNx growth, to achieve surface passivation of AlGaN / GaN high electron mobility transistors. This effectively solves the problem of poor passivation layer uniformity and device barrier layer damage caused by the corrosion of group III nitrides by the SiH4 reaction source during the epitaxial growth of SiNx layers on GaN. This provides a novel in-situ MOCVD growth method for SiNx passivation layers in HEMTs. Furthermore, the epitaxial fabrication is simple and easy to implement, with high repeatability and controllability, making it easier for large-scale production.

[0068] In this embodiment, during the formation of the composite layer 300 using MOCVD, the composite layer 300 is formed by gradually increasing the amount of silicon nitride. The grown dielectric layer can also effectively avoid particle contamination introduced by secondary epitaxy. In addition, this method can be easily implemented through epitaxial fabrication, and has very high repeatability and controllability, making it easier to carry out large-scale production. Correspondingly, SiNx / GaN composite layers with different proportions are formed from bottom to top, so that the discontinuous porous film formed by silicon nitride (SiN) during the deposition process is filled by gallium nitride (GaN) in the composite layer. This can effectively prevent the corrosion of the underlying multilayer semiconductor layer, making the interface between the composite layer and the multilayer semiconductor layer and the corresponding surface smooth, protecting the underlying multilayer semiconductor layer, and thus effectively improving the electrical performance of the gallium nitride transistor.

[0069] In one embodiment, a chip is also included, which contains the gallium nitride transistor described above.

[0070] The above description is merely an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A method for fabricating a gallium nitride transistor, characterized in that, include: Provide semiconductor substrates, Multiple semiconductor layers are formed on the semiconductor substrate; A composite layer is formed on the multilayer semiconductor layer; wherein the composite layer is a composite structure containing silicon nitride, and in the composite structure, the proportion of silicon nitride close to the multilayer semiconductor layer is smaller than the proportion of silicon nitride far from the multilayer semiconductor layer, so that the surface of the composite layer far from the multilayer semiconductor layer is flat. A source, a gate, and a drain are disposed on the composite layer, with the source, the gate, and the drain spaced apart from each other; the source, the gate, and the drain respectively penetrate the composite layer and contact the multilayer semiconductor layer; The composite layer comprises at least two composite layers; The formation of a composite layer on the multilayer semiconductor layers includes: A first composite layer is formed on the multilayer semiconductor layer, wherein a first dielectric layer is formed on the multilayer semiconductor layer using silicon nitride, and a second dielectric layer is formed on the first dielectric layer, wherein the second dielectric layer fills the gaps in the first dielectric layer to form the first composite layer; A second composite layer is formed on the first composite layer, wherein a third dielectric layer is formed on the first composite layer using the silicon nitride, and a fourth dielectric layer is formed on the third dielectric layer, wherein the fourth dielectric layer fills the gaps in the third dielectric layer to form the second composite layer. The proportion of silicon nitride in the first composite layer is less than the proportion of silicon nitride in the second composite layer.

2. The preparation method according to claim 1, characterized in that, The first dielectric layer in the first composite layer and the third dielectric layer in the second composite layer respectively form silicon nitride island structures, wherein the gap ratio of the silicon nitride island structure corresponding to the first dielectric layer is greater than the gap ratio of the silicon nitride island structure corresponding to the third dielectric layer.

3. The preparation method according to claim 1, characterized in that, The composite layer further includes a fifth dielectric layer, wherein the fifth dielectric layer is formed on the second composite layer to make the surface of the composite layer flat.

4. The preparation method according to claim 3, characterized in that, The materials of the first dielectric layer, the third dielectric layer, and the fifth dielectric layer are different from the materials of the second dielectric layer and the fourth dielectric layer, wherein the first dielectric layer, the third dielectric layer, and the fifth dielectric layer are silicon nitride layers.

5. The preparation method according to claim 1, characterized in that, After the composite layer is formed, a sixth dielectric layer is formed on the composite layer, wherein the material of the sixth dielectric layer is different from the materials of the second dielectric layer and the fourth dielectric layer.

6. The preparation method according to claim 1, characterized in that, The process of forming a multilayer semiconductor layer on the semiconductor substrate includes: A buffer layer is formed on the semiconductor substrate; A channel layer is formed on the buffer layer; An insertion layer is formed on the channel layer; A barrier layer is formed on the insertion layer; A capping layer is formed on the barrier layer.

7. The preparation method according to claim 6, characterized in that, The source, the gate, and the drain respectively penetrate the composite layer and contact the capping layer to form a gallium nitride transistor.

8. A gallium nitride transistor, characterized in that, include: Semiconductor substrate, A multilayer semiconductor layer is disposed on the semiconductor substrate; A composite layer is disposed on the multilayer semiconductor layer; wherein the composite layer is a composite structure containing silicon nitride, and in the composite structure, the proportion of silicon nitride close to the multilayer semiconductor layer is smaller than the proportion of silicon nitride far from the multilayer semiconductor layer; The source, gate, and drain are disposed on the composite layer at intervals and respectively penetrate the composite layer to contact the multilayer semiconductor layer; The composite layer comprises at least two composite layers; the composite layer includes a first composite layer and a second composite layer, wherein the first composite layer is disposed on the multilayer semiconductor layer, the second composite layer is disposed on the first composite layer, and the proportion of silicon nitride in the first composite layer is less than the proportion of silicon nitride in the second composite layer. The first composite layer includes: a first dielectric layer disposed on the multilayer semiconductor layer to form a silicon nitride island structure; and a second dielectric layer to fill the gaps in the silicon nitride island structure corresponding to the first dielectric layer. The second composite layer includes: a third dielectric layer disposed on the first composite layer to form a silicon nitride island structure; and a fourth dielectric layer to fill the gaps in the silicon nitride island structure corresponding to the third dielectric layer.

9. The gallium nitride transistor according to claim 8, characterized in that, The gap ratio of the silicon nitride island structure corresponding to the first dielectric layer is greater than the gap ratio of the silicon nitride island structure corresponding to the third dielectric layer.

10. The gallium nitride transistor according to claim 8, characterized in that, The composite layer further includes a fifth dielectric layer, wherein the fifth dielectric layer is disposed on the second composite layer.

11. The gallium nitride transistor according to claim 8, characterized in that, The gallium nitride transistor further includes a sixth dielectric layer disposed on the composite layer.

12. The gallium nitride transistor according to claim 8, characterized in that, The multilayer semiconductor layer includes a buffer layer, a channel layer, an insertion layer, a barrier layer, and a capping layer arranged sequentially.

13. A chip, characterized in that, Includes the gallium nitride transistor as described in any one of claims 8-12.

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