A processing method and product of MLO for FCBGA

By leading the pad in the FCBGA chip package to the outer layer and using laser technology to connect the outer layer to the secondary outer layer, the probe contact problem caused by ink is solved, the test accuracy and success rate are improved, and the risk of line short circuit is reduced.

CN116230552BActive Publication Date: 2025-05-20PI SEMICON (NANTONG) CO LTD
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Patent Information

Application Number
CN202310036411.5
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2023-01-09
Publication Date
2025-05-20
Estimated Expiration
2043-01-09

AI Technical Summary

Technical Problem

In FCBGA chip packaging, incoming unevenness causes the probe to fail to contact the pad normally. The existing technology is solved by raising copper columns, but the success rate is low and there is a risk of line short circuit.

Method used

By guiding the pad to the outer layer, the outer layer is connected to the secondary outer layer by using laser technology, the contact surface between the probe and the pad is increased, and the circuit is covered by the ABF membrane to reduce the risk of short circuit.

Benefits of technology

It improves the contact success rate between the probe and the pad, reduces the risk of the probe incorrectly tying the line, enhances the test accuracy and success rate, and protects the line from short circuits.

✦ Generated by Eureka AI based on patent content.

Smart Images

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Patent Text Reader

Abstract

The present invention relates to a processing method and product of MLO for FCBGA, including the following steps: first PTH, pretreatment, first lamination, first exposure, first development, copper electroplating, first film stripping, first flash etching, ABF pressing, laser, glue removal, second PTH, second lamination, second exposure, second development, hole filling electroplating, gold electroplating, second film stripping, second flash etching, and the processing method is simple. The processing method of the present invention is simple, reasonable, and easy to operate. By leading the pad to the outer layer, the circuit is placed in the sub-outer layer, and the outer layer is connected with the sub-outer layer by laser, thereby reducing the risk of the probe mistakenly piercing the circuit, increasing the contact surface between the probe and the pad, and thus improving the test accuracy and success rate.
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Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and in particular to a processing method and product of an MLO for FCBGA. Background Art

[0002] FCBGA (Flip Chip Ball Grid Array) is a chip packaging method, and MLO is a substrate. During the processing of the substrate, due to the easy unevenness of the ink during printing, the probe measurement pad (pad) will be lower than the ink, resulting in the probe being unable to contact the pad normally;

[0003] Therefore, the existing technology is to grow copper pillars on the pad to increase the height of the pad so that the pad can be contacted by the probe. The disadvantages of the existing technology are: the success rate of growing copper pillars on the pad is low, and at the same time, there is a risk of short circuit of the circuit.

[0004] For this reason, we propose a processing method and product of an MLO for FCBGA. Summary of the Invention

[0005] In view of the above-mentioned disadvantages in the existing production technology, the applicant provides a processing method and product of an MLO for FCBGA. By leading the pad to the outer layer and placing the circuit in the secondary outer layer, the outer layer and the secondary outer layer are connected by laser, thereby reducing the risk of the probe mis-poking the circuit, increasing the contact surface between the probe and the pad, and thus improving the test accuracy and success rate.

[0006] The technical solution adopted by the present invention is as follows:

[0007] A processing method of an MLO for FCBGA includes the following steps:

[0008] S1. First PTH: First perform PTH treatment on the substrate and attach a layer of copper with a thickness of 1-3 um as the first conductive layer;

[0009] S2. First film pressing, first exposure, first development: Form a first dry film layer on the first conductive layer through the film pressing process, and then through the exposure and development processes, expose the positions that need to be copper-plated;

[0010] S3. Electroplating copper: Electroplate another layer of first electroplated copper layer with a thickness of 16-20 um on the first conductive layer exposed on the first dry film layer to form a pad;

[0011] S4. First film removal: Remove the first dry film layer;

[0012] S5. First flash etching: Remove the first conductive layer;

[0013] S6. Press ABF: Press an ABF film on the substrate;

[0014] S7, Laser, Ablation: Remove the ABF film on the contact surface of the first electroplated copper layer by laser;

[0015] S8, Second PTH: Deposit a second conductive layer on the first electroplated copper layer and the ABF film;

[0016] S9, Second Film Lamination: Laminate a second dry film layer 7 on the second conductive layer;

[0017] S10, Second Exposure, Second Development: Expose and develop to expose the first electroplated copper layer that needs to be electroplated with copper;

[0018] S11, Via Filling Electroplating: Deposit a second electroplated copper layer on the first electroplated copper layer;

[0019] S12, Electroplated Gold: Deposit a gold plating layer on the second electroplated copper layer;

[0020] S13, Second Film Removal: Remove the second dry film layer;

[0021] S14, Second Flash Etching: Remove the second conductive layer.

[0022] It is further characterized in that:

[0023] The opening of the contact surface of the first electroplated copper layer in S7 is in an expanding shape.

[0024] The second electroplated copper layer in S11 extends out of the second dry film layer.

[0025] Before S2, it also includes pre-treatment, which cleans the surface of the substrate and increases the roughness of the copper surface to prepare for subsequent film lamination.

[0026] An MLO prepared by a processing method for MLO of FCBGA, including a substrate, a plurality of first electroplated copper layers connected to the upper and lower end faces of the substrate, ABF films are attached to the upper and lower end faces of the substrate outside the first electroplated copper layer, and a second electroplated copper layer extending out of the ABF film is laminated and connected to the side wall on the first electroplated copper layer.

[0027] A gold plating layer is connected to the end face of the second electroplated copper layer extending out of the ABF film.

[0028] The second electroplated copper layer is in a horn-shaped structure.

[0029] The beneficial effects of the present invention are as follows:

[0030] The processing method of the present invention is simple, reasonable and easy to operate. By leading out the pad (the first electroplated copper layer and the second electroplated copper layer) to the outer layer and placing the circuit on the second outer layer, the outer layer is connected to the second outer layer by laser, thereby reducing the risk of the probe accidentally piercing the circuit, increasing the contact area between the probe and the pad, improving the test accuracy and success rate. At the same time, ABF is used to cover part of the circuit, isolating the circuit layer, without the risk of short circuit, and protecting the circuit from being affected.

[0031] Meanwhile, the present invention also has the following advantages:

[0032] 1. By designing the second electroplated copper layer to extend out of the second dry film layer, the problem that the ink is higher than the pad can be effectively solved.

[0033] 2. By designing the shape of the second electroplated copper layer into a horn shape, the contact area between the pad and the probe is increased, thereby reducing the difficulty of chip testing.

[0034] 3. By leading out the pad (the first electroplated copper layer and the second electroplated copper layer) to the outer layer, the circuit is protected from being accidentally pierced by the probe.

[0035] 4. Using ABF to cover part of the circuit reduces the risk of the circuit being scratched and short-circuited. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 It is a diagram of the substrate state during the first PTH in Embodiment 1 of the present invention.

[0037] Figure 2 It is a diagram of the substrate state during the first film pressing in Embodiment 1 of the present invention.

[0038] Figure 3 It is a diagram of the substrate state during the first exposure and development in Embodiment 1 of the present invention.

[0039] Figure 4 It is a diagram of the substrate state during electroplating copper in Embodiment 1 of the present invention.

[0040] Figure 5 It is a diagram of the substrate state during the first film stripping in Embodiment 1 of the present invention.

[0041] Figure 6 It is a diagram of the substrate state during the first flash etching in Embodiment 1 of the present invention.

[0042] Figure 7 It is a diagram of the substrate state during pressing ABF in Embodiment 1 of the present invention.

[0043] Figure 8 It is a diagram of the substrate state during laser in Embodiment 1 of the present invention.

[0044] Figure 9This is the substrate state diagram during the second PTH in Embodiment 1 of the present invention.

[0045] Figure 10 This is the substrate state diagram during the second film pressing in Embodiment 1 of the present invention.

[0046] Figure 11 This is the substrate state diagram during the second exposure and development in Embodiment 1 of the present invention.

[0047] Figure 12 This is the substrate state diagram during the via filling electroplating in Embodiment 1 of the present invention.

[0048] Figure 13 This is the substrate state diagram during the electroplating of gold in Embodiment 1 of the present invention.

[0049] Figure 14 This is the substrate state diagram during the second film stripping in Embodiment 1 of the present invention.

[0050] Figure 15 This is the substrate state diagram during the second flash etching in Embodiment 1 of the present invention.

[0051] Wherein: 1. Substrate; 2. First electroplated copper layer; 3. Second electroplated copper layer; 4. ABF film; 5. Gold plating layer; 6. Second conductive layer; 7. Second dry film layer; 8. First conductive layer; 9. First dry film layer. Detailed implementation manners

[0052] The following combines with the attached drawings to illustrate the detailed implementation manners of the present invention.

[0053] Embodiment 1

[0054] This embodiment discloses a processing method and its product for MLO of FCBGA:

[0055] Introduction to the new technology process:

[0056] The first PTH → pretreatment → the first film pressing → the first exposure → the first development → electroplating copper →

[0057] The first film stripping → the first flash etching → pressing ABF → laser → degumming → the second PTH → the second film pressing →

[0058] The second exposure → the second development → via filling electroplating → electroplating of gold → the second film stripping → the second flash etching.

[0059] Specifically, it includes the following steps:

[0060] S1. The first PTH: First, perform PTH on the substrate 1, deposit a layer of copper with a thickness of 1 - 3 um to form the first conductive layer 8 for electroplating copper; (as Figure 1 shown);

[0061] S2. Pretreatment, First Film Lamination, First Exposure, First Development: Clean the surface of the substrate 1 and increase the roughness of the copper surface to prepare for subsequent film lamination. Form a first dry film layer 9 on the first conductive layer 8 through the film lamination process, and then expose and develop to expose the positions where copper plating is required; (as Figures 2 - 3 shown);

[0062] S3. Copper Electroplating: Deposit a first electroplated copper layer 2 with a thickness of 16 - 20 μm on the exposed first conductive layer 8 on the first dry film layer 9 to form pads; (as Figure 4 shown);

[0063] S4. First Demasking: Remove the pressed first dry film layer 9 through the demasking process; (as Figure 5 shown)

[0064] S5. First Flash Etching: Remove the first conductive layer 8 under the first dry film layer 9 by flash etching (as Figure 6 shown);

[0065] S6. ABF Lamination: Press an ABF film 4 on the substrate 1 processed in step S5 to cover the first electroplated copper layer 2 and the circuit (as Figure 7 shown);

[0066] S7. Laser Drilling and Glue Removal: Drill a laser on the first electroplated copper layer 2 to transfer the contact surface of the first electroplated copper layer 2 to the laser opening surface (as Figure 8 shown), and the opening is in an expanded shape;

[0067] S8. Second PTH: Deposit a second conductive layer 6 on the first electroplated copper layer 2 and the ABF film 4 (as Figure 9 shown);

[0068] S9. Second Film Lamination: Press a second dry film layer 7 on the second conductive layer 6 (as Figure 10 shown);

[0069] S10. Second Exposure and Second Development: Expose and develop to expose the first electroplated copper layer 2 where copper plating is required (as Figure 11 shown);

[0070] S11. Via Filling Electroplating: Deposit a second electroplated copper layer 3 on the first electroplated copper layer 2 to form pads extending outward on the original pads, so that the second electroplated copper layer 3 extends out of the second dry film layer 7 (as Figure 12 shown);

[0071] S12. Gold Electroplating: Deposit a gold plating layer 5 on the second electroplated copper layer 3 to ensure the hardness of the second electroplated copper layer 3 and prevent copper surface oxidation (as Figure 13 shown);

[0072] S13. Second stripping: Remove the second dry film layer 7 (as Figure 14 shown);

[0073] S14. Second flash etching: Remove the second conductive layer 6 under the second dry film layer 7 by flash etching (as Figure 15 shown), thereby forming the substrate structure of the present application.

[0074] In this technology, the pad (the first electroplated copper layer 2 and the second electroplated copper layer 3) is led out to the outer layer, and the circuit is placed in the second outer layer, and the outer layer and the second outer layer are connected by laser, thereby reducing the risk of the probe accidentally piercing the circuit, increasing the contact surface between the probe and the pad, and thus improving the test accuracy and success rate.

[0075] At the same time, ABF is used to cover part of the circuit, isolate the circuit layer, there is no risk of short circuit, and the circuit is protected from being affected.

[0076] Embodiment 2

[0077] As Figure 13 shown, an MLO for FCBGA disclosed in this embodiment is prepared by using the processing method of Embodiment 1, and it includes a substrate 1, a plurality of first electroplated copper layers 2 connected to the upper and lower end faces of the substrate 1. ABF films 4 are attached to the upper and lower end faces of the substrate 1 outside the first electroplated copper layer 2. A second electroplated copper layer 3 extending out of the ABF film 4 is stacked and connected to the side wall on the first electroplated copper layer 2. A gold plating layer 5 is connected to the end face of the second electroplated copper layer 3 extending out of the ABF film 4, and the second electroplated copper layer 3 is in a horn-shaped structure.

[0078] The first electroplated copper layer 2 and the second electroplated copper layer 3 are pads led out from the substrate 1, and can also be described as rising copper pillars.

[0079] It has the following advantages:

[0080] 1. By designing the second electroplated copper layer 3 to extend out of the second dry film layer 7, the problem that the ink is higher than the pad can be effectively solved.

[0081] 2. By designing the shape of the second electroplated copper layer 3 into a horn shape, the contact area between the pad and the probe is increased, thereby reducing the chip test difficulty.

[0082] 3. By leading the pad (the first electroplated copper layer 2 and the second electroplated copper layer 3) to the outer layer, the circuit is protected from being accidentally pierced by the probe.

[0083] 4. Using ABF to cover part of the circuit reduces the risk of the circuit being scratched and short-circuited.

[0084] The above description is an explanation of the present invention, not a limitation thereof. For the scope defined by the present invention, refer to the claims. Any form of modification may be made within the protection scope of the present invention.

Claims

1. A method for processing MLO for FCBGA, characterized in that: The steps include: S1. First PTH: firstly, PTH treatment is performed on the substrate (1) to attach a layer of 1-3um copper as the first conductive layer (8); S2, first lamination, first exposure, first development: forming a first dry film layer (9) on the first conductive layer (8) by lamination, and then exposing and developing to expose the position where copper plating is required; S3, electroplating copper: a first electroplated copper layer (2) with a thickness of 16-20 um is plated on the first conductive layer (8) exposed on the first dry film layer (9) to form a pad; S4, first film removal: removing the first dry film layer (9); S5, first flash etching: removing the first conductive layer (8); S6, pressing ABF: pressing a layer of ABF film (4) on the substrate (1); S7, laser treatment and adhesive removal: removing the ABF film (4) on the contact surface of the first electroplated copper layer (2) by laser treatment; S8, second PTH: plating a second conductive layer (6) on the first electroplated copper layer (2) and the ABF film (4); S9, second lamination: laminating a second dry film layer 7 on the second conductive layer (6); S10, second exposure and second development: exposing the first electroplated copper layer (2) to be plated with copper through exposure and development; S11, hole filling electroplating: plating a second electroplated copper layer (3) on the first electroplated copper layer (2); S12, electroplating: plating a gold-plated layer (5) on the second electroplated copper layer (3); S13, second film removal: removing the second dry film layer (7); S14, second flash etching: removing the second conductive layer (6).

2. The method for processing MLO for FCBGA according to claim 1, characterized in that: The opening of the contact surface of the first electroplated copper layer (2) in S7 is in an expanded shape.

3. The method for processing MLO for FCBGA according to claim 1, characterized in that: In the S11, the second electroplated copper layer (3) extends out a second dry film layer (7).

4. The method for processing MLO for FCBGA according to claim 1, characterized in that: Before S2, a pre-treatment is also included, in which the surface of the substrate (1) is cleaned and the copper surface roughness is increased to prepare for the subsequent lamination.

5. An MLO prepared by the processing method of an MLO for FCBGA according to any one of claims 1 to 4, characterized in that: The invention comprises a substrate (1), and a plurality of first electroplated copper layers (2) connected to the upper and lower end surfaces of the substrate (1); an ABF film (4) is attached to the upper and lower end surfaces of the substrate (1) outside the first electroplated copper layers (2); and a second electroplated copper layer (3) extending from the ABF film (4) is laminated and connected to the side wall of the first electroplated copper layer (2).

6. The MLO for FCBGA according to claim 5, characterized in that: The end surface of the second electroplated copper layer (3) extending out of the ABF film (4) is connected to a gold-plated layer (5).

7. The MLO for FCBGA according to claim 5, characterized in that: The second electroplated copper layer (3) is a trumpet-shaped structure.

Citation Information

Patent Citations

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