Power supply circuit, power supply method, and power supply

Abstract

This invention proposes a power supply circuit, power supply method, and power supply. The power supply circuit includes a first clamping circuit, a first power generation circuit, a boost circuit, a second clamping circuit, and a second power generation circuit. The first clamping circuit outputs a first clamping voltage based on the input power supply voltage. The first power generation circuit is coupled to both the first and second clamping circuits and generates a first supply voltage based on the first and second clamping voltages to power the boost circuit. The boost circuit outputs a boost voltage based on the first supply voltage. The second clamping circuit outputs a second clamping voltage based on the boost voltage. The second power generation circuit outputs a second supply voltage based on the second clamping voltage as the supply voltage. This invention provides a power supply circuit, power supply method, and power supply that effectively achieves stable power supply to the chip under a wide input power supply voltage range.

Description

Technical Field

[0001] This invention belongs to the field of power electronics technology, and relates to a power supply technology, particularly a power supply circuit, power supply method and power supply. Background Technology

[0002] Normally, a chip has only one input power supply voltage. When a chip requires multiple different power supply voltages, a dedicated power supply circuit needs to be designed to power different circuits or devices. For example, when the input power supply voltage is greater than 5V or even tens of volts, a dedicated power supply circuit needs to be designed to power the chip's internal 5V circuit. Because the 5V circuit uses 5V devices, the voltage of its power supply circuit needs to be less than or equal to 5V. Too high a voltage will damage the devices, causing the chip to malfunction.

[0003] like Figure 1 As shown, the existing power supply circuit includes a resistor R1, a Zener diode D1, and a metal-oxide-semiconductor field-effect transistor M1 (MOSFET). The first terminal of resistor R1 is connected to the input power supply voltage VIN, the second terminal of resistor R1 is coupled to one end of the Zener diode D1, and the other end of the Zener diode D1 is coupled to ground. The cathode of the Zener diode D1 is coupled to the gate of the MOSFET, and the source of the MOSFET acts as a follower, outputting VCC. When the input power supply voltage VIN is high, the voltage obtained is the Zener diode's regulated voltage minus VGS, thus supplying power to the 5V circuit. However, when the input power supply voltage is only 2.5V, assuming VGS = 1V, the voltage supplying the 5V circuit is only 1.5V. This voltage will cause most of the 5V circuitry within the chip to malfunction, thus failing to meet the requirement of a low input power supply voltage.

[0004] Therefore, a power supply circuit would be ideal if, when the input voltage is 2.5V, it could directly supply 2.5V to the 5V circuit; and when the input voltage is greater than 5V, it could output a supply voltage less than or equal to 5V. Only such a power supply circuit could meet the design requirement that the chip can still operate normally with a wide input voltage range.

[0005] In view of this, there is a need to provide a new structure or control method to solve at least some of the above problems. Summary of the Invention

[0006] In view of one or more problems in the prior art, the present invention proposes a power supply circuit, a power supply method thereon, and a power supply.

[0007] According to one aspect of the present invention, a power supply circuit is disclosed, the power supply circuit comprising:

[0008] The first clamping circuit has its input terminal coupled to the input power supply voltage and is used to output the first clamping voltage according to the input power supply voltage.

[0009] The first power supply generation circuit has a first input terminal coupled to the output terminal of the first clamping circuit and a second input terminal coupled to the output terminal of the second clamping circuit. It is used to generate a first power supply voltage based on the first clamping voltage and the second clamping voltage to supply power to the boost circuit. The first power supply voltage is positively correlated with the second clamping voltage for at least a period of time.

[0010] The boost circuit has its input terminal coupled to the output terminal of the first power generation circuit, and is used to output a boost voltage according to the first power supply voltage. The boost voltage is greater than the first power supply voltage.

[0011] The second clamping circuit, whose input is coupled to the output of the boost circuit, is used to output a second clamping voltage based on the boosted voltage; and

[0012] The second power supply generation circuit has its input terminal coupled to the output terminal of the second clamping circuit, and is used to output a second power supply voltage based on the second clamping voltage as the power supply voltage.

[0013] As one embodiment of the present invention, the boost circuit includes a boost circuit or a charge pump circuit.

[0014] In one embodiment of the present invention, the charge pump circuit includes:

[0015] Bias current generation circuit, used to generate bias current;

[0016] A clock signal generation circuit, whose input is coupled to the output of a bias current generation circuit, is used to output a clock signal; and,

[0017] The charge pump module receives a first supply voltage at its first input terminal and a clock signal at its second input terminal to generate a boost voltage based on the first supply voltage.

[0018] In one embodiment of the present invention, the first power supply generation circuit includes:

[0019] The third transistor has its control terminal coupled to the output terminal of the first clamping circuit, its first terminal coupled to the input power supply voltage, and its second terminal outputting the first supply voltage; and

[0020] The fourth transistor has its control terminal coupled to the output terminal of the second clamping circuit, its first terminal coupled to the input power supply voltage, and its second terminal coupled to the second terminal of the third transistor.

[0021] In one embodiment of the present invention, the second clamping circuit includes:

[0022] The second Zener diode has its cathode coupled to the output of the boost circuit; and

[0023] The second transistor has its control terminal coupled to the anode of the second Zener diode and the first terminal of the second transistor, respectively, and its second terminal is coupled to ground.

[0024] In one embodiment of the present invention, the first power supply generation circuit includes:

[0025] The third transistor has its control terminal coupled to the output terminal of the first clamping circuit, its first terminal used to couple to the input power supply voltage, and its second terminal used to output the first power supply voltage.

[0026] The fourth transistor has its control terminal coupled to the output terminal of the second clamping circuit, its first terminal coupled to the input power supply voltage, and its second terminal coupled to the second terminal of the third transistor.

[0027] The fifth transistor has its control terminal coupled to the output terminal of the first clamping circuit, its first terminal coupled to the input power supply voltage, and its second terminal coupled to the output of the third power supply voltage; and

[0028] The sixth transistor has its control terminal coupled to the output terminal of the second clamping circuit, its first terminal coupled to the input power supply voltage, and its second terminal coupled to the second terminal of the fifth transistor.

[0029] In one embodiment of the present invention, the first power supply generation circuit is further configured to generate a third power supply voltage based on the first clamping voltage and the second clamping voltage to power the bias current generation circuit, wherein the third power supply voltage is positively correlated with the second clamping voltage for at least a period of time; the first power supply voltage is used to power the clock signal generation circuit and the charge pump module respectively.

[0030] In one embodiment of the present invention, the second clamping circuit further includes a filter circuit, which includes a fourth resistor and a third capacitor. The first end of the fourth resistor is coupled to the cathode of the second Zener diode, the first end of the third capacitor is coupled to the second end of the fourth resistor, and the second end of the third capacitor is coupled to ground.

[0031] According to another aspect of the present invention, a power supply is disclosed, the power supply including a power supply circuit as described in any of the preceding claims, the power supply circuit being used to supply power to a chip in the power supply.

[0032] According to another aspect of the present invention, a power supply method is disclosed, the power supply method being used to control a power supply circuit, the power supply method comprising:

[0033] The first clamping voltage is output by clamping the input power supply voltage;

[0034] The system receives a first clamping voltage and a second clamping voltage, and generates a first supply voltage based on the first clamping voltage and the second clamping voltage. The first supply voltage is positively correlated with the second clamping voltage for at least a period of time.

[0035] The boost voltage is output based on the first supply voltage, and the boost voltage is greater than the first supply voltage.

[0036] Clamp the boost voltage to output a second clamp voltage; and

[0037] The second supply voltage is output based on the second clamping voltage as the supply voltage.

[0038] As one embodiment of the present invention, the step of outputting a boost voltage based on a first supply voltage includes:

[0039] Generate bias current and obtain clock signal;

[0040] The voltage is boosted based on the first supply voltage to output a boosted voltage.

[0041] In one embodiment of the present invention, the power supply circuit includes a charge pump circuit, which includes a bias current generation circuit, a clock signal generation circuit, and a charge pump module. The power supply method further includes:

[0042] A third supply voltage is generated based on the first clamping voltage and the second clamping voltage to power the bias current generation circuit. The third supply voltage is positively correlated with the second clamping voltage for at least a period of time. The first supply voltage is used to power the clock signal generation circuit and the charge pump module, respectively.

[0043] This invention proposes a power supply circuit, a power supply method, and a power supply power source. The power supply circuit includes a first clamping circuit, a first power generation circuit, a boost circuit, a second clamping circuit, and a second power generation circuit. The input terminal of the first clamping circuit is coupled to an input power supply voltage, and the first clamping circuit outputs a first clamping voltage based on the input power supply voltage. The first input terminal of the first power generation circuit is coupled to the output terminal of the first clamping circuit, and the second input terminal of the first power generation circuit is coupled to the output terminal of the second clamping circuit. The first power generation circuit generates a first supply voltage based on the first clamping voltage and the second clamping voltage to power the boost circuit. The first supply voltage is positively correlated with the second clamping voltage for at least a certain period of time. The input terminal of the boost circuit is coupled to the output terminal of the first power generation circuit, and the boost circuit outputs a boosted voltage based on the first supply voltage, the boosted voltage being greater than the first supply voltage. The input terminal of the second clamping circuit is coupled to the output terminal of the boost circuit, and the second clamping circuit outputs a second clamping voltage based on the boosted voltage. The input terminal of the second power supply generation circuit is coupled to the output terminal of the second clamping circuit. The second power supply generation circuit is used to output a second power supply voltage based on the second clamping voltage as the power supply voltage. The power supply circuit, power supply method, and power supply proposed in this invention effectively achieve stable power supply to the chip under wide input power supply voltage range operating conditions. Attached Figure Description

[0044] The accompanying drawings are provided to further illustrate the invention and, together with the description, serve to explain embodiments of the invention, but do not constitute a limitation thereof. In the drawings:

[0045] Figure 1 A schematic diagram of the circuit structure of a prior art power supply circuit is shown;

[0046] Figure 2 A schematic diagram of the circuit structure of a power supply circuit according to an embodiment of the present invention is shown;

[0047] Figure 3 A schematic diagram of the circuit structure of a power supply circuit according to another embodiment of the present invention is shown;

[0048] Figure 4 A schematic diagram of the circuit structure of a power supply circuit according to another embodiment of the present invention is shown;

[0049] Figure 5 A flowchart illustrating the steps of a power supply method according to an embodiment of the present invention is shown. Detailed Implementation

[0050] To further understand the present invention, preferred embodiments of the present invention are described below in conjunction with examples. However, it should be understood that these descriptions are only for further illustrating the features and advantages of the present invention, and not for limiting the scope of the claims of the present invention.

[0051] The description in this section pertains to only a few typical embodiments, and the present invention is not limited to the scope of the embodiments described. Combinations of different embodiments, substitution of some technical features in different embodiments, and substitution of similar or identical prior art with some technical features in the embodiments are also within the scope of the description and protection of the present invention.

[0052] The terms "coupled" or "connected" in this specification include both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as a connection through an electrically conductive medium like a conductor, which may contain parasitic inductance or capacitance. It can also be a connection through intermediate circuits or components described in the embodiments of this specification. Indirect connections may also include connections through other active or passive devices that achieve the same or similar functions, such as connections through switches, signal amplification circuits, follower circuits, or other circuits or components. "A plurality of" or "more" indicates two or more. Furthermore, in this invention, terms such as "first" and "second" are primarily used to distinguish one technical feature from another, and do not necessarily require or imply any actual relationship or order between these technical features.

[0053] like Figure 2As shown, an embodiment of the present invention discloses a power supply circuit, which includes a first clamping circuit 10, a first power generation circuit 11, a boost circuit 12, a second clamping circuit 13, and a second power generation circuit 14. The input terminal of the first clamping circuit 10 is coupled to an input power supply voltage VIN, and the first clamping circuit 10 is used to clamp the input power supply voltage to obtain a first clamping voltage. The first input terminal of the first power generation circuit 11 is coupled to the output terminal of the first clamping circuit 10, and the second input terminal of the first power generation circuit 11 is coupled to the output terminal of the second clamping circuit 14. The first power generation circuit 11 is used to generate a first power supply voltage based on the first clamping voltage and the second clamping voltage to power the boost circuit. The first power supply voltage is positively correlated with the second clamping voltage for at least a certain period of time. The input terminal of the boost circuit 12 is coupled to the output terminal of the first power generation circuit 11, and the boost circuit 12 is used to output a boost voltage based on the first power supply voltage. The boost voltage is K times the first power supply voltage, where K>1, that is, the boost voltage is greater than the first power supply voltage. The input terminal of the second clamping circuit 13 is coupled to the output terminal of the boost circuit, and the second clamping circuit 13 is used to output a second clamping voltage according to the boost voltage. The input terminal of the second power supply generation circuit 14 is coupled to the output terminal of the second clamping circuit 13, and the second power supply generation circuit 14 is used to output a second power supply voltage as the power supply voltage VCC according to the second clamping voltage.

[0054] In one specific embodiment, the first power supply generation circuit 11 obtains an initial first power supply voltage based on a first clamping voltage. This first power supply voltage powers the boost circuit 12, which in turn boosts the voltage based on the first power supply voltage to obtain a boosted voltage. The second clamping circuit clamps the boosted voltage to obtain a second clamping voltage. The first power supply generation circuit generates the first power supply voltage based on the first and second clamping voltages. As the second clamping voltage gradually increases, the first power supply voltage is positively correlated with the second clamping voltage for at least a certain period. In one embodiment, when the second clamping voltage is higher than the first clamping voltage, the first power supply voltage will gradually increase until a preset voltage is reached. In another embodiment, through the circuit configuration of the first power supply generation circuit, the increase in the first power supply voltage is not limited by the magnitude relationship between the second and first clamping voltages.

[0055] like Figure 3As shown, an embodiment of the present invention discloses a power supply circuit, which includes a first clamping circuit 20, a first power generation circuit 21, a boost circuit 22, a second clamping circuit 23, and a second power generation circuit. The first clamping circuit 20 includes a first resistor R1 and a first Zener diode D1. The first terminal of the first resistor R1 is coupled to the input power supply voltage VIN, the cathode of the first Zener diode is coupled to the second terminal of the first resistor R1, and the anode of the first Zener diode is grounded. The specific circuit of the first clamping circuit can be selected according to the needs of the actual circuit to obtain the required first clamping voltage. The first power generation circuit 21 includes a third transistor M3 and a fourth transistor M4. The control terminal of the third transistor M3 is coupled to the cathode of the first Zener diode D1 to obtain the first clamping voltage. The first terminal of the third transistor M3 is coupled to the input power supply voltage VIN, and the second terminal of the third transistor M3 is used to output the first power supply voltage V1. The control terminal of the fourth transistor M4 is coupled to the output terminal of the second clamping circuit 23. The first terminal of the fourth transistor M4 is coupled to the input power supply voltage VIN, and the second terminal of the fourth transistor M4 is coupled to the second terminal of the third transistor M3.

[0056] like Figure 3 As shown, the boost circuit 22 includes a charge pump circuit, which comprises a bias current generation circuit 221, a clock signal generation circuit 222, and a charge pump module 223. The bias current generation circuit 221 generates a bias current to charge and discharge the capacitor in the clock signal generation circuit. The input terminal of the clock signal generation circuit 222 is coupled to the output terminal of the bias current generation circuit 221, and the clock signal generation circuit 222 outputs a clock signal CLK. The first input terminal of the charge pump module 223 receives a first supply voltage V1, and the second input terminal of the charge pump module 223 receives the clock signal CLK. The charge pump module 223 boosts the first supply voltage V1 to generate a boost voltage CP_OUT. The charge pump module 223 periodically supplies charge to the output terminal of the power supply circuit according to the clock signal CLK. In a first state, the charge pump circuit charges the capacitor in the charge pump module; in a second state, the charge pump circuit transfers the charge on the capacitor in the charge pump module to the output terminal of the power supply circuit. The first power supply voltage V1 supplies power to the bias current generation circuit 221, the clock signal generation circuit 222, and the charge pump module 223, respectively.

[0057] In another embodiment of the present invention, the boost circuit includes a boost circuit, which boosts the first supply voltage to generate a boost voltage. The boost circuit is a common topology and will not be described in detail here.

[0058] like Figure 3In one embodiment shown, the second clamping circuit 23 includes a second Zener diode D2 and a second transistor M2. The cathode of the second Zener diode D2 is coupled to the output of the boost circuit 22 to receive the boost voltage CP_OUT. The control terminal of the second transistor M2 is coupled to the anode of the second Zener diode D2 and the first terminal of the second transistor M2, respectively, and the second terminal of the second transistor M2 is grounded. The second power generation circuit includes a first transistor M1. The control terminal of the first transistor M1 is coupled to the output of the second clamping circuit. The first terminal of the first transistor M1 is coupled to the input power supply voltage VIN, and the second terminal of the first transistor M1 outputs a second power supply voltage as the power supply voltage VCC. The power supply voltage VCC can be used to power the chip itself or the internal circuits within the chip.

[0059] like Figure 4 As shown, an embodiment of the present invention discloses a power supply circuit. The power supply circuit includes a first clamping circuit, a first power generation circuit 31, a boost circuit, a second clamping circuit, and a second power generation circuit. The first power generation circuit 31 includes a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6. The control terminal of the third transistor M3 is coupled to the output terminal of the first clamping circuit. The first terminal of the third transistor M3 is coupled to the input power supply voltage VIN, and the second terminal of the third transistor M3 is used to output a first power supply voltage V1, which is used to power the clock signal generation circuit and the charge pump module. The control terminal of the fourth transistor M4 is coupled to the output terminal of the second clamping circuit. The first terminal of the fourth transistor M4 is coupled to the input power supply voltage VIN, and the second terminal of the fourth transistor M4 is coupled to the second terminal of the third transistor M3. The control terminal of the fifth transistor M5 is coupled to the output terminal of the first clamping circuit. The first terminal of the fifth transistor M5 is coupled to the input power supply voltage VIN, and the second terminal of the fifth transistor M5 is used to output a third power supply voltage V3, which is used to power the bias current generation circuit. The control terminal of the sixth transistor M6 is coupled to the output terminal of the second clamping circuit. The first terminal of the sixth transistor M6 is coupled to the input power supply voltage VIN, and the second terminal of the sixth transistor M6 is coupled to the second terminal of the fifth transistor M5. The clock signal generation circuit and the charge pump module generate a periodic clock signal CLK, which affects the first supply voltage V1, causing it to glitches; that is, the first supply voltage V1 is not very stable. If the first supply voltage V1 is used to power the bias current generation circuit, it will affect the normal operation of the bias current generation circuit. Using the third supply voltage V3 to independently power the bias current generation circuit can effectively improve the stability of its operation.

[0060] In embodiments of the present invention, the first transistor, second transistor, third transistor, fourth transistor, fifth transistor, and sixth transistor can be any one of a bipolar junction transistor (BJT), a metal-oxide-semiconductor field-effect transistor (MOS transistor), and a junction field-effect transistor (JFET). In one embodiment, exemplaryly, the first transistor is a bipolar junction transistor (BJT), with its control terminal being the base, its first terminal being the collector, and its second terminal being the emitter. In another embodiment, the first transistor is a MOS transistor, with its control terminal being the gate, its first terminal being the drain, and its second terminal being the source. In one embodiment, the first transistor is an N-type MOS transistor. Preferably, the first, second, third, fourth, fifth, and sixth transistors are all enhancement-mode field-effect transistors (EMTs). In another preferred embodiment, the first, third, fourth, fifth, and sixth transistors are high-voltage MOS transistors.

[0061] like Figure 4 As shown, the second clamping circuit further includes a filter circuit, which includes a fourth resistor R4 and a third capacitor C3. The first end of the fourth resistor R4 is coupled to the cathode of the second Zener diode, the first end of the third capacitor C3 is coupled to the second end of the fourth resistor R4, and the second end of the third capacitor C3 is coupled to ground. Preferably, the second clamping circuit further includes a third resistor R3 and a second capacitor C2. The third resistor R3 is coupled between the boost circuit and the second Zener diode D2. The first end of the second capacitor C2 is coupled to the cathode of the second Zener diode D2, and the second end of the second capacitor C2 is coupled to ground. In another embodiment, the first clamping circuit further includes a second resistor R2 and a first capacitor C1. The first end of the second resistor R2 is coupled to the cathode of the first Zener diode D1, the first end of the first capacitor C1 is coupled to the second end of the second resistor, and the second end of the first capacitor C1 is coupled to ground.

[0062] In one embodiment of the present invention, combined with Figure 4When the input power supply voltage VIN is 2.5V, assuming that the VGS of transistors M1-M6 are all 1V, then the initial first supply voltage V1 and the third supply voltage V3 are both 1.5V. At this time, the bias current generation circuit receives power and starts working, providing the bias current required for the clock signal generation circuit to operate. Then, the clock signal generation circuit starts working, generating the clock signal CLK, and outputting the clock signal CLK to the charge pump module. In one embodiment, the boost voltage output by the charge pump module is twice the first supply voltage, that is, the boost voltage is 3V at this time. The voltage VGATE obtained after the filtering circuit is also 3V, so the second clamping voltage is 3V at this time. Since the VGS of the fourth transistor M4 and the sixth transistor M6 is 1V, the first supply voltage V1 and the third supply voltage V3 can be boosted to 2V, which is higher than the previous 1.5V. This is a positive feedback process. After the first supply voltage V1 and the third supply voltage V3 rise to 2V, the boost circuit will further increase the boost voltage to 4V, causing the first supply voltage V1 and the third supply voltage V3 to rise again. Ultimately, the first supply voltage V1 and the third supply voltage V3 will approach 2.5V (i.e., the input power supply voltage). Simultaneously, the supply voltage VCC output by the first transistor M1 through the voltage VGATE will also be 2.5V.

[0063] Similarly, when the input power supply voltage is less than 5V, the above positive feedback process also holds true, resulting in VCC = VIN. However, when the input power supply voltage is greater than 5V, such as Figure 4 The voltage VZ at the point is clamped by the second Zener diode and the second transistor, at which point both VZ and VGATE are 6V. Therefore, the first supply voltage V1 and the third supply voltage V3 can only reach a maximum of 5V. The VGS of the first transistor is 1V, so the second supply voltage (i.e., the supply voltage VCC) output by the first transistor can only reach a maximum of 5V. In this embodiment, only the bias current generation circuit, the clock signal generation circuit, and the charge pump module need to be able to operate at 1.5V, without requiring all other circuits to operate at a 1.5V supply voltage. Compared with existing technologies, this invention can still ensure that the power supply circuit has sufficient voltage to operate the 5V circuit even with a low input power supply voltage, and effectively achieves stable power supply to the chip in a wide input power supply voltage range operating scenario. The above embodiments are only used to further illustrate the implementation principle of this invention. Those skilled in the art can obtain specific circuit structures based on this invention and combined with actual power supply voltage requirements, all of which fall within the protection scope of this technical solution.

[0064] Another embodiment of the present invention discloses a power supply, which includes a power supply circuit as described in any of the preceding claims. The power supply circuit outputs a second power supply voltage as the power supply voltage, and supplies power to the chip in the power supply using the power supply voltage VCC. In a specific embodiment, the power supply circuit supplies power to the chip itself and / or the internal circuitry within the chip.

[0065] like Figure 5 As shown, another embodiment of the present invention also discloses a power supply method, which is used to control a power supply circuit. The power supply method includes:

[0066] Step S100: Clamp the input power supply voltage to output a first clamping voltage;

[0067] Step S200: Receive the first clamping voltage and the second clamping voltage, and generate a first supply voltage based on the first clamping voltage and the second clamping voltage. The first supply voltage is positively correlated with the second clamping voltage for at least a period of time.

[0068] Step S300: Output a boost voltage based on the first supply voltage, the boost voltage being greater than the first supply voltage;

[0069] Step S400: Clamp the boost voltage to output a second clamp voltage; and

[0070] Step S500: Output a second supply voltage based on the second clamping voltage as the supply voltage.

[0071] In one embodiment, the step of outputting a boost voltage based on a first supply voltage includes: generating a bias current and obtaining a clock signal; boosting the voltage based on the first supply voltage to output a boost voltage. In a specific embodiment, a bias current generation circuit is controlled to generate a bias current. Based on the bias current, a clock signal generation circuit outputs a clock signal to obtain a clock signal, and a charge pump module receives the clock signal and generates a boost voltage based on the first supply voltage.

[0072] In another embodiment, the power supply circuit includes a charge pump circuit, which includes a bias current generation circuit, a clock signal generation circuit, and a charge pump module. The power supply method further includes: generating a third power supply voltage based on a first clamping voltage and a second clamping voltage to power the bias current generation circuit. The third power supply voltage is positively correlated with the second clamping voltage for at least a period of time. The first power supply voltage is used to power the clock signal generation circuit and the charge pump module, respectively.

[0073] Those skilled in the art should know that the logic controls such as "high level" and "low level", "set" and "reset", "AND gate" and "OR gate", "non-inverting input" and "inverting input" in the logic control involved in the specification or drawings can be interchanged or changed, and the same function or purpose as the above embodiment can be achieved by adjusting the subsequent logic control.

[0074] The description and application of the present invention herein are illustrative and not intended to limit the scope of the invention to the embodiments described above. The effects or advantages described in the specification may not be apparent in actual experimental cases due to uncertainties in specific conditions or other factors, and such descriptions are not intended to limit the scope of the invention. Variations and modifications to the embodiments disclosed herein are possible, and various substitutions and equivalents of the components in the embodiments are well known to those skilled in the art. It should be understood by those skilled in the art that the invention can be implemented in other forms, structures, arrangements, proportions, and with other components, materials, and parts without departing from the spirit or essential characteristics of the invention. Other variations and modifications can be made to the embodiments disclosed herein without departing from the scope and spirit of the invention.

Claims

1. A power supply circuit, characterized in that, The power supply circuit includes: The first clamping circuit has its input terminal coupled to the input power supply voltage and is used to output the first clamping voltage according to the input power supply voltage. The first power supply generation circuit has a first input terminal coupled to the output terminal of the first clamping circuit and a second input terminal coupled to the output terminal of the second clamping circuit. It is used to generate a first power supply voltage based on the first clamping voltage and the second clamping voltage to supply power to the boost circuit. The first power supply voltage is positively correlated with the second clamping voltage for at least a period of time. The boost circuit has its input terminal coupled to the output terminal of the first power generation circuit, and is used to output a boost voltage according to the first power supply voltage. The boost voltage is greater than the first power supply voltage. The second clamping circuit, whose input is coupled to the output of the boost circuit, is used to output a second clamping voltage based on the boosted voltage; and The second power supply generation circuit has its input terminal coupled to the output terminal of the second clamping circuit, and is used to output a second power supply voltage based on the second clamping voltage as the power supply voltage.

2. The power supply circuit as described in claim 1, characterized in that, The boost circuit includes a boost circuit or a charge pump circuit.

3. The power supply circuit as described in claim 2, characterized in that, The charge pump circuit includes: Bias current generation circuit, used to generate bias current; A clock signal generation circuit, whose input is coupled to the output of a bias current generation circuit, is used to output a clock signal; and, The charge pump module receives a first supply voltage at its first input terminal and a clock signal at its second input terminal to generate a boost voltage based on the first supply voltage.

4. The power supply circuit as described in claim 1, characterized in that, The first power generation circuit includes: The third transistor has its control terminal coupled to the output terminal of the first clamping circuit, its first terminal coupled to the input power supply voltage, and its second terminal outputting the first supply voltage; and The fourth transistor has its control terminal coupled to the output terminal of the second clamping circuit, its first terminal coupled to the input power supply voltage, and its second terminal coupled to the second terminal of the third transistor.

5. The power supply circuit as described in claim 1, characterized in that, The second clamping circuit includes: The second Zener diode has its cathode coupled to the output of the boost circuit; and The second transistor has its control terminal coupled to the anode of the second Zener diode and the first terminal of the second transistor, respectively, and its second terminal is coupled to ground.

6. The power supply circuit as described in claim 1, characterized in that, The first power generation circuit includes: The third transistor has its control terminal coupled to the output terminal of the first clamping circuit, its first terminal used to couple to the input power supply voltage, and its second terminal used to output the first power supply voltage. The fourth transistor has its control terminal coupled to the output terminal of the second clamping circuit, its first terminal coupled to the input power supply voltage, and its second terminal coupled to the second terminal of the third transistor. The fifth transistor has its control terminal coupled to the output terminal of the first clamping circuit, its first terminal coupled to the input power supply voltage, and its second terminal coupled to the output of the third power supply voltage; and The sixth transistor has its control terminal coupled to the output terminal of the second clamping circuit, its first terminal coupled to the input power supply voltage, and its second terminal coupled to the second terminal of the fifth transistor.

7. The power supply circuit as described in claim 3, characterized in that, The first power supply generation circuit is also used to generate a third power supply voltage based on the first clamping voltage and the second clamping voltage to power the bias current generation circuit. The third power supply voltage is positively correlated with the second clamping voltage for at least a period of time. The first power supply voltage is used to power the clock signal generation circuit and the charge pump module, respectively.

8. The power supply circuit as described in claim 5, characterized in that, The second clamping circuit also includes a filter circuit, which includes a fourth resistor and a third capacitor. The first end of the fourth resistor is coupled to the cathode of the second Zener diode, the first end of the third capacitor is coupled to the second end of the fourth resistor, and the second end of the third capacitor is coupled to ground.

9. A power supply, characterized in that, The power supply includes a power supply circuit as described in any one of claims 1-8, the power supply circuit being used to supply power to the chip in the power supply.

10. A power supply method for controlling a power supply circuit, characterized in that, The power supply method includes: The first clamping voltage is output by clamping the input power supply voltage; The system receives a first clamping voltage and a second clamping voltage, and generates a first supply voltage based on the first clamping voltage and the second clamping voltage. The first supply voltage is positively correlated with the second clamping voltage for at least a period of time. The boost voltage is output based on the first supply voltage, and the boost voltage is greater than the first supply voltage. Clamp the boost voltage to output a second clamp voltage; and The second supply voltage is output based on the second clamping voltage as the supply voltage.

11. The power supply method as described in claim 10, characterized in that, The step of outputting a boost voltage based on the first supply voltage includes: Generate bias current and obtain clock signal; The voltage is boosted based on the first supply voltage to output a boosted voltage.

12. The power supply method as described in claim 10, characterized in that, The power supply circuit includes a charge pump circuit, which comprises a bias current generation circuit, a clock signal generation circuit, and a charge pump module. The power supply method further includes: A third supply voltage is generated based on the first clamping voltage and the second clamping voltage to power the bias current generation circuit. The third supply voltage is positively correlated with the second clamping voltage for at least a period of time. The first supply voltage is used to power the clock signal generation circuit and the charge pump module, respectively.

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