Drive circuit for power transistor

Abstract

The present disclosure provides a driving circuit of a power transistor, which controls the charging current of a control terminal node of the power transistor to be a constant value during the power-on of a power supply voltage by a first switch branch to provide a gate driving voltage, and mirrors the potential of a switch node in the second switch branch to the control terminal node during the power-on of the power supply voltage by a second switch branch, wherein the output voltage changes linearly with a constant rising slope / constant falling slope in the on and off states of the first switch branch during the power-on of the power supply voltage, so as to provide an output voltage with a fixed slope linear change, to meet the application requirements while protecting the power transistor and avoiding damage to the power transistor due to the rapid change of the source-drain voltage during the opening / closing switching.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and specifically to a driving circuit for a power transistor. Background Technology

[0002] Power switching transistors are widely used in various power management systems and are an important component of power supply and system monitoring products. In power management systems, metal-oxide-semiconductor field-effect transistors (MOSFETs) are generally selected, and a stable output voltage is provided by adjusting the linear impedance of the power switching transistor. In some applications, it is necessary for the power switching transistor to provide a linear rise / fall output voltage.

[0003] Figure 1 This illustrates a power transistor drive circuit in the prior art, such as... Figure 1 As shown, the driving circuit 100 includes: transistors Mp1 and Mn1 connected in series between the power supply terminal and ground, and capacitor C. VDD In this configuration, the power transistor Mpower is the main switch, and the connection node between transistors Mp1 and Mn1 provides the gate drive voltage V for the power transistor Mpower. G Capacitor C VDD One end of the transistor is connected to the power supply terminal, connected to the power supply voltage VDD, and the other end is grounded, connected to the common ground voltage VSS. The drain of the power transistor Mpower serves as the output terminal Output to provide the output voltage, and its source terminal is grounded. The gate terminals of transistors Mp1 and Mn1 together serve as the input terminal Inout. The capacitor C... GD This refers to the gate-drain parasitic capacitance of the power transistor Mpower.

[0004] Figure 2a and Figure 2b The gate voltage V of the power transistor Mpower is shown when it is turned on and off. G and drain voltage V D A schematic diagram showing the curve of voltage change over time. The gate voltage V is shown when the power transistor Mpower is turned on / off. G Both voltages remain constant for a period of time. This plateau where the voltage remains constant is called the Miller plateau. The voltage of the Miller plateau is approximately the threshold voltage Vth of the power transistor Mpower.

[0005] If the on-resistance of transistor Mp1 is Rp1 and the on-resistance of transistor Mn1 is Rn1, then Figure 2a The drain voltage V output from the middle D The decreasing slope is Sfalling=(VDD-Vth) / Rp1 / C GDBecause (VDD-Vth) varies greatly, the slope reduction Sfalling also varies greatly, which cannot meet the application requirements. Figure 2b The drain voltage V output from the middle D The slope of the ascent is Srising = Vth / Rn1 / C GD If the power supply voltage VDD approaches 0V and Rn1 approaches infinity, the rising slope (Srising) will vary greatly, which will also fail to meet the application requirements.

[0006] The shortcoming of existing power transistor drive circuits is that they cannot guarantee that the output voltage changes linearly with a fixed slope during application. Summary of the Invention

[0007] To address the aforementioned technical problems, this disclosure provides a driving circuit for a power transistor.

[0008] This disclosure provides a driving circuit for a power transistor, which provides an output voltage under the control of a gate drive voltage. The driving circuit includes:

[0009] The first switching branch, coupled between the input terminal and the first terminal of the power transistor, is used to control the charging current of the control terminal node of the power transistor to a constant value during the power supply voltage supply period, so as to provide the aforementioned gate drive voltage.

[0010] The second switching branch, coupled between the input terminal and the first terminal of the power transistor, is used to mirror the switching node potential in the second switching branch to the control terminal node during power-up of the power supply voltage.

[0011] An operational amplifier, with its positive input connected to a switching node and its negative input connected to a control node, is used to compare the aforementioned switching node potential with the gate drive voltage to generate an error signal.

[0012] Specifically, during the power-on and power-off states of the first switching branch, the output voltage maintains a linear change with a constant rising slope / constant falling slope.

[0013] Preferably, the first terminal of the aforementioned power transistor is connected to a common ground voltage, and the second terminal is used to provide the output voltage.

[0014] When the power transistor is in the ON state, the output voltage changes linearly with a constant decreasing slope; when the power transistor is in the OFF state, the output voltage changes linearly with a constant increasing slope.

[0015] Preferably, the first terminal of the aforementioned power transistor is used to provide the output voltage, and the second terminal is connected to a preset supply voltage.

[0016] When the power transistor is in the ON state, the output voltage changes linearly with a constant rising slope; when the power transistor is in the OFF state, the output voltage changes linearly with a constant falling slope.

[0017] Preferably, the aforementioned first switch branch includes:

[0018] A first transistor and a first resistor are connected in series between the input terminal and the first terminal of the power transistor. The connection node of the two is coupled to the control terminal node of the power transistor to provide the aforementioned gate drive voltage, and the control terminal of the first transistor is connected to an error signal.

[0019] A first current source is connected in parallel across the first transistor.

[0020] Preferably, the aforementioned second switch branch includes:

[0021] The second transistor and the second resistor are connected in series between the input terminal and the first terminal of the power transistor. The connection node between the two serves as a switching node, and the control terminal of the second transistor is connected to the aforementioned error signal.

[0022] Preferably, the aforementioned driving circuit further includes:

[0023] The coupling capacitor has its first end connected to the input terminal and connected to the power supply voltage, and its second end connected to the first terminal of the power transistor.

[0024] Preferably, the first transistor and the second transistor have the same width-to-length ratio, and the first resistor and the second resistor have the same specifications.

[0025] Preferably, when the aforementioned power transistor is in the ON state, both the first transistor and the first current source are in the ON working state;

[0026] When the aforementioned power transistor is in the off state, both the first transistor and the first current source are in the off state.

[0027] Preferably, any one of the aforementioned power transistor, the first transistor, and the second transistor is a P-channel metal-oxide-semiconductor field-effect transistor.

[0028] This disclosure provides a driving circuit for a power transistor. During power-up, the driving circuit utilizes a first switching branch to maintain a constant charging current at the control node of the power transistor, providing a gate drive voltage. During power-up, a second switching branch mirrors the potential of its switching node to the control node. An operational amplifier compares the switching node potential and the gate drive voltage to generate an error signal. The first switching branch maintains a linear output voltage with a constant rising slope and a constant falling slope during both on and off states during power-up. This driving circuit clamps the control node voltage of the power transistor using a mirror circuit structure, maintaining a constant current flowing through the control node during power-on and a constant control node potential during power-off. This ensures the output voltage changes linearly with a constant rising slope and a constant falling slope throughout the entire operation of the driving circuit. This approach meets application requirements while protecting the power transistor, preventing damage caused by rapid changes in its source-drain voltage during power transistor switching.

[0029] Moreover, the driving circuit can change the driving mode to upper-tube drive or lower-tube drive by switching the connection state at both ends of the power transistor, thereby improving the applicability of the driving circuit. At the same time, the driving circuit has a simple structure and is easy to operate. Attached Figure Description

[0030] The above and other objects, features and advantages of this disclosure will become clearer from the following description of embodiments of this disclosure with reference to the accompanying drawings.

[0031] Figure 1 A schematic diagram of a power transistor drive circuit in the prior art is shown.

[0032] Figure 2a and Figure 2b Show each Figure 1 The gate voltage V of the medium power transistor Mpower when it is turned on and off G and drain voltage V D A schematic diagram of the curve changing over time;

[0033] Figure 3 A schematic diagram of a power transistor driving circuit provided in an embodiment of the present disclosure is shown in one implementation.

[0034] Figure 4 This diagram illustrates a different embodiment of the power transistor driving circuit provided in this disclosure. Detailed Implementation

[0035] To facilitate understanding of this disclosure, a more complete description will be given below with reference to the accompanying drawings, which illustrate preferred embodiments of the present disclosure. However, this disclosure may be implemented in various forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the contents of this disclosure.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0037] It should be understood that, in the following description, "circuit" refers to a conductive loop consisting of at least one element or sub-circuit connected by an electrical or electromagnetic link. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it can be directly coupled or connected to the other element, or there may be intermediate elements. The connection between elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.

[0038] The present disclosure will now be described in detail with reference to the accompanying drawings.

[0039] Figure 3 The diagram illustrates a schematic representation of one embodiment of the power transistor driving circuit provided in this disclosure. Figure 4 This diagram illustrates a structural schematic of the power transistor drive circuit provided in an embodiment of the present disclosure in another implementation.

[0040] refer to Figure 3 and Figure 4 This disclosure provides a driving circuit 200 for a power transistor M0. The power transistor M0 provides an output voltage Vout under the control of a gate drive voltage VG. The first terminal of the power transistor M0 serves as the source, with its potential denoted as VS; the second terminal serves as the drain, with its potential denoted as VD; and its control terminal serves as the gate, with its potential denoted as VG (i.e., the gate drive voltage). In practice, the power transistor M0 has a parasitic capacitance C between its gate and drain. GD .

[0041] In this embodiment, the driving circuit 200 includes a first switching branch 203, a second switching branch 202, and an operational amplifier 201.

[0042] The first switch branch 203 is coupled between the input terminal and the first terminal of the power transistor M0, and is used to control the charging current of the control terminal node of the power transistor M0 to a constant value during the power supply voltage VDD, so as to provide the aforementioned gate drive voltage VG.

[0043] The second switching branch 202 is coupled between the input terminal and the first terminal of the power transistor M0, and is used to mirror the switching node potential VR in the second switching branch 202 to the control terminal node during the power supply voltage VDD.

[0044] The positive input terminal of the operational amplifier 201 is connected to the aforementioned switching node, and the negative input terminal is connected to the aforementioned control node. It is used to compare the aforementioned switching node potential VR and the gate drive voltage VG to generate an error signal Va.

[0045] Specifically, during the power supply voltage VDD's on and off states, the first switch branch 203 maintains the output voltage Vout in a linear change with a constant rising slope / constant falling slope.

[0046] Furthermore, in this embodiment, the aforementioned first switching branch 203 includes: a first transistor Mp2 and a first resistor R2, as well as a first current source I1.

[0047] The first transistor Mp2 and the first resistor R2 are connected in series between the input terminal and the first terminal of the power transistor M0. The connection node of the two is coupled to the control terminal node of the power transistor M0 to provide the aforementioned gate drive voltage VG. The control terminal of the first transistor Mp2 is connected to the error signal Va. The first current source I1 is connected in parallel across the two ends of the first transistor Mp2.

[0048] Furthermore, in this embodiment, the aforementioned second switch branch 202 includes:

[0049] The second transistor Mp1 and the second resistor R1 are connected in series between the input terminal and the first terminal of the power transistor M0. The connection node of the two serves as a switching node, and the control terminal of the second transistor Mp1 is connected to the aforementioned error signal Va.

[0050] Furthermore, in this embodiment, the aforementioned driving circuit 200 further includes:

[0051] The coupling capacitor C1 has its first end connected to the input terminal and connected to the power supply voltage VDD, and its second end connected to the first end of the power transistor M0.

[0052] Furthermore, in this embodiment, the aforementioned power transistor M0 is in the on state, and both the first transistor Mp2 and the first current source I1 are in the on working state.

[0053] When the aforementioned power transistor M0 is in the off state, both the first transistor Mp2 and the first current source I1 are in the off state.

[0054] Furthermore, in this embodiment, any one of the aforementioned power transistor M0, the first transistor Mp2, and the second transistor Mp1 is a P-channel metal-oxide-semiconductor field-effect transistor (MOSFET, hereinafter referred to as MOS transistor).

[0055] Furthermore, such as Figure 3 As shown, in this embodiment, the first terminal of the aforementioned power transistor M0 is connected to the common ground voltage VSS, and the second terminal is used to provide the output voltage Vout. The driving circuit 200 is a lower transistor driving circuit. When the power transistor M0 is in the on state, the output voltage Vout changes linearly with a constant decreasing slope; when the power transistor M0 is in the off state, the output voltage Vout changes linearly with a constant increasing slope.

[0056] Furthermore, such as Figure 4 As shown, in this embodiment, the first terminal of the aforementioned power transistor M0 is used to provide the output voltage Vout, and the second terminal is connected to a preset power supply voltage VM. The driving circuit 200 is an upper transistor driving circuit. When the power transistor M0 is in the conducting state, the output voltage Vout changes linearly with a constant rising slope; when the power transistor M0 is in the off state, the output voltage Vout changes linearly with a constant falling slope.

[0057] Therefore, the driving circuit 200 can change the driving mode of the driving circuit 200 to upper tube driving or lower tube driving by switching the connection state of the two ends of the power transistor M0, thereby improving the applicability of the driving circuit 200. At the same time, the driving circuit 200 has a simple structure and is easy to operate.

[0058] Specifically, in this embodiment, the improved lower transistor drive circuit is as follows: Figure 3 As shown, the first transistor Mp2 and the second transistor Mp1 have the same width-to-length ratio, and the first resistor R2 and the second resistor R1 have the same specifications. The operational amplifier 201 locks the switching node potential VR and the control terminal node potential VG to the same value, so the current flowing through the first transistor Mp2 cancels out the current flowing through the first resistor R1. Therefore, when the power transistor M0 is in the on state, the falling slope of the second terminal potential VD of the power transistor M0, i.e., the output voltage Vout of the power transistor M0, is: Sfalling=I1 / C GD Where I1 represents the current value of the first current source I1, C GDThis represents the equivalent capacitance of the parasitic capacitance. It can be seen that the falling slope Sfalling is a constant value, not changing with the power supply voltage VDD. This solves the problem of ordinary drive circuits in existing technologies. Furthermore, when the first transistor Mp2 and the first current source I1 are in the off state, the power transistor M0 is turned off. At this time, the rising slope of the output voltage Vout output from the second terminal of the power transistor M0 is Srising = Vth / R1 / C. GD Where Vth represents the turn-on threshold voltage of power transistor M0, R1 represents the resistance value of the first resistor R1, and C GD This represents the equivalent capacitance of the parasitic capacitance. It can be seen that the rising slope, Shrising, does not change with the power supply voltage VDD, thus solving the problem of ordinary drive circuits.

[0059] Therefore, the output voltage Vout of the power transistor M0 driving circuit 200 provided in this embodiment changes linearly with a constant rising slope / constant falling slope throughout the entire operation of the driving circuit 200. This protects the power transistor M0 while meeting application requirements and prevents damage caused by excessively rapid changes in its source-drain voltage when switching the power transistor M0 on / off.

[0060] Similarly, in this embodiment, the improved upper transistor drive circuit is as follows: Figure 4 As shown, the first terminal of the power transistor M0 serves as the output terminal, used to provide the output voltage Vout, and... Figure 3 Unlike the lower transistor drive circuit shown, in this circuit, when the power transistor M0 is in the on state, the output voltage Vout increases, and when the power transistor M0 is in the off state, the output voltage Vout decreases. Similarly, it can be seen that the rising slope of the output voltage Vout is Srising = I1 / C. GD Its descending slope is Sfalling=Vth / R1 / C GD .

[0061] In summary, the driving circuit 200 for the power transistor M0 provided in this disclosure can utilize the first switching branch 203 to control the charging current of the control terminal node of the power transistor M0 to a constant value during the power supply voltage VDD, thereby providing the gate drive voltage VG. Furthermore, during the power supply voltage VDD, the second switching branch 202 mirrors the switching node potential VR in the second switching branch 202 to the control terminal node. An operational amplifier 201 compares the switching node potential VR and the gate drive voltage VG to generate an error signal Va. The first switching branch 203, in its on / off states during the power supply voltage VDD power-on period, maintains the output voltage Vout in a linear manner with a constant rising slope (Srising) and a constant falling slope (Sfalling). In the driving circuit 200, the control terminal potential VG of the power transistor M0 is clamped by a mirror circuit structure, so that the output voltage Vout changes linearly with a constant rising slope (Srising) / constant falling slope (Sfalling) throughout the entire operation of the driving circuit 200. This protects the power transistor M0 while meeting application requirements, and prevents damage caused by excessively rapid changes in its source-drain voltage when switching the power transistor M0 on / off.

[0062] Furthermore, the drive circuit 200 can change its driving mode to upper transistor drive by switching the connection state at both ends of the power transistor M0. Figure 4 (as shown) or lower transistor drive ( Figure 3 As shown in the figure, this improves the applicability of the drive circuit 200, while the drive circuit 200 has a simple structure and is easy to operate.

[0063] In the above embodiments, power transistor M0 and transistors Mn1 and Mn2 are, for example, PMOS transistors. In this embodiment, "control terminal," "first terminal," and "second terminal" are, for example, the "gate," "source," and "drain" of a field-effect transistor.

[0064] It should be understood that the transistors in the above embodiments are implemented using field-effect transistors, but this invention is not limited thereto. In other embodiments of this invention, the transistors in the above embodiments can be implemented using bipolar transistors, where the "control terminal," "first terminal," and "second terminal" in the embodiments are respectively the "base," "emitter," and "collector" of the bipolar transistor.

[0065] It should be noted that, in the description of this disclosure, the terms "upper," "lower," "inner," etc., which indicate orientation or positional relationship, are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the components or elements referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0066] Furthermore, throughout this document, the terms "comprising," "including," or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0067] Finally, it should be noted that the above embodiments are merely examples for clearly illustrating this disclosure and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations. However, obvious variations or modifications derived therefrom remain within the scope of this disclosure.

Claims

1. A driving circuit for a power transistor, wherein the power transistor provides an output voltage under the control of a gate driving voltage, characterized in that, The driving circuit includes: The first switching branch, coupled between the input terminal and the first terminal of the power transistor, is used to control the charging current of the control terminal node of the power transistor to a constant value during the power supply voltage supply period, so as to provide the gate drive voltage. The second switching branch, coupled between the input terminal and the first terminal of the power transistor, is used to mirror the switching node potential in the second switching branch to the control terminal node during the power-on of the power supply voltage. An operational amplifier, with its positive input connected to the switching node and its negative input connected to the control node, is used to compare the switching node potential with the gate drive voltage to generate an error signal. Wherein, the first switch branch maintains the output voltage in a linear change with a constant rising slope / constant falling slope during the on and off states of the power supply voltage during power-on.

2. The driving circuit according to claim 1, characterized in that, The first terminal of the power transistor is connected to a common ground voltage, and the second terminal is used to provide the output voltage. When the power transistor is in the ON state, the output voltage changes linearly with a constant decreasing slope; when the power transistor is in the OFF state, the output voltage changes linearly with a constant increasing slope.

3. The driving circuit according to claim 1, characterized in that, The first terminal of the power transistor is used to provide the output voltage, and the second terminal is connected to a preset supply voltage. When the power transistor is in the ON state, the output voltage changes linearly with a constant rising slope; when the power transistor is in the OFF state, the output voltage changes linearly with a constant falling slope.

4. The driving circuit according to claim 2 or 3, characterized in that, The first switch branch includes: A first transistor and a first resistor are connected in series between the input terminal and the first terminal of the power transistor. The connection node of the two transistors is coupled to the control terminal node of the power transistor to provide the gate drive voltage. The control terminal of the first transistor is connected to the error signal. A first current source is connected in parallel across the two ends of the first transistor.

5. The driving circuit according to claim 4, characterized in that, The second switch branch includes: The second transistor and the second resistor are connected in series between the input terminal and the first terminal of the power transistor. The connection node of the two serves as the switching node, and the control terminal of the second transistor is connected to the error signal.

6. The driving circuit according to claim 5, characterized in that, Also includes: A coupling capacitor, the first end of which is connected to the input terminal and connected to the power supply voltage, and the second end of which is connected to the first terminal of the power transistor.

7. The driving circuit according to claim 6, characterized in that, The first transistor and the second transistor have the same width-to-length ratio, and the first resistor and the second resistor have the same specifications.

8. The driving circuit according to claim 7, characterized in that, When the power transistor is in the ON state, both the first transistor and the first current source are in the ON working state. When the power transistor is in the off state, both the first transistor and the first current source are in the off state.

9. The driving circuit according to claim 8, characterized in that, Any one of the power transistor, the first transistor, and the second transistor is a P-channel metal-oxide-semiconductor field-effect transistor.

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