Duplexer Wafer-Level Packaging Method, Packaging Structure and Radio Frequency Module

Abstract

The present invention provides a wafer-level packaging method, a packaging structure and a radio frequency module for a duplexer. The packaging method comprises the following steps: S1, providing a piezoelectric substrate; S2, fabricating a first interdigital component and a second interdigital component on the piezoelectric substrate through a photolithography process; S3, fabricating a first cofferdam and a second cofferdam on the piezoelectric substrate through a photolithography process; S4, forming a cover plate that simultaneously covers the first cofferdam and the second cofferdam through a photolithography process, and forming a first notch, a second notch and a third notch on the cover plate through a photolithography process; S5, electroplating a first filling layer, a second filling layer and a third filling layer at positions of the piezoelectric substrate corresponding to the first notch, the second notch and the third notch respectively through an electroplating process; S6, growing solder balls on the first filling layer and the third filling layer respectively to complete the packaging. The duplexer manufactured by the wafer-level packaging method of the present invention has a simple structure, good spatial isolation performance, reduces electromagnetic crosstalk in space, and is convenient for improving the isolation degree of the duplexer.

Description

Technical Field

[0001] The present invention relates to the field of wireless communication technologies, and in particular to a method for wafer-level packaging of a duplexer. Background Art

[0002] As humanity enters the information age, wireless communication technologies have developed rapidly, and radio frequency modules have become an indispensable part of social life and development. The progress of wireless communication technologies is inseparable from the development of radio frequency circuits and microwave technologies. A radio frequency module is a module chip that includes two or more of devices such as a low-noise amplifier (LNA), a switch, a filter, and an amplifier (PA). Due to its high integration, high performance, etc., the radio frequency module chip is widely used in mobile terminals such as mobile phones and wearable devices. With the increasingly strict requirements for space in terminal devices, radio frequency modules have become even more highly integrated. The increasing demand for miniaturization of radio frequency modules has also put more stringent requirements on the sizes of various devices therein.

[0003] A filter is one of the important devices in a radio frequency module. To meet the requirements of the radio frequency module for size, the wafer-level packaging (WLP) of the filter has made great progress. Its basic principle is that after directly forming a cofferdam on the filter substrate by lithography of an organic material, an organic cover plate is then covered to complete the entire packaging. Since it does not require a substrate for traditional chip-scale packaging (CSP), the size of the WLP has been further reduced. In actual radio frequency applications, a duplexer is a filter that has both receiving and transmitting functions at the same time. Among them, the receiving part is generally called the receiving module (RX) filter, and the transmitting part is generally called the transmitting module (TX) filter. Since the duplexer isolates transmission and reception and prevents cross-interference of the transmission frequency band on the reception in the module, it is an important component in the radio frequency module. The isolation effect between its RX and TX is generally defined by isolation. The higher the isolation, the lower the requirements for other parts of the module, and the more redundancy can be provided for module design. Conversely, if the isolation of the filter is too low, it may be impossible for other components to meet the requirements of the entire module anyway, and the entire module will fail.

[0004] However, according to requirements, existing radio frequency modules generally require an isolation of -65 dB. Due to limitations such as the Q value of resonators that make up the filter, spatial crosstalk, insufficient grounding area, and trace interference, existing duplexers generally can only reach an isolation of -40 dB to -55 dB, and rarely fully meet the requirement of -65 dB. In this case, the requirements for other components such as switches, power amplifiers, and mobile phone antennas in the module will be greatly increased, which limits the cost and application scenarios of related modules. Summary of the Invention

[0005] In view of the deficiencies of the above-mentioned prior art, the present invention proposes a wafer-level packaging method for a duplexer to solve the problems of high manufacturing cost, low isolation, and poor anti-interference performance in the application of traditional wafer-level duplexers.

[0006] To solve the above technical problems, the present invention adopts the following technical solutions:

[0007] In a first aspect, an embodiment of the present invention provides a wafer-level packaging method for a duplexer, characterized in that the packaging method includes the following steps:

[0008] S1. Provide a piezoelectric substrate;

[0009] S2. Through a photolithography process, fabricate a first interdigital component for receiving signals and a second interdigital component for transmitting signals that are spaced apart from each other on the piezoelectric substrate;

[0010] S3. Through a photolithography process, fabricate a first cofferdam and a second cofferdam that are spaced apart from each other on the piezoelectric substrate; the first cofferdam surrounds the first interdigital component and is spaced from the first interdigital component, the second cofferdam surrounds the second interdigital component and is spaced from the second interdigital component, and the first cofferdam and the second cofferdam respectively form a receiving module area for receiving signals and a transmitting module area for transmitting signals that are spaced apart from each other for the first interdigital component and the second interdigital component;

[0011] S4. Through a photolithography process, form a cover plate that simultaneously covers the first cofferdam and the second cofferdam, and form a first notch, a second notch, and a third notch on the cover plate through a photolithography process. The first notch is located in the receiving module area, the second notch is located between the receiving module area and the transmitting module area and completely separates the receiving module area and the transmitting module area, and the third notch is located in the transmitting module area;

[0012] S5. Through an electroplating process, electroplate a first filling layer, a second filling layer, and a third filling layer at positions corresponding to the first notch, the second notch, and the third notch on the piezoelectric substrate respectively, and make the first filling layer, the second filling layer, and the third filling layer respectively fill the first notch, the second notch, and the third notch, and the second filling layer completely separates the receiving module area from the transmitting module area;

[0013] S6. Grow solder balls on the first filling layer and the third filling layer respectively to complete the packaging.

[0014] Preferably, the first interdigital component includes a first interdigital finger and a first bus bar formed on the piezoelectric substrate by photolithography and screen printing; the first interdigital finger is connected to the first bus bar; the second interdigital component includes a second interdigital finger and a second bus bar formed on the piezoelectric substrate by photolithography and screen printing; the second interdigital finger is connected to the second bus bar.

[0015] Preferably, both the first cofferdam and the second cofferdam are formed on the piezoelectric substrate by using an organic material and a photolithography and screen printing process.

[0016] Preferably, the first interdigital fingers include a plurality of them, which are spaced apart on the piezoelectric substrate; the second interdigital fingers include a plurality of them, which are spaced apart on the piezoelectric substrate.

[0017] Preferably, the first filling layer, the second filling layer, and the third filling layer are respectively formed on the piezoelectric substrate by using an organic material and a photolithography and screen printing process.

[0018] Preferably, the first filling layer includes a first seed layer formed on the piezoelectric substrate and a first connecting post formed by electroplating on the surface of the first seed layer; the second filling layer includes a second seed layer formed on the piezoelectric substrate and a second connecting post formed by electroplating on the surface of the second seed layer; the third filling layer includes a third seed layer formed on the piezoelectric substrate and a third connecting post formed by electroplating on the surface of the third seed layer.

[0019] Preferably, in step S6, the solder balls are respectively formed on the first filling layer and the third filling layer by brushing through a solder ball mask.

[0020] Preferably, the piezoelectric substrate is made of any one of lithium niobate, lithium tantalate, piezoelectric ceramics, and piezoelectric quartz.

[0021] In a second aspect, the present invention further provides a duplexer wafer-level packaging structure, and the duplexer wafer-level packaging structure is made by the above-mentioned duplexer wafer-level packaging method.

[0022] In a third aspect, the present invention provides a radio frequency module, including the above-mentioned duplexer wafer-level packaging structure.

[0023] Compared with the related art, in the embodiments of the present invention, through the above steps S1-S6, by growing a cover plate on the first cofferdam and the second cofferdam, and forming a first notch, a second notch, and a third notch on the cover plate through a photolithography process, and electroplating a first filling layer, a second filling layer, and a third filling layer in the first notch, the second notch, and the third notch respectively through an electroplating process, the second filling layer completely separates the receiving module area from the transmitting module area; in this way, through the process of solder ball columns, the second filling layer is inserted to form a metal partition to improve the spatial isolation performance of the receiving module area (RX part) and the transmitting module area (TX part) in the duplexer, thereby reducing the electromagnetic crosstalk in the space and improving the isolation degree of the duplexer. Description of the Drawings

[0024] The present invention will be described in detail below with reference to the drawings. Through the detailed description in conjunction with the following drawings, the above or other aspects of the present invention will become clearer and easier to understand. In the drawings:

[0025] Figure 1 is a flowchart of the wafer-level packaging method of the duplexer in the embodiments of the present invention;

[0026] Figure 2 is a packaging schematic diagram of the wafer-level packaging method of the duplexer in the embodiments of the present invention;

[0027] Figure 3 is a structural schematic diagram of the wafer-level packaging structure of the duplexer in the embodiments of the present invention;

[0028] Figure 4 is Figure 3 a cross-sectional view taken along line A-A of

[0029] Among them, 100 is the wafer-level packaging structure of the duplexer, 1 is the piezoelectric substrate, 2 is the first finger assembly, 21 is the first finger, 3 is the second finger assembly, 31 is the second finger, 4 is the first cofferdam, 5 is the receiving module area, 6 is the transmitting module area, 7 is the cover plate, 71 is the first cover plate, 72 is the second cover plate, 8 is the solder ball, 81 is the first solder ball, 82 is the second solder ball, 9 is the first notch, 10 is the second notch, 11 is the third notch, 12 is the first filling layer, 121 is the first seed layer, 122 is the first connecting column, 13 is the second filling layer, 131 is the second seed layer, 132 is the second connecting column, 14 is the third filling layer, 141 is the third seed layer, 142 is the third connecting column, 15 is the second cofferdam. Detailed Embodiments

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs; the terms used in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" and any variations thereof in the specification and claims of this application and the above drawings are intended to cover non-exclusive inclusion. The terms "first", "second", etc. in the specification and claims of this application or the above drawings are used to distinguish different objects and not to describe a specific order.

[0031] Reference herein to "embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiments can be included in at least one embodiment of this application. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0032] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.

[0033] Embodiment 1

[0034] Please refer to Figures 1-4 As shown, the embodiment of the present invention provides a method for wafer-level packaging of a duplexer, characterized in that the packaging method includes the following steps:

[0035] S1. Provide a piezoelectric substrate 1. The provided piezoelectric substrate 1 is used to form a main body support structure, which is convenient for growing interdigital components, dams 4, etc.

[0036] S2. Fabricate, by means of a lithography process, on the piezoelectric substrate 1, first interdigital components 2 for receiving signals and second interdigital components 3 for transmitting signals that are spaced apart from each other.

[0037] S3. Fabricate, by means of a lithography process, on the piezoelectric substrate 1, first dams 4 and second dams 15 that are spaced apart from each other; the first dams 4 surround the first interdigital components 2 and are spaced from the first interdigital components 2, the second dams 15 surround the second interdigital components 3 and are spaced from the second interdigital components 3, and the first dams 4 and the second dams 15 respectively form a receiving module area 5 for receiving signals and a transmitting module area 6 for transmitting signals that are spaced apart from each other for the first interdigital components 2 and the second interdigital components 3.

[0038] S4. Form a cover plate 7 that simultaneously covers the first cofferdam 4 and the second cofferdam 15 through a photolithography process, and form a first notch 9, a second notch 10, and a third notch 11 on the cover plate 7 through a photolithography process. The first notch 9 is located in the receiving module area 5, the second notch 10 is located between the receiving module area 5 and the transmitting module area 6 and completely separates the receiving module area 5 and the transmitting module area 6, and the third notch 11 is located in the transmitting module area 6.

[0039] S5. Electroplate a first filling layer 12, a second filling layer 13, and a third filling layer 14 at positions corresponding to the first notch 9, the second notch 10, and the third notch 11 on the piezoelectric substrate through an electroplating process, and make the first filling layer, the second filling layer, and the third filling layer fill the first notch, the second notch, and the third notch respectively. The second filling layer 13 completely separates the receiving module area 5 and the transmitting module area 6. Make the first filling layer 12, the second filling layer 13, and the third filling layer 14 be connected to the piezoelectric substrate 1 respectively.

[0040] Among them, there are multiple first notches 9 and third notches 11, and they are cylindrical structures. The second notch 10 is a rectangular structure, formed between the first cofferdam 4 and the second cofferdam 15, and is used to separate the receiving module area 5 and the transmitting module area 6.

[0041] S6. Grow solder balls 8 on the first filling layer 12 and the third filling layer 14 respectively to complete the encapsulation. Among them, form a first cover plate 71 covering the first cofferdam 4 and a second cover plate 72 covering the second cofferdam 15 through a photolithography process respectively, and reserve a first notch 9 for growing a first solder ball 81 on the first cover plate 71 and reserve a third notch 11 for growing a second solder ball 82 on the second cover plate 72. The first filling layer 12 and the third filling layer 14 have good electrical conductivity, which is convenient for growing solder balls 8. In the final actual use, the second filling layer 13 can be grounded or not grounded to improve the electromagnetic isolation degree of the RX and TX parts, thereby improving the filter isolation degree of the RX / TX duplexer. Optionally, the second filling layer 13 is grounded or not grounded.

[0042] Specifically, through the above steps S1 - S6, by growing a cover plate 7 on the first cofferdam 4 and the second cofferdam 15, and forming a first notch 9, a second notch 10, and a third notch 11 on the cover plate 7 through a photolithography process, and electroplating a first filling layer 12, a second filling layer 13, and a third filling layer 14 in the first notch 9, the second notch 10, and the third notch 11 respectively through an electroplating process, the second filling layer 13 completely separates the receiving module area 5 from the transmitting module area 6; in this way, through the process of the solder ball 8 column, the second filling layer 13 is inserted to form a metal partition, so as to improve the spatial isolation performance of the receiving module area 5 (RX part) and the transmitting module area 6 (TX part) in the duplexer, thereby reducing the electromagnetic crosstalk in the space and improving the isolation degree of the duplexer.

[0043] In this embodiment, the first finger assembly 2 includes a first finger 21 and a first bus bar formed on the piezoelectric substrate 1 through photolithographic screen printing; the first finger 21 is connected to the first bus bar; the second finger assembly 3 includes a second finger 31 and a second bus bar formed on the piezoelectric substrate 1 through photolithographic screen printing; the second finger 31 is connected to the second bus bar. The first finger 21 is connected to the first bus bar and the piezoelectric substrate 1 to achieve conduction. The second finger 31 is connected to the second bus bar and the piezoelectric substrate 1 to achieve conduction.

[0044] In this embodiment, both the first cofferdam 4 and the second cofferdam 15 are formed on the piezoelectric substrate 1 using an organic material through a photolithographic screen printing process. It is convenient to manufacture and the performance of the filter is excellent.

[0045] In this embodiment, the first finger 21 includes a plurality of them, and they are spaced apart on the piezoelectric substrate 1; the second finger 31 includes a plurality of them, and they are spaced apart on the piezoelectric substrate 1.

[0046] In this embodiment, the first filling layer 12, the second filling layer 13, and the third filling layer 14 are respectively formed on the piezoelectric substrate 1 using an organic material through a photolithographic screen printing process.

[0047] In this embodiment, the first filling layer 12 includes a first seed layer 121 formed on the piezoelectric substrate 1 and a first connecting column 122 formed by electroplating on the first seed layer 121; the second filling layer 13 includes a second seed layer 131 formed on the piezoelectric substrate 1 and a second connecting column 132 formed by electroplating on the surface of the second seed layer 131; the third filling layer 14 includes a third seed layer 141 formed on the piezoelectric substrate 1 and a third connecting column 142 formed by electroplating on the surface of the third seed layer 141. The first seed layer 121, the second seed layer 131, and the third seed layer 141 are respectively used to connect the piezoelectric substrate 1. The first connecting column 122, the second connecting column 132, and the third connecting column 142 are respectively grown on the first seed layer 121, the second seed layer 131, and the third seed layer 141. The first connecting column 122, the second connecting column 132, and the third connecting column 142 have good electrical conductivity, which is convenient for growing the solder balls 8.

[0048] In this embodiment, in step S6, the solder balls 8 are respectively formed on the first filling layer 12 and the third filling layer 14 by brushing through a solder ball mask.

[0049] In this embodiment, the piezoelectric substrate 1 is made of any one of lithium niobate, lithium tantalate, piezoelectric ceramics, and piezoelectric quartz. This makes the piezoelectric substrate 1 have high strength and good piezoelectric performance.

[0050] Embodiment Two

[0051] As Figures 3-4 shown, the present invention also provides a duplexer wafer-level packaging structure 100, and the duplexer wafer-level packaging structure 100 is made by the duplexer wafer-level packaging method described in the above Embodiment One.

[0052] Embodiment Three

[0053] The present invention provides a radio frequency module, including the duplexer wafer-level packaging structure 100 of the above Embodiment Two.

[0054] It should be noted that each of the above-described embodiments described with reference to the accompanying drawings is only used to illustrate the present invention rather than to limit the scope of the present invention. Those of ordinary skill in the art should understand that any modification or equivalent replacement made to the present invention without departing from the spirit and scope of the present invention shall be covered within the scope of the present invention. In addition, unless otherwise specified in the context, words in the singular form include the plural form, and vice versa. Additionally, unless otherwise specified, all or part of any embodiment can be used in combination with all or part of any other embodiment.

Claims

1. A wafer-level packaging method for a duplexer, characterized in that, The encapsulation method includes the following steps: S1. Provide a piezoelectric substrate; S2. Fabricate, by means of a lithography process, a first interdigital component for receiving signals and a second interdigital component for transmitting signals that are spaced apart from each other on the piezoelectric substrate; S3. Fabricate, by means of a lithography process, a first cofferdam and a second cofferdam that are spaced apart from each other on the piezoelectric substrate; the first cofferdam surrounds the first interdigital component and is spaced from the first interdigital component, the second cofferdam surrounds the second interdigital component and is spaced from the second interdigital component, and the first cofferdam and the second cofferdam respectively form a receiving module area for receiving signals and a transmitting module area for transmitting signals that are spaced apart from each other for the first interdigital component and the second interdigital component; S4. Form, by means of a lithography process, a cover plate that covers both the first cofferdam and the second cofferdam, and form, by means of a lithography process, a first notch, a second notch, and a third notch on the cover plate, where the first notch is located in the receiving module area, the second notch is located between the receiving module area and the transmitting module area and completely separates the receiving module area and the transmitting module area, and the third notch is located in the transmitting module area; S5. Electroplate a first filling layer, a second filling layer, and a third filling layer at positions on the piezoelectric substrate corresponding to the first notch, the second notch, and the third notch respectively by means of an electroplating process, and make the first filling layer, the second filling layer, and the third filling layer respectively fill the first notch, the second notch, and the third notch, and the second filling layer completely separates the receiving module area from the transmitting module area; S6. Grow solder balls on the first filling layer and the third filling layer respectively to complete the encapsulation.

2. The packaging method of the duplexer at the wafer level according to claim 1, wherein, The first interdigital component includes a first finger and a first bus bar formed on the piezoelectric substrate by means of lithography and screen printing; the first finger is connected to the first bus bar; the second interdigital component includes a second finger and a second bus bar formed on the piezoelectric substrate by means of lithography and screen printing; the second finger is connected to the second bus bar.

3. The packaging method of the duplexer at the wafer level according to claim 1, wherein, Both the first cofferdam and the second cofferdam are formed on the piezoelectric substrate by means of a lithography and screen printing process using an organic material.

4. The packaging method of the duplexer at the wafer level according to claim 2, characterized in that, The first finger includes a plurality of them, and they are spaced apart and arranged on the piezoelectric substrate; the second finger includes a plurality of them, and they are spaced apart and arranged on the piezoelectric substrate.

5. The packaging method for a duplexer at the wafer level according to claim 1, wherein The first filling layer, the second filling layer, and the third filling layer are respectively formed on the piezoelectric substrate by means of a lithography and screen printing process using an organic material.

6. The packaging method of the duplexer in wafer level according to claim 1 or 5, characterized in that, The first filling layer includes a first seed layer formed on the piezoelectric substrate and a first connecting post electroplated on the surface of the first seed layer; the second filling layer includes a second seed layer formed on the piezoelectric substrate and a second connecting post electroplated on the surface of the second seed layer; the third filling layer includes a third seed layer formed on the piezoelectric substrate and a third connecting post electroplated on the surface of the third seed layer.

7. The wafer-level packaging method of the duplexer according to claim 1, characterized in that, In step S6, the solder balls are respectively formed by brushing on the first filling layer and the third filling layer in a solder ball mask manner.

8. The packaging method of the duplexer at the wafer level according to claim 1, characterized in that The piezoelectric substrate is made of any one of lithium niobate, lithium tantalate, piezoelectric ceramics, and piezoelectric quartz.

9. A duplexer wafer-level packaging structure, characterized in that The duplexer wafer-level packaging structure is made by the duplexer wafer-level packaging method according to any one of claims 1-8.

10. A radio frequency module, characterized in that, It includes the duplexer wafer-level packaging structure according to claim 9.

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