A method and system for standardizing and reconfiguring satellite-borne routers

Abstract

This specification discloses a standardized refresh and reconfiguration method and system for spaceborne routers, relating to the field of satellite payload technology. The method includes: when an antifuse FPGA receives a first external control frame sent by a satellite platform via a data interface, it disconnects the dedicated FPGA refresh circuit from the bus corresponding to the switching software bitstream memory and erases the switching software bitstream memory; the antifuse FPGA receives a second external control frame, writes the software bitstream carried by the second external control frame into the corresponding location of the switching software bitstream memory, and reconnects the dedicated FPGA refresh circuit to the bus corresponding to the switching software bitstream memory; the antifuse FPGA receives a third external control frame and converts the format of the third external control frame into a command in the proprietary frame format of the dedicated FPGA refresh circuit; after receiving the third external control frame, the dedicated FPGA refresh circuit starts refreshing the reconfigured SRAM FPGA based on the software bitstream in the switching software bitstream memory. This method addresses the problems of complex refresh logic and slow reconfiguration speed in spaceborne routers.

Description

Technical Field

[0001] This document relates to the field of satellite payload technology, and in particular to a method and system for standardized refresh and reconstruction of satellite-borne routers. Background Art

[0002] The onboard router is one of the core devices of the low-orbit network constellation satellite, providing routing path selection and data exchange and forwarding functions for multi-source data arriving at the satellite. Unlike ground-based commercial routers, onboard routers work in space and are susceptible to single-particle upsets, which lead to frequent interruptions of mission functions. In addition, they need to frequently perform on-orbit upgrades to update the routing protocol of the satellite network. Therefore, onboard routers require special designs to meet long-term on-orbit work. In terms of functional division, onboard routers contain two functional entities: a 3-layer routing protocol and a 2.5-layer switching and forwarding. The routing protocol is implemented by the CPU, and a routing table for the entire network is maintained through control plane signaling interaction, and mapped into a 2.5-layer forwarding table. Switching and forwarding are implemented using static random access memory (SRAM) programmable array logic (FPGA). Multi-source access data and inter-satellite forwarding data are searched in the forwarding table to achieve high-speed switching and forwarding of network data. When the onboard router is working in orbit, the execution logic of the routing protocol software is monitored in real time, and the configuration bit stream of the switching and forwarding software is refreshed periodically to ensure reliable operation of the onboard router in orbit. When the onboard router is upgraded in orbit, the routing protocol software and switching and forwarding software are reconstructed to achieve on-orbit function update.

[0003] Traditionally, there are two ways to achieve the refresh and reconstruction of onboard processing loads. One is to use a single large-scale anti-fuse FPGA, such as the AX1000 chip with 1 million gate resources, to implement the refresh logic and reconstruction logic of the SRAM FPGA through the anti-fuse FPGA, which is used for the refresh and reconstruction of the onboard router; the other is to use a single small-scale anti-fuse FPGA, such as the AX500 chip with 500,000 gate resources, and a dedicated FPGA refresh chip to implement the refresh logic and reconstruction logic of the SRAM FPGA. The small-scale anti-fuse FPGA implements external interface adaptation and internal logic control, and the dedicated FPGA refresh chip implements the action execution of the SRAM FPGA refresh and reconstruction, which is used for the refresh and reconstruction of the onboard router. The advantage of the former solution is that it is flexible to use and has a fast software reconstruction time. However, with the continuous improvement of the switching capacity of satellite routers, the selection of SRAMFPGAs has developed from the K series and V series to larger chips such as the KU series. The organizational forms of the configuration areas of different types of SRAM FPGAs are different, and the refresh logic in the anti-fuse FPGA is very difficult to implement; the latter solution uses a dedicated FPGA refresh circuit that matches the SRAMFPGA to implement the refresh and reconstruction functions, which can greatly reduce the workload of implementing the refresh logic, but it is not flexible to use and must be operated according to the dedicated format of the chip manufacturer. In addition, an anti-fuse FPGA is required to implement external interface adaptation and internal logic control. At the same time, it is limited by the communication interface rate of the dedicated FPGA refresh circuit, and the software reconstruction speed is very slow. Summary of the invention

[0004] This specification provides a method and system for standardizing the refresh and reconstruction of satellite-borne routers, which are used to solve the problems of complex refresh logic and slow reconstruction speed of satellite-borne routers.

[0005] To solve this technical problem, this specification provides the following technical solutions:

[0006] On the one hand, this specification provides a standardized refresh and reconstruction method for a satellite-borne router, including:

[0007] S1. When the anti-fuse FPGA receives the first external control frame sent by the satellite platform through the data interface, it disconnects the connection between the dedicated FPGA refresh circuit and the bus corresponding to the exchange software bit stream memory, and completes the erasure of the exchange software bit stream memory. The first external control frame is used to indicate the start of reconstruction of the SRAM FPGA.

[0008] S2, the anti-fuse FPGA receives a second external control frame sent by the satellite platform through the data interface, writes the software bit stream carried by the second external control frame into the corresponding position of the exchange software bit stream memory, and rebuilds the connection between the dedicated FPGA refresh circuit and the corresponding bus of the exchange software bit stream memory, wherein the second external control frame is sent by the satellite platform after determining that the anti-fuse FPGA is in the SRAM FPGA reconstruction state;

[0009] S3, the anti-fuse FPGA receives the third external control frame sent by the satellite platform through the data interface, and converts the format of the third external control frame into a command of a proprietary frame format of the dedicated FPGA refresh circuit, wherein the third external control frame is used to instruct the dedicated FPGA refresh circuit to start refreshing the reconstructed SRAM FPGA;

[0010] S4. After receiving the third external control frame, the dedicated FPGA refresh circuit starts refreshing the reconstructed SRAM FPGA based on the software bit stream in the exchange software bit stream memory.

[0011] On the other hand, this specification also provides a satellite router reconstruction method, characterized by comprising:

[0012] The anti-fuse FPGA receives the seventh external control frame sent by the satellite platform through the data interface, disconnects the connection between the CPU and the bus corresponding to the routing software bit stream memory, and completes the erasure of the routing software bit stream memory, wherein the seventh external control frame is used to instruct to start the reconstruction of the CPU;

[0013] The antifuse FPGA receives the seventh external control frame sent by the satellite platform through the data interface, writes the software bit stream carried by the seventh external control frame into the corresponding position of the routing software bit stream memory, and rebuilds the connection between the CPU and the corresponding bus of the routing software bit stream memory. The seventh external control frame is sent by the satellite platform after determining that the antifuse FPGA is in the CPU reconstruction state.

[0014] On the other hand, the present specification also provides a standardized refresh and reconstruction system for a satellite-borne router, characterized in that it includes an SRAM FPGA start-up reconstruction module, an SRAM FPGA bit stream reconstruction module, a format conversion module and a start-up refresh module, wherein:

[0015] The SRAM FPGA reconstruction start module is used to disconnect the connection between the dedicated FPGA refresh circuit and the bus corresponding to the exchange software bit stream memory and complete the erasure of the exchange software bit stream memory when the anti-fuse FPGA receives the first external control frame sent by the satellite platform through the data interface, and the first external control frame is used to indicate the start of reconstruction of the SRAM FPGA;

[0016] The SRAM FPGA bitstream reconstruction module is used for the anti-fuse FPGA to receive a second external control frame sent by the satellite platform through the data interface, and write the software bitstream carried by the second external control frame into the corresponding position of the exchange software bitstream memory, and rebuild the connection between the dedicated FPGA refresh circuit and the corresponding bus of the exchange software bitstream memory, wherein the second external control frame is sent by the satellite platform after determining that the anti-fuse FPGA is in the SRAM FPGA reconstruction state;

[0017] A format conversion module, used for the anti-fuse FPGA to receive a third external control frame sent by the satellite platform through a data interface, and convert the format of the third external control frame into a command of a proprietary frame format of a dedicated FPGA refresh circuit, wherein the third external control frame is used to instruct the dedicated FPGA refresh circuit to start refreshing the reconstructed SRAM FPGA;

[0018] The refresh start module is used for the dedicated FPGA refresh circuit to start refreshing the reconstructed SRAM FPGA based on the software bit stream in the exchange software bit stream memory after receiving the third external control frame.

[0019] On the other hand, the present specification also provides a satellite router reconstruction system, characterized in that it includes a CPU reconstruction startup module and a CPU bit stream reconstruction module, wherein:

[0020] A CPU reconstruction start module is used for the anti-fuse FPGA to receive the seventh external control frame sent by the satellite platform through the data interface, disconnect the CPU from the bus corresponding to the routing software bit stream memory, and complete the erasure of the routing software bit stream memory, wherein the seventh external control frame is used to indicate the start of reconstruction of the CPU;

[0021] The CPU bitstream reconstruction module is used for the anti-fuse FPGA to receive the seventh external control frame sent by the satellite platform through the data interface, write the software bitstream carried by the seventh external control frame into the corresponding position of the routing software bitstream memory, and rebuild the connection between the CPU and the corresponding bus of the routing software bitstream memory. The seventh external control frame is sent by the satellite platform after determining that the anti-fuse FPGA is in the CPU reconstruction state.

[0022] At least one of the above technical solutions adopted in this specification can achieve the following beneficial effects:

[0023] Based on a small-scale anti-fuse FPGA and a dedicated FPGA refresh circuit, through clever function allocation and software design optimization, standardized refresh of SRAM FPGA is achieved, which reduces the workload of refresh logic and greatly shortens the time of software reconstruction, thus realizing the flexible on-orbit application of spaceborne routers. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The drawings described herein are used to provide a further understanding of this specification and constitute a part of this specification. The illustrative embodiments and descriptions of this specification are used to explain this specification and do not constitute an improper limitation on this specification. In the drawings:

[0025] Figure 1 A flowchart of a standardized refresh and reconstruction method for a satellite-based router provided in an embodiment of this specification;

[0026] Figure 2 A schematic flow chart of a standardized refresh method for a satellite-borne router provided in another embodiment of the present specification;

[0027] Figure 3 A schematic flow chart of a satellite router reconstruction method provided in another embodiment of the present specification;

[0028] Figure 4 A schematic diagram of a standardized refresh and reconstruction system for onboard routers provided in another embodiment of the present specification;

[0029] Figure 5 A schematic diagram of a satellite router reconstruction system provided in accordance with another embodiment of the present specification. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solutions and advantages of this specification more clear, the technical solutions of this specification will be clearly and completely described below in combination with the specific embodiments of this specification and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of this specification, not all of them. Based on the embodiments in this specification, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this specification.

[0031] The technical solutions provided by the embodiments of this specification are described in detail below in conjunction with the accompanying drawings.

[0032] Figure 1 A schematic diagram of a standardized refresh and reconstruction method for a satellite router provided in an embodiment of this specification, see Figure 1 , the method may specifically include the following steps:

[0033] Step 102: When the anti-fuse FPGA receives the first external control frame sent by the satellite platform through the data interface, it disconnects the dedicated FPGA refresh circuit from the bus corresponding to the exchange software bit stream memory, and completes erasing the exchange software bit stream memory. The first external control frame is used to indicate the start of reconstruction of the SRAM FPGA.

[0034] It should be noted that one implementation of step 102 may be:

[0035] The anti-fuse FPGA is connected to the external data interface, where the external data interface is used to complete the reception of external control frames and the return of telemetry frames of the onboard router itself. After the external data interface receives the command sent by the satellite platform to start the reconstruction of the SRAM FPGA, it sends it to the anti-fuse FPGA. When the anti-fuse FPGA receives the command, it disconnects the connection between the dedicated FPGA refresh circuit and the corresponding bus of the exchange software bit stream memory, and the anti-fuse FPGA obtains the control right of the exchange software bit stream memory and erases the software bit stream in the exchange software bit stream memory.

[0036] After the anti-fuse FPGA completes erasure, it sends the telemetry back to the satellite platform through the external data interface. The satellite platform determines whether the anti-fuse FPGA is in the SRAM FPGA reconstruction state based on the telemetry. If the anti-fuse FPGA is in the SRAM FPGA reconstruction state, continue with step 104; if the anti-fuse FPGA has not entered the SRAM FPGA reconstruction state, the satellite platform continues to send a command for starting the reconstruction of the SRAM FPGA to the anti-fuse FPGA through the external data interface. When the anti-fuse FPGA receives the command, it disconnects the dedicated FPGA refresh circuit from the corresponding bus of the exchange software bitstream memory, and the anti-fuse FPGA obtains control of the exchange software bitstream memory and erases the software bitstream in the exchange software bitstream memory.

[0037] Furthermore, this embodiment provides a preprocessing method before SRAM FPGA reconstruction, including:

[0038] The anti-fuse FPGA receives the zeroth external control frame sent by the satellite platform through the data interface, and converts the format of the zeroth external control frame into a command of a proprietary frame format of a dedicated FPGA refresh circuit, wherein the zeroth external control frame is used to instruct the dedicated FPGA refresh circuit to turn off refreshing;

[0039] After receiving the zeroth external control frame, the dedicated FPGA refresh circuit turns off refreshing of the SRAM FPGA.

[0040] Specifically, the satellite platform sends an external control frame for instructing the dedicated FPGA refresh circuit to turn off refresh to the anti-fuse FPGA through the external data interface. After receiving the command, the anti-fuse FPGA converts the format of the external control frame into the frame format of the dedicated FPGA refresh circuit and sends it to the dedicated FPGA refresh circuit. The dedicated FPGA refresh circuit stops refreshing the SRAM FPGA according to the command to turn off refresh. At the same time, the status of whether the dedicated FPGA refresh circuit has successfully turned off refresh is sent to the anti-fuse FPGA and the satellite platform in sequence through the external data interface.

[0041] If the dedicated FPGA refresh circuit successfully turns off the refresh, step 102 is executed; if the dedicated FPGA refresh circuit fails to turn off the refresh, the satellite platform continues to send an external control frame for instructing the dedicated FPGA refresh circuit to turn off the refresh to the anti-fuse FPGA through the external data interface. After receiving the command, the anti-fuse FPGA converts the format of the external control frame into the frame format of the dedicated FPGA refresh circuit and sends it to the dedicated FPGA refresh circuit. The dedicated FPGA refresh circuit stops refreshing the SRAM FPGA according to the command to turn off the refresh.

[0042] Based on this, by confirming that the dedicated FPGA refresh circuit is in the refresh-off state before the SRAM FPGA is reconfigured, conditions are provided for the SRAM FPGA reconstruction and refresh and reconstruction execution errors are avoided.

[0043] Step 104, the anti-fuse FPGA receives a second external control frame sent by the satellite platform through the data interface, writes the software bit stream carried by the second external control frame into the corresponding position of the exchange software bit stream memory, and rebuilds the connection between the dedicated FPGA refresh circuit and the corresponding bus of the exchange software bit stream memory. The second external control frame is sent by the satellite platform after determining that the anti-fuse FPGA is in the SRAM FPGA reconstruction state.

[0044] It should be noted that one implementation of step 104 may be:

[0045] After the satellite platform determines that the anti-fuse FPGA is in the SRAM FPGA reconstruction state, it sends external control frames for instructing the anti-fuse FPGA to reconstruct the bit stream to the anti-fuse FPGA through the external data interface. After receiving the external control frame, the anti-fuse FPGA writes the software bit stream carried by the external control frame into the corresponding position of the exchange software bit stream memory in sequence until the complete exchange software bit stream is written into the exchange software bit stream memory. Then the anti-fuse FPGA releases the control right of the exchange software bit stream memory and re-establishes the connection between the dedicated FPGA refresh circuit and the corresponding bus of the exchange software bit stream memory.

[0046] Furthermore, in order to ensure the accuracy of software reconstruction, the embodiment of this specification provides a readback verification method, including:

[0047] The anti-fuse FPGA calculates a check code according to the software bit stream in the exchange software bit stream memory, and the check code is used by the satellite platform to determine whether the reconstruction is correct;

[0048] If the reconstruction is incorrect, the anti-fuse FPGA receives the fourth external control frame sent by the satellite platform through the data interface and executes S1-S4, wherein the fourth external control frame is used to instruct to restart the reconstruction.

[0049] Specifically, the satellite platform sends an external control frame for instructing readback verification to the anti-fuse FPGA through an external data interface. After receiving the external control frame, the anti-fuse FPGA reads the software bit stream written in the exchange software bit stream memory and calculates the verification code.

[0050] The anti-fuse FPGA sends a check code back to the satellite platform through the external data interface, and the satellite platform determines whether the software reconstruction is correct based on the received check code.

[0051] If the software reconstruction is correct, then continue to execute step 106. If the software reconstruction is incorrect, then return to execute step 102.

[0052] Based on this, the accuracy of software reconstruction is ensured by reading back and checking the software bit stream.

[0053] Further, on the basis of completing the SRAM FPGA reconstruction, in order to reload the exchange software bit stream, the embodiment of this specification provides a software reset method, including:

[0054] The anti-fuse FPGA receives the fifth external control frame sent by the satellite platform through the data interface, and controls the watchdog circuit to output a global reset signal, wherein the fifth external control frame is used to indicate a global reset of the circuit;

[0055] The dedicated FPGA refresh circuit reloads the software bit stream in the exchange software bit stream memory according to the global reset signal.

[0056] Specifically, the satellite platform sends an external control frame for indicating a global reset of the circuit to the anti-fuse FPGA through an external data interface, and after the watchdog logic and hardware reset "AND" operation, controls the watchdog circuit to output a global reset signal. When the dedicated FPGA refresh circuit receives the global reset signal, it reloads the exchange software bit stream memory.

[0057] Based on this, the switching software bit stream is reloaded by resetting the global circuit software.

[0058] Step 106: The anti-fuse FPGA receives the third external control frame sent by the satellite platform through the data interface, and converts the format of the third external control frame into a command of a proprietary frame format of a dedicated FPGA refresh circuit, wherein the third external control frame is used to instruct the dedicated FPGA refresh circuit to start refreshing the reconstructed SRAM FPGA.

[0059] It should be noted that one implementation of step 106 may be:

[0060] The satellite platform sends an external control frame to the anti-fuse FPGA through the external data interface, which is used for the dedicated FPGA refresh circuit to start refreshing the reconstructed SRAM FPGA. After receiving the external control frame, the anti-fuse FPGA converts its format into a command in the proprietary frame format of the dedicated FPGA refresh circuit and sends it to the dedicated FPGA refresh circuit.

[0061] Step 108: After receiving the third external control frame, the dedicated FPGA refresh circuit starts refreshing the reconstructed SRAM FPGA based on the software bit stream in the exchange software bit stream memory.

[0062] It should be noted that one implementation of step 108 may be:

[0063] After receiving the external control frame for starting the refresh of the reconstructed SRAM FPGA, the dedicated FPGA refresh circuit starts the refresh operation of the SRAM FPGA. At the same time, the dedicated FPGA refresh circuit sends its refresh start status to the anti-fuse FPGA and the satellite platform in sequence.

[0064] If the dedicated FPGA refresh circuit is in the refresh-on state, it indicates that the SRAM FPGA reconstruction of the onboard router is complete.

[0065] If the dedicated FPGA refresh circuit is not in the refresh start state, the satellite platform sends an external control frame for the dedicated FPGA refresh circuit to start refreshing the reconstructed SRAM FPGA to the anti-fuse FPGA through the external data interface. After receiving the external control frame, the anti-fuse FPGA converts its format into a command of the dedicated FPGA refresh circuit's proprietary frame format and sends it to the dedicated FPGA refresh circuit. After receiving the external control frame for the dedicated FPGA refresh circuit to start refreshing the reconstructed SRAM FPGA, the dedicated FPGA refresh circuit starts the refresh operation on the SRAM FPGA.

[0066] In summary, based on a small-scale antifuse FPGA and a dedicated FPGA refresh circuit, through clever function allocation and software design optimization, the standardization and reconstruction joint processing of SRAM FPGA is realized, which reduces the workload of the refresh logic and greatly shortens the software reconstruction time, thus realizing the flexible on-orbit application of the spaceborne router.

[0067] Figure 2 A schematic diagram of a standardized refresh method for a satellite router provided in an embodiment of this specification, see Figure 2 The method may specifically include the following steps:

[0068] Step 202: The anti-fuse FPGA receives the sixth external control frame sent by the satellite platform through the data interface, and converts the format of the sixth external control frame into a command in a proprietary frame format of a dedicated FPGA refresh circuit, wherein the sixth external control frame is used to instruct the dedicated FPGA refresh circuit to perform a standardized refresh on the SRAM FPGA.

[0069] It should be noted that one implementation of step 202 may be:

[0070] The satellite platform sends an external control frame to the anti-fuse FPGA through the external data interface for the dedicated FPGA refresh circuit to perform standardized refresh of the SRAM FPGA. After receiving the external control frame, the anti-fuse FPGA converts its format into a command in the proprietary frame format of the dedicated FPGA refresh circuit and sends it to the dedicated FPGA refresh circuit.

[0071] Step 204: After receiving the sixth external control frame, the dedicated FPGA refresh circuit performs a standardized refresh on the SRAM FPGA.

[0072] It should be noted that one implementation of step 204 may be:

[0073] After receiving the external control frame for the dedicated FPGA refresh circuit to perform standardized refresh on the SRAM FPGA, the dedicated FPGA refresh circuit starts the standardized refresh operation on the SRAM FPGA. At the same time, the dedicated FPGA refresh circuit sends its refresh start status to the anti-fuse FPGA and the satellite platform in sequence.

[0074] If the dedicated FPGA refresh circuit is in the refresh-on state, it indicates that the SRAM FPGA reconstruction of the onboard router is complete.

[0075] If the dedicated FPGA refresh circuit is not in the refresh start state, the satellite platform sends an external control frame for the dedicated FPGA refresh circuit to perform standardized refresh of the SRAM FPGA to the anti-fuse FPGA through the external data interface. After receiving the external control frame, the anti-fuse FPGA converts its format into a command of the proprietary frame format of the dedicated FPGA refresh circuit and sends it to the dedicated FPGA refresh circuit. After receiving the external control frame for the dedicated FPGA refresh circuit to perform standardized refresh of the SRAM FPGA, the dedicated FPGA refresh circuit starts the standardized refresh operation of the SRAM FPGA.

[0076] In summary, through the function allocation and software optimization of the anti-fuse FPGA, the standardized refresh of the SRAM FPGA is realized, the refresh logic is simplified, and the workload of the refresh operation is reduced.

[0077] Figure 3 This is a flowchart of a satellite router reconstruction method provided in an embodiment of this specification, see Figure 3 The method may specifically include the following steps:

[0078] Step 302, the anti-fuse FPGA receives the seventh external control frame sent by the satellite platform through the data interface, disconnects the connection between the CPU and the corresponding bus of the routing software bitstream memory, and completes the erasure of the routing software bitstream memory. The seventh external control frame is used to instruct the CPU to start reconstruction.

[0079] It should be noted that one implementation of step 302 may be:

[0080] After receiving the command sent by the satellite platform to start the CPU reconstruction, the external data interface sends it to the anti-fuse FPGA. When the anti-fuse FPGA receives the command, it disconnects the CPU from the bus corresponding to the routing software bitstream memory, and the anti-fuse FPGA obtains the control right of the routing software bitstream memory and erases the software bitstream in the routing software bitstream memory.

[0081] After the anti-fuse FPGA completes erasure, it sends the telemetry back to the satellite platform through the external data interface. The satellite platform determines whether the anti-fuse FPGA is in the CPU reconstruction state based on the telemetry. If the anti-fuse FPGA is in the CPU reconstruction state, proceed to step 304; if the anti-fuse FPGA has not entered the CPU reconstruction state, the satellite platform continues to send a command for starting the reconstruction of the CPU to the anti-fuse FPGA through the external data interface. When the anti-fuse FPGA receives the command, it disconnects the CPU from the bus corresponding to the routing software bitstream memory, and the anti-fuse FPGA obtains control of the CPU and erases the software bitstream in the routing software bitstream memory.

[0082] Step 304: The antifuse FPGA receives the seventh external control frame sent by the satellite platform through the data interface, writes the software bit stream carried by the seventh external control frame into the corresponding position of the routing software bit stream memory, and rebuilds the connection between the CPU and the corresponding bus of the routing software bit stream memory. The seventh external control frame is sent by the satellite platform after determining that the antifuse FPGA is in the CPU reconstruction state.

[0083] It should be noted that one implementation of step 304 may be:

[0084] After the satellite platform determines that the anti-fuse FPGA is in the CPU reconstruction state, it sends external control frames for instructing the anti-fuse FPGA to reconstruct the bit stream to the anti-fuse FPGA through the external data interface. After receiving the external control frame, the anti-fuse FPGA writes the software bit stream carried by the external control frame into the corresponding position of the routing software bit stream memory in sequence until the complete routing software bit stream is written into the routing software bit stream memory. Then the anti-fuse FPGA releases the control right of the routing software bit stream memory and re-establishes the connection between the CPU and the corresponding bus of the routing software bit stream memory.

[0085] In summary, the time for reconfiguring the routing CPU is greatly reduced through the function allocation and software optimization of the anti-fuse FPGA.

[0086] Figure 4 This is a schematic diagram of a standardized refresh and reconstruction system for a satellite router provided in an embodiment of this specification, the system includes an SRAM FPGA start-up reconstruction module, an SRAM FPGA bit stream reconstruction module, a format conversion module and a start-up refresh module, see Figure 4 , the device may specifically include:

[0087] The SRAM FPGA reconstruction start module 402 is used to disconnect the dedicated FPGA refresh circuit from the bus corresponding to the exchange software bit stream memory and complete the erasure of the exchange software bit stream memory when the anti-fuse FPGA receives the first external control frame sent by the satellite platform through the data interface, and the first external control frame is used to indicate the start of reconstruction of the SRAM FPGA;

[0088] The SRAM FPGA bit stream reconstruction module 404 is used for the anti-fuse FPGA to receive a second external control frame sent by the satellite platform through the data interface, and write the software bit stream carried by the second external control frame into the corresponding position of the exchange software bit stream memory, and reconstruct the connection between the dedicated FPGA refresh circuit and the corresponding bus of the exchange software bit stream memory, wherein the second external control frame is sent by the satellite platform after determining that the anti-fuse FPGA is in the SRAM FPGA reconstruction state;

[0089] A format conversion module 406 is used for the anti-fuse FPGA to receive a third external control frame sent by the satellite platform through the data interface, and convert the format of the third external control frame into a command of a proprietary frame format of a dedicated FPGA refresh circuit, wherein the third external control frame is used to instruct the dedicated FPGA refresh circuit to start refreshing the reconstructed SRAM FPGA;

[0090] The refresh start module 408 is used for the dedicated FPGA refresh circuit to start refreshing the reconstructed SRAM FPGA based on the software bit stream in the exchange software bit stream memory after receiving the third external control frame.

[0091] Optionally, the system further includes a pre-reconstruction pre-processing module, which is specifically used to:

[0092] The anti-fuse FPGA receives the zeroth external control frame sent by the satellite platform through the data interface, and converts the format of the zeroth external control frame into a command of a proprietary frame format of a dedicated FPGA refresh circuit, wherein the zeroth external control frame is used to instruct the dedicated FPGA refresh circuit to turn off refreshing;

[0093] After receiving the zeroth external control frame, the dedicated FPGA refresh circuit turns off refreshing of the SRAM FPGA.

[0094] Based on this, by confirming that the dedicated FPGA refresh circuit is in the refresh-off state before the SRAM FPGA is reconfigured, conditions are provided for the SRAM FPGA reconstruction and refresh and reconstruction execution errors are avoided.

[0095] Optionally, the system further includes a readback verification module, which is specifically used to:

[0096] The anti-fuse FPGA calculates a check code according to the software bit stream in the exchange software bit stream memory, and the check code is used by the satellite platform to determine whether the reconstruction is correct;

[0097] If the reconstruction is incorrect, the anti-fuse FPGA receives the fourth external control frame sent by the satellite platform through the data interface and executes S1-S4, wherein the fourth external control frame is used to instruct to restart the reconstruction.

[0098] Based on this, the accuracy of software reconstruction is ensured by reading back and checking the software bit stream.

[0099] Optionally, the system further includes a software reset module, specifically used for:

[0100] The anti-fuse FPGA receives the fifth external control frame sent by the satellite platform through the data interface, and controls the watchdog circuit to output a global reset signal, wherein the fifth external control frame is used to indicate a global reset of the circuit;

[0101] The dedicated FPGA refresh circuit reloads the software bit stream in the exchange software bit stream memory according to the global reset signal.

[0102] Based on this, the switching software bit stream is reloaded by resetting the global circuit software.

[0103] Optionally, the system further includes a standardized refresh module, specifically used for:

[0104] The anti-fuse FPGA receives the sixth external control frame sent by the satellite platform through the data interface, and converts the format of the sixth external control frame into a command of a proprietary frame format of the dedicated FPGA refresh circuit, wherein the sixth external control frame is used to instruct the dedicated FPGA refresh circuit to perform standardized refresh on the SRAM FPGA;

[0105] After receiving the sixth external control frame, the dedicated FPGA refresh circuit performs standardized refresh on the SRAM FPGA.

[0106] Based on this, through the function allocation and software optimization of the anti-fuse FPGA, the standardized refresh of the SRAM FPGA is realized, the refresh logic is simplified, and the workload of the refresh operation is reduced.

[0107] In summary, based on a small-scale antifuse FPGA and a dedicated FPGA refresh circuit, through clever function allocation and software design optimization, the standardization and reconstruction joint processing of SRAM FPGA is realized, which reduces the workload of the refresh logic and greatly shortens the software reconstruction time, thus realizing the flexible on-orbit application of the spaceborne router.

[0108] Figure 5 This is a schematic diagram of a satellite router reconfiguration system provided by an embodiment of the present specification, the system comprising a CPU reconfiguration startup module and a CPU bit stream reconfiguration module, wherein:

[0109] The CPU reconstruction start module 502 is used for the anti-fuse FPGA to receive the seventh external control frame sent by the satellite platform through the data interface, disconnect the CPU from the bus corresponding to the routing software bit stream memory, and complete the erasure of the routing software bit stream memory, wherein the seventh external control frame is used to indicate the start of reconstruction of the CPU;

[0110] The CPU bitstream reconstruction module 504 is used for the anti-fuse FPGA to receive the seventh external control frame sent by the satellite platform through the data interface, write the software bitstream carried by the seventh external control frame into the corresponding position of the routing software bitstream memory, and rebuild the connection between the CPU and the corresponding bus of the routing software bitstream memory. The seventh external control frame is sent by the satellite platform after determining that the anti-fuse FPGA is in the CPU reconstruction state.

[0111] In summary, the time for reconfiguring the routing CPU is greatly reduced through the function allocation and software optimization of the anti-fuse FPGA.

[0112] In another feasible embodiment, this embodiment provides a standardized refresh and reconstruction device for a satellite-borne router, and the device may specifically include:

[0113] Processor; and

[0114] A memory arranged to store computer executable instructions, which, when executed, cause the processor to perform the steps in any of the above method embodiments.

[0115] In another feasible embodiment, this embodiment provides a standardized refresh and reconstruction storage medium for a satellite-borne router, and the storage medium may specifically include:

[0116] The storage medium stores a processing program for standardized refresh and reconstruction of onboard routers, and when the processing program for standardized refresh and reconstruction of onboard routers is executed by the processor, the steps in any of the above method embodiments are implemented.

[0117] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims

1. A standardized refresh and reconstruction method for onboard routers, characterized in that: include: S1. When the anti-fuse FPGA receives the first external control frame sent by the satellite platform through the data interface, it disconnects the connection between the dedicated FPGA refresh circuit and the bus corresponding to the exchange software bit stream memory, and completes the erasure of the exchange software bit stream memory. The first external control frame is used to indicate the start of reconstruction of the SRAM FPGA. S2, the anti-fuse FPGA receives a second external control frame sent by the satellite platform through the data interface, writes the software bit stream carried by the second external control frame into the corresponding position of the exchange software bit stream memory, and rebuilds the connection between the dedicated FPGA refresh circuit and the corresponding bus of the exchange software bit stream memory, wherein the second external control frame is sent by the satellite platform after determining that the anti-fuse FPGA is in the SRAM FPGA reconstruction state; S3, the anti-fuse FPGA receives the third external control frame sent by the satellite platform through the data interface, and converts the format of the third external control frame into a command of a proprietary frame format of the dedicated FPGA refresh circuit, wherein the third external control frame is used to instruct the dedicated FPGA refresh circuit to start refreshing the reconstructed SRAM FPGA; S4. After receiving the third external control frame, the dedicated FPGA refresh circuit starts refreshing the reconstructed SRAM FPGA based on the software bit stream in the exchange software bit stream memory.

2. The method according to claim 1, characterized in that When the anti-fuse FPGA receives the first external control frame sent by the satellite platform through the data interface, the dedicated FPGA refresh circuit is disconnected from the bus corresponding to the exchange software bit stream memory, and before the exchange software bit stream memory is erased, the method includes: The anti-fuse FPGA receives the zeroth external control frame sent by the satellite platform through the data interface, and converts the format of the zeroth external control frame into a command of a proprietary frame format of a dedicated FPGA refresh circuit, wherein the zeroth external control frame is used to instruct the dedicated FPGA refresh circuit to turn off refreshing; After receiving the zeroth external control frame, the dedicated FPGA refresh circuit turns off refreshing of the SRAM FPGA.

3. The method according to claim 1, characterized in that The anti-fuse FPGA receives a second external control frame sent by the satellite platform through a data interface, writes the software bit stream carried by the second external control frame into a corresponding position of the exchange software bit stream memory, and reestablishes the connection between the dedicated FPGA refresh circuit and the corresponding bus of the exchange software bit stream memory, including: The anti-fuse FPGA calculates a check code according to the software bit stream in the exchange software bit stream memory, and the check code is used by the satellite platform to determine whether the reconstruction is correct; If the reconstruction is incorrect, the anti-fuse FPGA receives the fourth external control frame sent by the satellite platform through the data interface and executes S1-S4, wherein the fourth external control frame is used to instruct to restart the reconstruction.

4. The method according to claim 1, characterized in that: The anti-fuse FPGA receives a third external control frame sent by the satellite platform through a data interface, and converts the format of the third external control frame into a command of a proprietary frame format of a dedicated FPGA refresh circuit, including: The anti-fuse FPGA receives the fifth external control frame sent by the satellite platform through the data interface, and controls the watchdog circuit to output a global reset signal, wherein the fifth external control frame is used to indicate a global reset of the circuit; The dedicated FPGA refresh circuit reloads the software bit stream in the exchange software bit stream memory according to the global reset signal.

5. The method according to claim 1, characterized in that Also includes: The anti-fuse FPGA receives the sixth external control frame sent by the satellite platform through the data interface, and converts the format of the sixth external control frame into a command of a proprietary frame format of the dedicated FPGA refresh circuit, wherein the sixth external control frame is used to instruct the dedicated FPGA refresh circuit to perform standardized refresh on the SRAM FPGA; After receiving the sixth external control frame, the dedicated FPGA refresh circuit performs standardized refresh on the SRAM FPGA.

6. The method according to claim 1, characterized in that Also includes: The anti-fuse FPGA receives the seventh external control frame sent by the satellite platform through the data interface, disconnects the connection between the CPU and the bus corresponding to the routing software bit stream memory, and completes the erasure of the routing software bit stream memory, wherein the seventh external control frame is used to instruct to start the reconstruction of the CPU; The antifuse FPGA receives the seventh external control frame sent by the satellite platform through the data interface, writes the software bit stream carried by the seventh external control frame into the corresponding position of the routing software bit stream memory, and rebuilds the connection between the CPU and the corresponding bus of the routing software bit stream memory. The seventh external control frame is sent by the satellite platform after determining that the antifuse FPGA is in the CPU reconstruction state.

7. A satellite router reconstruction method, characterized in that: include: The anti-fuse FPGA receives the seventh external control frame sent by the satellite platform through the data interface, disconnects the connection between the CPU and the bus corresponding to the routing software bit stream memory, and completes the erasure of the routing software bit stream memory, wherein the seventh external control frame is used to instruct to start the reconstruction of the CPU; The antifuse FPGA receives the seventh external control frame sent by the satellite platform through the data interface, writes the software bit stream carried by the seventh external control frame into the corresponding position of the routing software bit stream memory, and rebuilds the connection between the CPU and the corresponding bus of the routing software bit stream memory. The seventh external control frame is sent by the satellite platform after determining that the antifuse FPGA is in the CPU reconstruction state.

8. A standardized refresh and reconstruction system for onboard routers, characterized in that: It includes an opening reconstruction module, a reconstruction bit stream module, a format conversion module and an opening refresh module, wherein: The SRAM FPGA reconstruction start module is used to disconnect the connection between the dedicated FPGA refresh circuit and the bus corresponding to the exchange software bit stream memory and complete the erasure of the exchange software bit stream memory when the anti-fuse FPGA receives the first external control frame sent by the satellite platform through the data interface, and the first external control frame is used to indicate the start of reconstruction of the SRAM FPGA; The SRAM FPGA bitstream reconstruction module is used for the anti-fuse FPGA to receive a second external control frame sent by the satellite platform through the data interface, and write the software bitstream carried by the second external control frame into the corresponding position of the exchange software bitstream memory, and rebuild the connection between the dedicated FPGA refresh circuit and the corresponding bus of the exchange software bitstream memory, wherein the second external control frame is sent by the satellite platform after determining that the anti-fuse FPGA is in the SRAM FPGA reconstruction state; A format conversion module, used for the anti-fuse FPGA to receive a third external control frame sent by the satellite platform through a data interface, and convert the format of the third external control frame into a command of a proprietary frame format of a dedicated FPGA refresh circuit, wherein the third external control frame is used to instruct the dedicated FPGA refresh circuit to start refreshing the reconstructed SRAM FPGA; The refresh start module is used for the dedicated FPGA refresh circuit to start refreshing the reconstructed SRAM FPGA based on the software bit stream in the exchange software bit stream memory after receiving the third external control frame.

9. A satellite router reconstruction system, characterized in that: It includes a CPU reconstruction startup module and a CPU bit stream reconstruction module, wherein: A CPU reconstruction start module is used for the anti-fuse FPGA to receive the seventh external control frame sent by the satellite platform through the data interface, disconnect the CPU from the bus corresponding to the routing software bit stream memory, and complete the erasure of the routing software bit stream memory, wherein the seventh external control frame is used to indicate the start of reconstruction of the CPU; The CPU bitstream reconstruction module is used for the anti-fuse FPGA to receive the seventh external control frame sent by the satellite platform through the data interface, write the software bitstream carried by the seventh external control frame into the corresponding position of the routing software bitstream memory, and rebuild the connection between the CPU and the corresponding bus of the routing software bitstream memory. The seventh external control frame is sent by the satellite platform after determining that the anti-fuse FPGA is in the CPU reconstruction state.

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