P-type channel gan hemt device and method of making the same

Abstract

The application provides a p-type channel GaN HEMT device and a preparation method thereof, a plurality of superlattice structures are epitaxially formed on an isolation layer, a first part of the isolation layer is missing, a cavity is formed between the first part of the plurality of superlattice structures and the isolation layer, the first part of the plurality of superlattice structures comprises N fin-type units arranged at intervals, and a part of the N fin-type units located above the cavity corresponds to form N superlattice nanowires, and a gate metal wraps around each superlattice nanowire from all around, wherein each superlattice structure comprises a pAlGaN layer and a pGaN layer formed in sequence in a direction away from the substrate, and each superlattice structure corresponds to form a conductive channel, the application utilizes the plurality of superlattice nanowires to improve the output current of the p-type channel GaN HEMT device, meanwhile, the annular gate metal completely turns off all the conductive channels from all around, the gate control ability and the switching performance of the p-type channel GaN HEMT device are improved, and the performance of the p-type channel GaN HEMT device is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor, in particular to a p-type channel GaN HEMT device and a preparation method thereof. BACKGROUND

[0002] In recent years, GaN HEMT devices are widely used in the field of integrated circuits, especially in the field of high-frequency power circuits, due to the advantages of GaN materials, such as chemical stability, high electron mobility, high temperature resistance, high breakdown voltage, etc.

[0003] At present, GaN HEMT devices commonly use N-type channel GaN HEMT devices, while the hole acceptor of the p-type channel GaN HEMT device is Mg, which is difficult to activate, resulting in low two-dimensional hole gas (2DHG) mobility (~10-20cm 2 / V.s), which is much lower than the mobility of the two-dimensional electron gas (2DEG) of the n-channel (~1000-1500cm 2 / V.s), resulting in a large on-resistance of the device and a small output current. Ultimately, the output current of the p-channel GaN HEMT device under the same size is much smaller than that of the n-channel GaN HEMT device under the same conditions, and the current of the p-type channel GaN HEMT device commonly uses a planar structure, which has a large leakage current, resulting in low reliability of the device.

[0004] Therefore, how to improve the output current of the p-type channel GaN HEMT device while improving the gate control ability of the device has become a technical problem that needs to be solved in the industry. SUMMARY

[0005] The present application provides a p-type channel GaN HEMT device and a preparation method thereof to solve the problem of how to improve the output current of the p-type channel GaN HEMT device while improving the gate control ability of the device.

[0006] According to a first aspect of the present application, a preparation method of a p-type channel GaN HEMT device is provided, comprising:

[0007] providing a substrate;

[0008] forming a buffer layer, an interface layer and an isolation layer on the substrate in sequence in a direction away from the substrate;

[0009] forming a plurality of superlattice structures on the isolation layer, each superlattice structure comprising a pAlGaN layer and a pGaN layer formed in sequence in a direction away from the substrate;

[0010] selectively etching the several-layer superlattice structure to form isolation mesas on both sides of the isolation layer along a first direction;

[0011] selectively etching a first part of the several-layer superlattice structure to form N fin-type units along a first direction, where N is an integer greater than or equal to 2;

[0012] removing the first part of the isolation layer to form a cavity between the first part of the several-layer superlattice structure and the interface layer; wherein a portion of the N fin-type units located above the cavity correspond to form N superlattice nanowires;

[0013] forming a source electrode and a drain electrode on the several-layer superlattice structure in an epitaxial manner, wherein the source electrode and the drain electrode are located on both sides of the cavity along the first direction;

[0014] depositing a gate metal on the periphery of each superlattice nanowire, the gate metal wrapping around the corresponding superlattice nanowire from all sides.

[0015] Optionally, the selectively etching the first part of the several-layer superlattice structure to form N fin-type units along a first direction includes:

[0016] coating a photoresist on the exposed several-layer superlattice structure, exposing and developing the photoresist to form a patterned photoresist;

[0017] using the patterned photoresist as a mask, selectively etching the first part of the several-layer superlattice structure to form N fin-type units along a first direction.

[0018] Optionally, the removing the first part of the isolation layer to form a cavity between the first part of the several-layer superlattice structure and the interface layer includes:

[0019] coating a photoresist on the exposed isolation layer, exposing and developing the photoresist to form a patterned photoresist;

[0020] using the patterned photoresist as a mask, etching the first part of the isolation layer to form a cavity between the first part of the several-layer superlattice structure and the interface layer;

[0021] removing the patterned photoresist to form the isolation layer covering part of the interface layer.

[0022] Optionally, the forming N gate electrodes specifically includes:

[0023] Depositing the gate metal in the N gate regions of the cavity to form the N gates.

[0024] Optionally, before forming the N gates, further comprising:

[0025] Depositing gate dielectric in the N gate regions of the cavity, the gate dielectric surrounding the corresponding superlattice nanowire.

[0026] According to a second aspect of the present application, there is provided a p-type channel GaN HEMT device, comprising:

[0027] a substrate, and a buffer layer, an interface layer and an isolation layer are formed on the substrate in sequence in a direction away from the substrate;

[0028] a plurality of superlattice structures formed on the isolation layer, a first part of the plurality of superlattice structures comprises N fin-type units arranged at intervals, a first part of the isolation layer is missing, so that a cavity is formed between the first part of the plurality of superlattice structures and the isolation layer; wherein N is an integer greater than or equal to 2, each superlattice structure comprises a pAlGaN layer and a pGaN layer formed in sequence in a direction away from the substrate, and a part of the N fin-type units located above the cavity correspond to N superlattice nanowires;

[0029] a source electrode and a drain electrode formed on the plurality of superlattice structures; wherein the source electrode and the drain electrode are located on both sides of the cavity along the first direction;

[0030] a gate metal surrounding each superlattice nanowire.

[0031] Optionally, the surface of the isolation layer along the second direction is wider than the width of the plurality of superlattice structures.

[0032] Optionally, the gate metal is filled in N gate regions of the cavity, and surrounds the corresponding superlattice nanowire.

[0033] Optionally, further comprising a gate dielectric;

[0034] The gate dielectric is wrapped between the gate metal and the superlattice nanowire.

[0035] Optionally, the material of the interface layer is AlN, the material of the gate metal is TiN, and the material of the isolation layer is Al2O3.

[0036] According to a third aspect of the present application, there is provided a method for manufacturing an electronic device, comprising the method for manufacturing the p-type channel GaN HEMT device according to any one of the first aspect of the present application.

[0037] According to a fourth aspect of the present application, there is provided an electronic device comprising the p-type channel GaN HEMT device of any one of the second aspect of the present application.

[0038] The p-type channel GaN HEMT device and the preparation method thereof provided by the present application, by epitaxially forming a plurality of superlattice structures on the isolation layer, the first part of the isolation layer is missing, so that a cavity is formed between the first part of the plurality of superlattice structures and the isolation layer, the first part of the plurality of superlattice structures comprises N fin-type units arranged at intervals, and a part of the N fin-type units located above the cavity corresponds to form N superlattice nanowires, and the gate metal wraps around each superlattice nanowire from all around, wherein each layer of superlattice structure comprises a pAlGaN layer and a pGaN layer formed in turn in a direction away from the substrate; each layer of superlattice structure corresponds to form a conductive channel, the present application uses a plurality of superlattice nanowires to improve the output current of the p-type channel GaN HEMT device, at the same time, the annular gate metal completely turns off all the conductive channels from all around, which improves the gate control ability and switching performance of the p-type channel GaN HEMT device, thereby realizing the effect of improving the performance of the p-type channel GaN HEMT device. BRIEF DESCRIPTION OF DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0040] Figure 1 is a flowchart of a preparation method of a p-type channel GaN HEMT device provided by an embodiment of the present application;

[0041] Figure 2 is a device structure schematic diagram of different process stages of the p-type channel GaN HEMT device prepared according to the preparation method of the p-type channel GaN HEMT device provided by an embodiment of the present application Figure One ;

[0042] Figure 3 is a device structure schematic diagram of different process stages of the p-type channel GaN HEMT device prepared according to the preparation method of the p-type channel GaN HEMT device provided by an embodiment of the present application Figure Two ;

[0043] Figure 4 is a device structure schematic diagram of different process stages of the p-type channel GaN HEMT device prepared according to the preparation method of the p-type channel GaN HEMT device provided by an embodiment of the present application Figure Three ;

[0044] Figure 5is a device structure schematic of different process stages of a p-type channel GaN HEMT device prepared according to the preparation method of the p-type channel GaN HEMT device provided in an embodiment of the present application Figure Four ;

[0045] Figure 6 is a device structure schematic of different process stages of a p-type channel GaN HEMT device prepared according to the preparation method of the p-type channel GaN HEMT device provided in an embodiment of the present application Figure Five ;

[0046] Figure 7 is a device structure schematic of different process stages of a p-type channel GaN HEMT device prepared according to the preparation method of the p-type channel GaN HEMT device provided in an embodiment of the present application Figure Six ;

[0047] Figure 8 is a device structure schematic of different process stages of a p-type channel GaN HEMT device prepared according to the preparation method of the p-type channel GaN HEMT device provided in an embodiment of the present application Figure Seven ;

[0048] Figure 9 is a device structure schematic of different process stages of a p-type channel GaN HEMT device prepared according to the preparation method of the p-type channel GaN HEMT device provided in an embodiment of the present application Figure Eight ;

[0049] Figure 10 is a device structure schematic of different process stages of a p-type channel GaN HEMT device prepared according to the preparation method of the p-type channel GaN HEMT device provided in an embodiment of the present application Figure Nine ;

[0050] BRIEF DESCRIPTION OF THE DRAWINGS

[0051] 101 - substrate

[0052] 102 - buffer layer

[0053] 103 - interface layer

[0054] 104 - isolation layer

[0055] 105 - superlattice layer

[0056] 106 - gate metal

[0057] 107 - gate dielectric

[0058] 108 - source

[0059] 109 - drain

[0060] 1051 - first fin-type unit

[0061] 1052 - second fin-type unit

[0062] 1053 - third fin-type cell

[0063] 10511 - first superlattice structure

[0064] 10512 - second superlattice structure

[0065] 10513 - third superlattice structure

[0066] 10514 - fourth superlattice structure DETAILED DESCRIPTION

[0067] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0068] The terms "first", "second", "third", "fourth" and the like (if any) in the specification and claims of the present application and the above drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or a chronological sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but can include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0069] Since the GaN material has the advantages of chemical stability, high electron mobility, high temperature resistance, high breakdown voltage and the like, it has great application value in power devices;

[0070] However, for the p-type channel GaN HEMT device, due to its large on-resistance and small output current, the output current of the p-type channel GaN HEMT device under the same size is far less than that of the N-channel GaN HEMT device under the same conditions, which also seriously slows down the processing speed of the GaN-based integrated circuit. At the same time, the p-type channel GaN HEMT device has a large leakage current, and the device performance is not good.

[0071] In view of the prior art, it is difficult to improve the output current of the p-type channel GaN HEMT device while improving the gate control ability of the device. The present application provides a p-type channel GaN HEMT device and a preparation method thereof. A plurality of superlattice structures are epitaxially formed on an isolation layer, a first part of the isolation layer is missing, a cavity is formed between the first part of the plurality of superlattice structures and the isolation layer, the first part of the plurality of superlattice structures includes N fin-type units arranged at intervals, and a part of the N fin-type units located above the cavity corresponds to form N superlattice nanowires, and a gate metal wraps around each superlattice nanowire from all around. Each layer of superlattice structure includes a pAlGaN layer and a pGaN layer formed in turn in a direction away from the substrate. Each layer of superlattice structure corresponds to form a conductive channel. The present application uses a plurality of superlattice nanowires to improve the output current of the p-type channel GaN HEMT device, and at the same time, the annular gate metal completely turns off all conductive channels from all around, thereby improving the gate control ability and switching performance of the p-type channel GaN HEMT device, thereby realizing the effect of improving the performance of the p-type channel GaN HEMT device.

[0072] The technical solutions of the present application will be described in detail below with specific examples. The following specific examples can be combined with each other, and the same or similar concepts or processes may not be described in detail in some examples.

[0073] Please refer to Figure 8 and Figure 9 According to an embodiment of the present application, a p-type channel GaN HEMT device is provided, comprising:

[0074] A substrate 101, and a buffer layer 102, an interface layer 103 and an isolation layer 104 are epitaxially formed on the substrate 101 in a direction away from the substrate 101;

[0075] A plurality of superlattice structures are formed on the isolation layer 104, a first part of the plurality of superlattice structures includes N fin-type units arranged at intervals, a first part of the isolation layer 104 is missing, and a cavity is formed between the first part of the plurality of superlattice structures and the isolation layer 104; wherein N is an integer greater than or equal to 2, each layer of superlattice structure includes a pAlGaN layer and a pGaN layer formed in turn in a direction away from the substrate 101, and a part of the N fin-type units located above the cavity corresponds to form N superlattice nanowires;

[0076] A source 108 and a drain 107 are formed on the plurality of superlattice structures; wherein the source 108 and the drain 107 are located on both sides of the cavity in the first direction;

[0077] The gate metal 106 wraps around each superlattice nanowire.

[0078] The gate metal 106 wraps around each superlattice nanowire to form a ring gate structure, which can completely turn off the conductive channel of the p-type channel GaN HEMT device from all sides, increase the control area of the gate on the channel, greatly enhance the gate control ability, effectively suppress the short channel effect, suppress the gate leakage current, reduce the sub-threshold swing and device power consumption, and improve the switching speed and performance of the p-type channel GaN HEMT device.

[0079] In an example, the material of the interface layer 103 is AlN, the material of the gate metal 106 is TiN, and the material of the isolation layer 104 is Al2O3. Of course, the foregoing several structure layers can also be composed of other materials, and the present application is not limited thereto. Any implementation form of the material of the corresponding structure layer is within the protection scope of the present application.

[0080] Regarding the N-finger unit and the superlattice structure, the following is specifically described:

[0081] After the pAlGaN / pGaN material is alternately grown into an ideal superlattice structure, the valence bands of the two materials form a hole microband and an electron microband, and the acceptor ionization rate is significantly improved. The final result is to increase the hole concentration and improve the output current of the p-type channel GaN HEMT device, but the mobility of the two-dimensional hole gas (2DHG) is relatively low (~ 10-20 cm 2 / V.s), which is much lower than the mobility of the two-dimensional electron gas (2DEG) of the N-channel (~ 1000-1500 cm 2 / V.s), and the conductivity is still insufficient. This is because the main dopant of the p-type doped gallium nitride material is Mg, but after doping Mg, the acceptor atom Mg and the residual H atom form a Mg-H complex, causing the passivation effect of Mg. High-temperature annealing or laser annealing can break the Mg-H bond and activate the passivated Mg. However, the carrier concentration does not continue to increase with the increase of the Mg doping concentration. Typically, the hole concentration is 10 18 cm -3 orders of magnitude, but increasing the Mg doping will not increase the carrier concentration. This is because heavy doping will increase the lattice defects and introduce donor levels to compensate for the activated Mg ions. By adopting the mode that the first part of the superlattice structure includes N finger units arranged at intervals, the part of the N finger units located above the cavity corresponds to the formation of N superlattice nanowires. Compared with the previous single conductive channel mode, the output current is increased by N times, so that the output current of the p-type channel GaN HEMT device under the same size is close to that of the n-type channel GaN HEMT device under the same conditions.

[0082] Specifically, in Figure 9 In the example shown, the superlattice layer 105 includes three fin-type units 1051, 1052, 1053; the first fin-type unit 1051 includes a first superlattice structure 1051, a second superlattice structure 1052, a third superlattice structure 1053, and a fourth superlattice structure 1054, a total of four layers of superlattice structures are taken as an example for illustration:

[0083] In one embodiment, please refer to Figure 9 , Figure 9 is a cross-section of the p-type channel GaN HEMT device at N superlattice nanowires. The surface of the isolation layer 104 along the second direction is wider than the width of the plurality of layers of superlattice structures (i.e., the superlattice layer 105), for providing electrical isolation when multiple GaN HEMT devices are connected.

[0084] In a preferred embodiment, please refer to Figure 8 The gate metal 106 is filled in the N gate regions of the cavity, respectively, and wraps around the corresponding superlattice nanowires to form N gates; wherein the gate metal 106 does not contact the interface layer 103. In this case, the N gates can also be connected to each other through an interconnection process, facilitating subsequent application of circuits.

[0085] To increase the reliability of the device, in a further preferred embodiment, please refer to Figure 10 , Figure 10 is a cross-section of the GaN HEMT device at the superlattice nanowires, the p-type channel GaN HEMT device further includes a gate dielectric 107;

[0086] Each of the gate dielectric 107 is wrapped between the corresponding gate metal 106 and the corresponding superlattice nanowire. The gate dielectric 107 acts as an insulating layer to isolate the gate metal 106 and the plurality of conductive channels, and protects the GaN HEMT device when the gate voltage is too high.

[0087] In an example, the material of the gate dielectric 107 is Al2O3, of course, the gate dielectric 107 can also be other materials, the present application is not limited thereto, but also can be SiO2, SiON, HfO2, etc., those skilled in the art can select the appropriate gate dielectric according to actual needs, any corresponding gate dielectric material implementation form is within the protection scope of the present application.

[0088] In addition, please refer to Figures 1-10According to other embodiments of the present application, a method for manufacturing a p-type channel GaN HEMT device is also provided, which comprises the following steps:

[0089] providing a substrate 101;

[0090] forming a buffer layer 102, an interface layer 103 and an isolation layer 104 on the substrate 101 in sequence in a direction away from the substrate 101;

[0091] forming a plurality of superlattice structures on the isolation layer 104, each of which comprises a p-AlGaN layer and a p-GaN layer formed in sequence in a direction away from the substrate 101;

[0092] selectively etching the plurality of superlattice structures to form isolation mesas on both sides of the isolation layer 104 in a first direction;

[0093] selectively etching a first part of the plurality of superlattice structures to form N fin-type units in the first part of the plurality of superlattice structures in the first direction, where N is an integer greater than or equal to 2;

[0094] removing a first part of the isolation layer 104 to form a cavity between the first part of the plurality of superlattice structures and the interface layer 103, wherein a part of the N fin-type units located above the cavity correspond to N superlattice nanowires;

[0095] forming a source electrode 108 and a drain electrode 107 on the plurality of superlattice structures, wherein the source electrode 108 and the drain electrode 107 are located on both sides of the cavity in the first direction;

[0096] depositing a gate metal 106 on the periphery of each superlattice nanowire, wherein the gate metal 106 wraps around the corresponding superlattice nanowire.

[0097] As a specific embodiment, please refer to Figure 1 In actual use, the p-type channel GaN HEMT device is prepared by using the method provided by the embodiments of the present application, as shown in Figures 2-10 The method comprises steps S11-S17, which are as follows:

[0098] S11: providing a substrate 101;

[0099] S12: forming a buffer layer 102, an interface layer 103 and an isolation layer 104 on the substrate 101 in sequence in a direction away from the substrate 101; the device after forming the buffer layer 102, the interface layer 103 and the isolation layer 104 is as shown in Figure 2

[0100] ​S13: epitaxially forming a plurality of superlattice structures on the isolation layer 104;

[0101] Specifically, each superlattice structure includes a pAlGaN layer and a pGaN layer formed in sequence away from the substrate 101. The device after forming the superlattice layer 105 is as shown in FIG. 4B. Figure 3

[0102] S14: selectively etching a first part of the plurality of superlattice structures;

[0103] Specifically, the first part of the plurality of superlattice structures is selectively etched to form N fin-type units in the first direction, where N is an integer greater than or equal to 2. The device after forming the N fin-type units is as shown in FIG. 5B. Figure 5

[0104] Since the selective etching of the first part of the plurality of superlattice structures requires microfabrication, in an example, dry etching can be used to selectively etch the first part of the plurality of superlattice structures, so that the first part of the plurality of superlattice structures forms N fin-type units in the first direction.

[0105] S15: removing a first part of the isolation layer 104;

[0106] Specifically, the first part of the isolation layer 104 is removed to form a cavity between the first part of the plurality of superlattice structures and the interface layer 103. The part of the N fin-type units above the cavity corresponds to the formation of N superlattice nanowires. The device after removing the first part of the isolation layer 104 is as shown in FIG. 6B. Figure 6

[0107] Since the removal of the isolation layer 104 does not require microfabrication, in an example, a wet method (for example, HF solution) can be used to remove the first part of the isolation layer 104, so that all the materials of the first part of the isolation layer 104 are removed.

[0108] S16: epitaxially forming a source 108 and a drain 109 on the plurality of superlattice structures;

[0109] The source 108 and the drain 109 are located on both sides of the cavity in the first direction. The device after forming the source 108 and the drain 109 is as shown in FIG. 7B. Figure 7

[0110] S17: depositing a gate metal 106 on the outer periphery of each superlattice nanowire, respectively;

[0111] ​​​​Specifically, a gate metal 106 is deposited on the periphery of each superlattice nanowire, which wraps around the corresponding superlattice nanowire; and the device after the gate metal 106 wraps around each superlattice nanowire is as shown in FIG. 6. Figure 8

[0112] In an example, the gate metal 106 can be deposited on the periphery of each superlattice nanowire by atomic layer deposition.

[0113] As the preparation of N fin-type units requires precision machining, as an implementation, step S14 can specifically include coating a photoresist on the exposed superlattice structure, exposing and developing the photoresist to form a patterned photoresist.

[0114] Using the patterned photoresist as a mask, the first part of the superlattice structure is selectively etched by plasma to form N fin-type units in the first direction.

[0115] In this case, step S15 can specifically include coating a photoresist on the exposed isolation layer 104, exposing and developing the photoresist to form a patterned photoresist.

[0116] Using the patterned photoresist as a mask, the first part of the isolation layer 104 is etched by wet etching to form a cavity between the first part of the superlattice structure and the interface layer 103.

[0117] The patterned photoresist is removed to form the isolation layer 104 covering part of the interface layer 103.

[0118] In order to optimize the performance of the GaN HEMT device, as a further preferred implementation, step S17 can specifically further include depositing the gate metal 106 in the N gate regions of the cavity to form the N gates; and the device after the N gate regions of the cavity deposit the gate metal 106 to form the N gates is as shown in FIG. 8. Figure 9

[0119] In a preferred implementation, the selective etching of the first part of the superlattice structure in step S14 includes steps S141-S143, specifically as follows:

[0120] S141: sample cleaning of the p-type channel GaN HEMT device;

[0121] ​​This is because in actual production, the surface of the p-type channel GaN HEMT device will have impurities such as organic matter, metal, particles, etc., which will affect the yield, performance and reliability of the device, and sample cleaning of the p-type channel GaN HEMT device can also remove the surface oxide layer and CVD deposited oxide;

[0122] S142: Selective etching of the superlattice structure;

[0123] Specifically, the superlattice structure is selectively etched to form an isolation mesa on both sides of the isolation layer 104 along the first direction.

[0124] This is because space is needed for the gate metal 106 to contact the 2DEG conductive channel corresponding to the superlattice structure on the mesa sidewall, and to provide electrical isolation when multiple GaN HEMT devices are connected. The device after forming the isolation mesa is as shown in Figure 4 .

[0125] S143: Selective etching of the first part of the superlattice structure;

[0126] Specifically, the first part of the superlattice structure is selectively etched to form N fin-type units along the first direction in the first part of the superlattice structure, where N is an integer greater than or equal to 2. The device after forming the N fin-type units is as shown in Figure 5 .

[0127] In a preferred embodiment, step S17 of forming the gate specifically includes steps S171-S172, which are as follows:

[0128] S171: Depositing gate dielectric 107 in the N gate regions of the cavity, respectively, which wraps around the corresponding superlattice nanowire from all sides;

[0129] S172: Depositing the gate metal 106 in the N gate regions of the cavity, respectively, to form the N gates, which wraps around the gate dielectric 107 from all sides. The device after depositing the gate dielectric 107 and the gate metal 106 is as shown in Figure 10 .

[0130] In addition, according to other embodiments of the present application, a method for manufacturing an electronic device is also provided, which includes the preparation method of the p-type channel GaN HEMT device of any one of the first aspect of the present application.

[0131] According to another embodiment of the present application, an electronic device is also provided, which includes the p-type channel GaN HEMT device of any one of the second aspect of the present application.

[0132] In summary, the p-type channel GaN HEMT device and the preparation method thereof provided by the application, by epitaxially forming a plurality of superlattice structures on the isolation layer, the first part of the isolation layer is missing, so that the first part of the plurality of superlattice structures and the isolation layer form a cavity, the first part of the plurality of superlattice structures includes N fin-type units arranged at intervals, and the part of the N fin-type units located above the cavity corresponds to form N superlattice nanowires, and the gate metal wraps around each superlattice nanowire from all around, wherein each layer of superlattice structure includes a pAlGaN layer and a pGaN layer formed in turn in the direction away from the substrate; each layer of superlattice structure corresponds to form a conductive channel, the application uses a plurality of superlattice nanowires to improve the output current of the p-type channel GaN HEMT device, at the same time, the annular gate metal completely turns off all the conductive channels from all around, which improves the gate control ability and switching performance of the p-type channel GaN HEMT device, thereby realizing the effect of improving the performance of the p-type channel GaN HEMT device.

[0133] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the application, and not to limit them; although the application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the application.

Claims

1. A method for fabricating a p-channel GaN HEMT device, characterized in that, include: Provide a substrate; A buffer layer, an interface layer, and an isolation layer are sequentially epitaxially formed on the substrate in a direction away from the substrate. Several superlattice structures are epitaxially formed on the isolation layer, and each superlattice structure includes a pAlGaN layer and a pGaN layer formed sequentially along the direction away from the substrate. Selective etching is performed on the plurality of superlattice structures to form isolation mesas on both sides of the isolation layer along the first direction; Selective etching is performed on the first part of the plurality of superlattice structures to form N fin units along a first direction in the first part of the plurality of superlattice structures, where N is an integer greater than or equal to 2. A first portion of the isolation layer is removed to form a cavity between the first portion of the plurality of superlattice structures and the interface layer; wherein, portions of the N fin units located above the cavity are correspondingly formed into N superlattice nanowires; Sources and drains are epitaxially formed on the plurality of superlattice structures, wherein the source and drain are located on opposite sides of the cavity along the first direction; Gate dielectrics are deposited in N gate regions of the cavity, and the gate dielectrics surround the corresponding superlattice nanowires from all sides. After depositing the gate medium, gate metal is deposited on the outer periphery of each superlattice nanowire, the gate metal enveloping the corresponding superlattice nanowire from all sides.

2. The method for fabricating a p-channel GaN HEMT device according to claim 1, characterized in that, Selective etching is performed on a first portion of the plurality of superlattice layers to form N fin-shaped units along a first direction in the first portion of the plurality of superlattice layers, including: Photoresist is coated onto several exposed superlattice structures, and the photoresist is exposed and developed to form a patterned photoresist. Using the patterned photoresist as a mask, plasma selective etching is employed on the first portion of the plurality of superlattice layers to form N fin units along a first direction in the first portion of the plurality of superlattice layers.

3. The method for fabricating a p-channel GaN HEMT device according to claim 2, characterized in that, Removing a first portion of the isolation layer to form a cavity between the first portion of the plurality of superlattice structures and the interface layer includes: Photoresist is coated on the exposed isolation layer, and the photoresist is exposed and developed to form a patterned photoresist. The first portion of the isolation layer is etched using the patterned photoresist as a mask to form a cavity between the first portion of the plurality of superlattice structures and the interface layer. Remove the patterned photoresist to form the isolation layer covering a portion of the interface layer.

4. The method for fabricating a p-channel GaN HEMT device according to claim 3, characterized in that, Forming N gates, specifically including: The gate metal is deposited in the N gate regions of the cavity to form the N gates.

5. A p-channel GaN HEMT device, characterized in that, include: A substrate, wherein a buffer layer, an interface layer and an isolation layer are sequentially epitaxially formed on the substrate in a direction away from the substrate; A plurality of superlattice structures are formed on the isolation layer. The first part of the plurality of superlattice structures includes N fin units spaced apart. The first part of the isolation layer is missing, so that a cavity is formed between the first part of the plurality of superlattice structures and the isolation layer. Wherein, N is an integer greater than or equal to 2. Each superlattice structure includes a pAlGaN layer and a pGaN layer formed sequentially along the direction away from the substrate, and the portion of the N fin units located above the cavity corresponds to the formation of N superlattice nanowires. The source and drain are formed on the plurality of superlattice structures; wherein the source and drain are located on opposite sides of the cavity along a first direction; Gate metal is used to wrap around each superlattice nanowire. A gate dielectric, which is enclosed between the gate metal and the superlattice nanowire.

6. The p-channel GaN HEMT device according to claim 5, characterized in that, The surface of the isolation layer along the second direction is wider than the width of the plurality of superlattice structures.

7. The p-channel GaN HEMT device according to claim 5, characterized in that, The gate metal fills the N gate regions of the cavity and surrounds the corresponding superlattice nanowires.

8. The p-channel GaN HEMT device according to claim 5, characterized in that, The interface layer is made of AlN, the gate metal is made of TiN, and the isolation layer is made of Al2O3.

9. A method for manufacturing an electronic device, characterized in that, The method for fabricating the p-channel GaN HEMT device according to any one of claims 1 to 4.

10. An electronic device, characterized in that, Includes the p-channel GaN HEMT device according to any one of claims 5-8.

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