PWM conversion analog output digital-to-analog conversion circuit, chip and electronic equipment

Abstract

Embodiments of the present disclosure provide a digital-to-analog conversion circuit, chip, and electronic device for converting PWM to analog output. The digital-to-analog conversion circuit includes a PWM wave generation circuit and a filtering circuit. The PWM wave generation circuit is configured to count a clock signal using a first counter and then generate a PWM wave based on a comparison result between the output value of the first counter and an input digital code value. The number of bits of the first counter is the same as the number of bits of the input digital code value, and the frequency of the clock signal varies with the preset conversion frequency of the digital-to-analog conversion circuit and the number of bits of the input digital code value. The filtering circuit is configured to filter the PWM wave to obtain an analog output signal. This solves the problem of low precision and inconvenient integration of existing DAC circuits of this type.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of integrated circuit technology, and in particular, to a digital-to-analog conversion circuit, chip, and electronic device for PWM conversion of analog output. Background Art

[0002] A digital-to-analog converter (DAC), also known as a digital-to-analog converter (DAC), can be implemented in a variety of ways, with pulse-width modulation (PWM) being a common approach. PWM DACs achieve varying analog output levels by controlling the duty cycle of a clock using a digital code input. The implementation of a PWM DAC typically involves two steps: PWM wave generation and filtering. Currently, there are two main approaches to generating PWM waves in PWM DACs. One approach uses an analog comparator, generating a sawtooth wave (for example, by charging a capacitor with a constant current or using an RC integrator) and a controllable DC voltage level. This generates a PWM wave with an adjustable duty cycle, which can be adjusted by changing the DC voltage level. However, this analog modulation approach requires a large area and consumes a lot of power, while non-ideal factors such as comparator offset can affect modulation accuracy. Another approach uses an external MCU chip to generate the corresponding PWM wave, but this approach is not ideal for integration.

[0003] In summary, how to propose a PWM DAC circuit with high precision and easy integration is an urgent problem to be solved. Summary of the Invention

[0004] The embodiments described herein provide a digital-to-analog conversion circuit, chip, and electronic device for converting PWM to analog output, in order to provide a digital-to-analog conversion circuit for converting PWM to analog output that is highly accurate and easy to integrate.

[0005] According to a first aspect of the present disclosure, a digital-to-analog conversion circuit for PWM conversion of analog output is provided, comprising: a PWM wave generating circuit and a filtering circuit, wherein the PWM wave generating circuit is configured to count a clock signal using a first counter and then generate a PWM wave based on a comparison result between an output value of the first counter and an input digital code value, wherein the number of bits of the first counter is the same as the number of bits of the input digital code value, and the frequency of the clock signal varies with a preset conversion frequency of the digital-to-analog conversion circuit and a change in the number of bits of the input digital code value; and the filtering circuit is configured to filter the PWM wave to obtain an analog output signal.

[0006] Optionally, the PWM wave generating circuit includes: a first counter, multiple first XOR gates, an OR gate, a first trigger, and a second trigger, wherein the input end of the first counter is coupled to the clock signal, and each output end of the first counter is coupled to an input end of a first XOR gate; the other input end of each first XOR gate is coupled to a bit signal of the input digital code value, and the output end of each first XOR gate is coupled to an input end of the OR gate, and the number of first XOR gates is equal to the number of bits of the first counter; the output end of the OR gate is coupled to the clock end of the first trigger, and the input end of the first trigger is respectively coupled to the second output end of the first trigger and the reset end of the second trigger, and the reset end of the first trigger is coupled to the reset end of the first counter; the input end of the second trigger is coupled to the power supply voltage, the clock end of the second trigger is coupled to the clock signal, and the first output end of the second trigger outputs the PWM wave.

[0007] Optionally, the filtering circuit filters the PWM wave through a combination of an RC low-pass filter and a notch filter, and the filtering circuit includes: an RC low-pass filter and a notch filter, wherein the input end of the RC low-pass filter is coupled to the PWM wave, the output end of the RC low-pass filter is coupled to the input end of the notch filter, and the output end of the notch filter outputs the analog output signal.

[0008] Optionally, the notch filter includes: two ping-pong mode sampling and holding circuits and a sampling clock generating circuit, wherein the first end of the first ping-pong mode sampling and holding circuit and the second end of the second ping-pong mode sampling and holding circuit are coupled together and are both coupled to the output end of the RC low-pass filter; the second end of the first ping-pong mode sampling and holding circuit and the first end of the second ping-pong mode sampling and holding circuit are coupled together to output the analog output signal; and the sampling clock generating circuit provides a sampling clock signal for the two ping-pong mode sampling and holding circuits.

[0009] Optionally, the ping-pong mode sampling and holding circuit includes: a first switch, a second switch, and a sampling capacitor, wherein one end of the first switch is coupled to one end of the second switch, the other end of the first switch serves as the first end of the ping-pong mode sampling and holding circuit, and the other end of the second switch serves as the second end of the ping-pong mode sampling and holding circuit; one end of the sampling capacitor is coupled to one end of the first switch and one end of the second switch, respectively, and the other end of the sampling capacitor is coupled to the ground end.

[0010] Optionally, the sampling clock generating circuit includes: a delay module, a second counter, a second XOR gate, a plurality of third XOR gates, a NOR gate, a third trigger, and a non-overlapping clock generating circuit, wherein the input end of the delay module is coupled to the clock signal, and the output end of the delay module is coupled to an input end of the second XOR gate; the other input end of the second XOR gate is coupled to the clock signal, and the output end of the second XOR gate is coupled to the input end of the second counter; the reset end of the second counter is coupled to a reset signal, and the reset signal is a signal of the output signal of the reset end of the first counter delayed by one cycle of the clock signal, and each output end of the second counter is coupled to a first XOR gate. One input terminal of the three XOR gates, the number of bits of the second counter is 1 greater than the number of bits of the input digital code value; another input terminal of one of the multiple third XOR gates is coupled to the ground terminal, and another input terminal of each of the other third XOR gates is coupled to a bit signal of the input digital code value; the output terminal of each third XOR gate is coupled to an input terminal of the NOR gate; the output terminal of the NOR gate is coupled to the clock terminal of the third flip-flop, the input terminal of the third flip-flop is respectively coupled to the second output terminal of the third flip-flop and the input terminal of the non-overlapping clock generation circuit, and the reset terminal of the third flip-flop is coupled to the power supply voltage; the output terminal of the non-overlapping clock generation circuit outputs the sampling clock signal.

[0011] Optionally, the sampling clock signal includes a first sampling clock signal and a second sampling clock signal; wherein the first sampling clock signal controls the first switch, and the second sampling clock signal controls the second switch.

[0012] Optionally, the frequency of the clock signal is twice the preset conversion frequency of the digital-to-analog conversion circuit. N times, where N is the number of bits of the input digital code value.

[0013] Optionally, the delay of the delay module is less than half of the period of the clock signal.

[0014] According to a second aspect of the present disclosure, a chip is provided, comprising a digital-to-analog conversion circuit for PWM conversion of analog output according to any one of the first aspects.

[0015] According to a third aspect of the present disclosure, an electronic device is provided, comprising the chip according to the second aspect.

[0016] The PWM-to-analog conversion circuit, chip, and electronic device of the embodiments of the present disclosure include a PWM wave generating circuit and a filtering circuit, wherein the PWM wave generating circuit is configured to count a clock signal through a first counter, and then generate a PWM wave based on a comparison result between the output value of the first counter and the input digital code value, wherein the number of bits of the first counter is the same as the number of bits of the input digital code value, and the frequency of the clock signal varies with the preset conversion frequency of the PWM-to-analog conversion circuit and the number of bits of the input digital code value; and the filtering circuit is configured to filter the PWM wave to obtain an analog output signal. It can be seen that the PWM wave generating circuit in the PWM-to-analog conversion circuit of the embodiments of the present disclosure is a purely digital circuit, which can improve accuracy compared to the implementation method of an analog comparator. In addition, no additional chip such as an MCU is used, which facilitates integration. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be noted that the drawings described below only relate to some embodiments of the present disclosure and are not intended to limit the present disclosure.

[0018] Figure 1 This is a schematic block diagram of a digital-to-analog conversion circuit for PWM conversion of analog output according to an embodiment of the present disclosure;

[0019] Figure 2 is an exemplary circuit diagram of a PWM wave generating circuit according to an embodiment of the present disclosure;

[0020] Figure 3 yes Figure 2 Output waveforms of each key signal corresponding to the working process;

[0021] Figure 4 is a schematic block diagram of a filter circuit according to an embodiment of the present disclosure;

[0022] Figure 5 is a schematic block diagram of another filtering circuit according to an embodiment of the present disclosure;

[0023] Figure 6 is an exemplary circuit diagram of a ping-pong mode sample-and-hold circuit according to an embodiment of the present disclosure;

[0024] Figure 7 is an exemplary circuit diagram of a sampling clock generating circuit according to an embodiment of the present disclosure;

[0025] Figure 8 yes Figure 7 Output waveforms of various key signals related to the circuit operation process;

[0026] Elements in the drawings are schematic and not drawn to scale. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0028] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant technology, and will not be interpreted in an idealized or overly formal form unless otherwise clearly defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together should refer to the parts being directly combined together or combined through one or more intermediate components. In addition, terms such as "first" and "second" are only used to distinguish one component (or a part of a component) from another component (or another part of a component).

[0029] In order to solve the problems of low precision and inconvenience in integration of existing PWM-to-analog conversion circuits, a new PWM-to-analog conversion circuit is proposed. The PWM-to-analog conversion circuit of the present disclosure is described in detail below.

[0030] like Figure 1 The schematic block diagram of a PWM-to-analog conversion circuit 100 according to an embodiment of the present disclosure includes a PWM wave generating circuit 110 and a filtering circuit 120. The PWM wave generating circuit 110 is configured to count the clock signal CLK1 through a first counter I0, and then calculate the value of the output of the first counter and the input digital code value DIN. <n-1:0>The comparison result generates the PWM wave PWM_OUT, the number of bits of the first counter and the input digital code value DIN <n-1:0>The number of bits is the same as that of the first counter. <n-1:0>The comparison result generates the PWM wave PWM_OUT" as follows: the output value of the first counter and the input digital code value DIN <n-1:0>Perform bit-by-bit comparison. When the output value of the first counter is equal to the input digital code value DIN <n-1:0>At the same time, the PWM wave PWM_OUT is high level, so that the input digital code value DIN can be realized. <n-1:0>When the PWM wave PWM_OUT is changed, the high level of the PWM wave PWM_OUT also changes, that is, a PWM wave with adjustable duty cycle can be obtained. In addition, in order to meet the requirements, the frequency of the clock signal CLK1 needs to be based on the preset conversion frequency f of the digital-to-analog conversion circuit. out , and input digital code value DIN <n-1:0>That is, the frequency of the clock signal CLK1 changes with the preset conversion frequency f of the digital-to-analog conversion circuit. out , and input digital code value DIN <n-1:0>The specific frequency of the clock signal CLK1 is the preset conversion frequency f of the digital-to-analog conversion circuit. out 2 N Times, where N is the input digital code value DIN <n-1:0>The filter circuit 120 is coupled to the PWM wave generating circuit 110 and is configured to filter the PWM wave PWM_OUT to obtain an analog output signal Vout. The specific filter circuit 120 may be a first-order or high-order RC low-pass filter circuit. Figure 5 Figure 121 provides an example diagram of a first-order RC low-pass filter circuit. Of course, in actual applications, other RC low-pass filter circuits that can achieve low-pass filtering can also be used.

[0031] Further, such as Figure 2 As shown, the PWM wave generating circuit 110 includes: a first counter (N-bit Counter) I0, a plurality of first XOR gates 111, an OR gate 112, a first trigger I1, and a second trigger I2, wherein the input terminal of the first counter I0 is coupled to the clock signal CLK1, and each output terminal ZOUT of the first counter I0 is connected to the clock signal CLK1. <n-1:0>coupled to one input terminal of a first XOR gate 111; and the other input terminal of each first XOR gate 111 is coupled to the input digital code value DIN. <n-1:0>The output terminal of each first XOR gate 111 is coupled to an input terminal of an OR gate 112. The number of the first XOR gates 111 is equal to the number of bits of the first counter I0. The output terminal of the OR gate 112 (the signal outputted by the output terminal is C_OK) is coupled to the clock terminal CLK of the first flip-flop I1. The input terminal D of the first flip-flop I1 is respectively coupled to the second output terminal of the first flip-flop I1. The reset terminal of the second trigger I2 The reset terminal of the first trigger I1 The reset terminal Reset of the first counter I0 is coupled; the input terminal D of the second trigger I2 is coupled to the power supply voltage VDD, the clock terminal CLK of the second trigger I2 is coupled to the clock signal CLK1, and the first output terminal Q of the second trigger I2 outputs the PWM wave PWM_OUT.

[0032] Combine Figure 2 The circuit diagram in the figure illustrates the working principle of the PWM wave generating circuit 110: Assuming that for a 3-bit digital-to-analog conversion circuit, the input digital code value DIN <n-1:0>DIN<2:0>, the first counter I0 is a 3-bit counter, the number of the first XOR gates 111 is 3, and the frequency of the clock signal CLK1 is 8*f out When the input digital code value DIN<2:0> is 3'b001, the first counter I0 outputs 3'b001 on the rising edge of the first clock. The output value of the first counter I0 is compared bit by bit with the input digital code value DIN<2:0> through multiple first XOR gates 111, and then added through the OR gate 112 to generate a signal C_OK. C_OK remains at 0 in the first clock cycle and returns to 1 on the rising edge of the second clock. At this time, the first trigger I1 is activated, causing the T_RESET signal to be pulled low, thereby pulling down the value of PWM_OUT on the rising edge of the second clock cycle. The first counter I0 will continue to work until the count reaches 2. 3 =After 8 clock cycles, a reset signal A_RESET of the entire circuit is output to reset I0 and I1. PWM_OUT also returns to a high level at the rising edge of the 9th clock cycle, thus looping this process. Figure 3 The output waveforms of the key signals within 8 clock cycles are shown in Figure 1. From top to bottom, they are: CLK1, C_OK, T_RESET, PWM_OUT, and A_RESET. Similarly, when the input code value DIN<2:0> changes between 3'b000 and 3'b111, the high level time of PWM_OUT also changes accordingly, resulting in a duty cycle of DIN<2:0> / 2. 3 PWM wave, so that the final level can be DIN<2:0> / 2 3 *VDD analog output signal Vout. For the N-bit digital-to-analog conversion circuit, only the number of bits of the first counter I0 and the number of the first XOR gate 111 need to be modified, and the digital logic remains consistent. In addition, it should be noted that the first trigger I1 and the second trigger I2 in the embodiment of the present disclosure are triggers with reset terminals and can be triggered on the rising edge of the clock, for example, Figure 2 The D flip-flop shown in the figure may also be an RS flip-flop, a JK flip-flop, or the like, which may have a reset terminal and may be triggered on the rising edge of the clock.

[0033] According to the above description, it can be seen that the PWM wave generating circuit in the digital-to-analog conversion circuit of the PWM conversion analog output in the embodiment of the present invention is a purely digital circuit, which can improve the accuracy compared with the analog comparator implementation method. In addition, no additional chips such as MCU are used, so it is easy to integrate.

[0034] Furthermore, for the filter circuit 120 in the above embodiment, since the circuit obtains the analog level through first-order or high-order RC low-pass filtering, this solution will cause the output analog signal to have large ripples (for example: Figure 8 RC_OUT is based on Figure 5 The waveform diagram of the PWM wave PWM_OUT after being filtered by the RC low-pass filter 121 in FIG. 1 shows a large ripple), and when the RC value is large, the settling time is very long. In order to solve the problem of large ripple, the embodiment of the present disclosure provides a new implementation method of the filter circuit 120. Specifically, the filter circuit 120 filters the PWM wave PWM_OUT through a combination of an RC low-pass filter and a notch filter to obtain an analog output signal Vout. The PWM wave PWM_OUT is first subjected to preliminary low-pass filtering by the RC low-pass filter. Usually, after passing through the RC low-pass filter, it will show a ripple similar to a triangular wave, and the frequency of this ripple is the preset conversion frequency f of the digital-to-analog conversion circuit. out Therefore, a notch filter is considered to reduce the ripple of the analog output signal Vout. Figure 4 An exemplary block diagram of the filter circuit 120 provided in an embodiment of the present disclosure is shown. Figure 4 As shown, the filter circuit 120 includes: an RC low-pass filter 121 and a notch filter 122, wherein the input end of the RC low-pass filter 121 is coupled to the PWM wave PWM_OUT, the output end of the RC low-pass filter (output end outputs RC_OUT signal) is coupled to the input end of the notch filter 122, and the output end of the notch filter 122 outputs the analog output signal Vout. Figure 5 As shown, the RC low-pass filter 121 includes a filter resistor R and a filter capacitor C. The filter resistor R and the filter capacitor C form a first-order RC low-pass filter 121, which performs preliminary filtering on the PWM wave PWM_OUT output by the PWM wave generating circuit 110. It should be noted that, Figure 4 The RC low-pass filter 121 in the embodiment may also be other forms of RC low-pass filter structures. Figure 5 This is just an example, for example, it can also be a high-order RC low-pass filter structure. Figure 5 As shown, the notch filter 122 includes: two ping-pong mode sample-and-hold circuits 1221 and a sampling clock generating circuit 1222. A first terminal of the first ping-pong mode sample-and-hold circuit 1221 and a second terminal of the second ping-pong mode sample-and-hold circuit 1221 are coupled together and are both coupled to the output terminal of the RC low-pass filter 121. A second terminal of the first ping-pong mode sample-and-hold circuit 1221 and a first terminal of the second ping-pong mode sample-and-hold circuit 1221 are coupled together and output an analog output signal Vout. The sampling clock generating circuit 1222 provides a sampling clock signal (fout) for the two ping-pong mode sample-and-hold circuits 1221. s 、 ). Further, Figure 6 FIG. 1 shows an exemplary circuit diagram of two ping-pong mode sample-and-hold circuits 1221. Figure 6 As shown, the ping-pong mode sampling and holding circuit 1221 includes: a first switch S1, a second switch S2, and a sampling capacitor C0, wherein one end of the first switch S1 is coupled to one end of the second switch S2, the other end of the first switch S1 serves as the first end of the ping-pong mode sampling and holding circuit 1221, and the other end of the second switch S2 serves as the second end of the ping-pong mode sampling and holding circuit 1221; one end of the sampling capacitor C0 is coupled to one end of the first switch S1 and one end of the second switch S2, respectively, and the other end of the sampling capacitor C0 is coupled to the ground end. Specifically, the sampling clock signal includes a first sampling clock signal Second sampling clock signal The first sampling clock signal f s and the second sampling clock signal do not overlap; wherein the first sampling clock signal f s Control the first switch S1, the second sampling clock signal Control the second switch S2. Sampling clock signal (f s 、 ) is the preset conversion frequency f of the digital-to-analog conversion circuit. out half of the center frequency of the notch filter 122, thereby making the center frequency of the notch filter 122 f out , so that sampling is always performed on the same side slope of RC_OUT, reducing DC level offset and ripple. And through the sampling clock signal (f s 、 ) can ensure that the generation logic of different input digital code values ​​DIN <n-1:0>Each sampling point of the control corresponds to the middle point of the high level of PWM_OUT, and finally the analog output signal Vout is obtained. Vout is the level of DIN <n-1:0> / 2 N *Analog value of VDD.

[0035] Further, Figure 7 shows the method for generating the sampling clock signal (f s 、 ) is an exemplary circuit diagram of the sampling clock generating circuit 1222. Figure 7 As shown, the sampling clock generation circuit 1222 includes: a delay module I3, a second counter ((N+1)-bit Counter) I4, a second XOR gate 12221, multiple third XOR gates 12222, a NOR gate 12223, a third flip-flop I5, and a non-overlapping clock generator I6. An input terminal of the delay module I3 is coupled to the clock signal CLK1, and an output terminal of the delay module I3 is coupled to one input terminal of the second XOR gate 12221. Another input terminal of the second XOR gate 12221 is coupled to the clock signal CLK1, and an output terminal of the second XOR gate 12221 (output terminal outputting a CLK_D signal) is coupled to an input terminal of the second counter I4. A reset terminal Reset of the second counter I4 is coupled to a reset signal A_RESET_D, which is an output signal A_RESET of the reset terminal Reset of the first counter I0 delayed by one cycle of the clock signal CLK1. Each output terminal ZOUT of the second counter I4 is coupled to a reset signal A_RESET_D. <n:0>Coupled to an input terminal of a third XOR gate 12222, the number of bits of the second counter I4 is greater than the input digital code value DIN <n-1:0>Another input terminal of one of the third XOR gates 12222 is coupled to the ground terminal GND, and another input terminal of each of the other third XOR gates 12222 is coupled to the input digital code value DIN <n-1:0>The output terminal of each third XOR gate 12222 is coupled to an input terminal of the NOR gate 12223; the output terminal of the NOR gate 12223 (the output terminal outputs the D_OK signal) is coupled to the clock terminal CLK of the third flip-flop I5, and the input terminal D of the third flip-flop I5 is respectively coupled to the second output terminal of the third flip-flop I5. The input terminal of the non-overlapping clock generating circuit I6 and the reset terminal of the third trigger I5 The output terminal of the non-overlapping clock generating circuit I6 outputs a sampling clock signal (f s 、 ). In addition, it should be noted that the third trigger I5 in the embodiment of the present disclosure is a trigger with a reset terminal and can be triggered on the rising edge of the clock, for example, Figure 7 The D flip-flop shown in the figure may also be an RS flip-flop, a JK flip-flop, or the like, which may have a reset terminal and may be triggered on the rising edge of the clock.

[0036] Combine Figure 7 The working principle of the sampling clock generation circuit 1222 is described as follows: first, the clock signal CLK1 is delayed for a period of time by the delay module I3, and then the output result of the delay module I3 is XORed with the clock signal CLK1 to generate a double-frequency clock signal CLK_D signal, which is then counted by a (N+1)-bit second counter I4 (where N is the input digital code value DIN). <n-1:0>The reason for this is that after multiplying CLK1, the middle point of the high level of PWM_OUT is at the 1st (DIN) of the CLK_D signal. <n:0>+1) at the rising edge of the clock, the reset signal A_RESET_D of the second counter I4 is obtained by delaying the previous A_RESET signal by 1 CLK1 cycle. Using the A_RESET_D signal as the reset signal of the second counter I4 can skip the counting of the first cycle of CLK_D, thereby avoiding the implementation of the +1 circuit (avoiding the circuit design of adding 1 to the original code value, because if an adder is required for addition, it will increase the area consumption. The present disclosure adds 1 to the clock and achieves the same effect through clock delay, which can reduce the area consumption). It should be noted here that the delay of the delay module I3 depends on the clock rate of CLK1. Specifically, the delay time can take any value that is less than 1 / 2 times the clock period of the clock signal CLK1. Taking N=3 as an example to illustrate the subsequent circuit principle, when the output value ZOUT<3:0> of the second counter I4 corresponds to the input digital code value DIN<2:0>, D_OK is a high level. At this time, the second output terminal of I5 The output signal CLKOUT flips, and after the next I4 reset and DIN<2:0> CLK_D cycles, CLKOUT flips again. Therefore, each time CLKOUT flips in the middle of the high level of PWM_OUT, a non-overlapping clock generation circuit I6 can adaptively generate a sampling and holding clock signal, that is, a sampling clock signal (f s 、 In addition, it should be noted that for the N-bit digital-to-analog conversion circuit, only the number of bits of the second counter I4 and the number of the third XOR gates 12222 need to be modified, and the digital logic remains consistent.

[0037] Further, Figure 8 The sampling clock signal (f s 、 ) The output waveforms of each key signal in the generation process. Figure 8 As shown, from top to bottom: CLK1, CLK_D, PWM_OUT, A_RESET_D, D_OK, f s 、 The waveform diagram of Vout and RC_OUT corresponds to Sampling, where Sampling is the sampling point. It can be seen that sampling is always performed on the same side of the slope as RC_OUT, reducing the DC level offset. The ripple of the analog output signal Vout is significantly suppressed compared to RC_OUT.

[0038] Based on the above description, it can be seen that the addition of a notch filter to the filtering stage of the PWM-to-analog conversion circuit of the disclosed embodiment can significantly reduce the ripple of the output analog signal. Building on the aforementioned embodiments, the PWM-to-analog conversion circuit of the disclosed embodiment is a high-precision, easily integrated, and low-ripple DAC circuit.

[0039] The present disclosure also provides a chip including a digital-to-analog conversion circuit for converting PWM to analog output according to the present disclosure. The chip is, for example, a chip for performing high-precision digital-to-analog signal conversion.

[0040] An embodiment of the present disclosure further provides an electronic device. The electronic device includes a chip according to an embodiment of the present disclosure. The electronic device is, for example, an automatic test device or an industrial process control device.

[0041] The flow charts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the apparatus and method according to multiple embodiments of the present disclosure. In this regard, each box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and the part of the module, program segment or instruction contains one or more executable instructions for realizing the specified logical function. In some alternative implementations, the functions marked in the box can also occur in a sequence different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented by a dedicated hardware-based system that performs the specified function or action, or can be implemented by a combination of dedicated hardware and computer instructions.

[0042] Unless the context clearly indicates otherwise, as used herein and in the appended claims, the singular includes the plural, and vice versa. Thus, when referring to the singular, the plural of the corresponding term is generally included. Similarly, the words "include" and "comprising" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it follows a group of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or comprehensive.

[0043] Further aspects and scope of adaptability become apparent from the description provided herein. It should be understood that various aspects of the present disclosure can be implemented individually or in combination with one or more other aspects. It should also be understood that the description and specific embodiments herein are intended to be illustrative only and are not intended to limit the scope of the present disclosure.

[0044] Several embodiments of the present disclosure have been described in detail above, but it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The scope of protection of the present disclosure is defined by the appended claims.

Claims

1. A digital-to-analog conversion circuit for PWM conversion analog output, characterized in that: include: PWM wave generating circuit, filtering circuit, The PWM wave generating circuit is configured to count a clock signal through a first counter and then generate a PWM wave based on a comparison result between an output value of the first counter and an input digital code value. The number of bits of the first counter is the same as the number of bits of the input digital code value. The conversion frequency of the digital-to-analog conversion circuit varies with the frequency of the clock signal and the number of bits of the input digital code value. The filtering circuit is configured to filter the PWM wave to obtain an analog output signal; The PWM wave generating circuit includes: a first counter, a plurality of first XOR gates, an OR gate, a first trigger, and a second trigger, wherein the input end of the first counter is coupled to the clock signal, and each output end of the first counter is coupled to an input end of a first XOR gate; the other input end of each first XOR gate is coupled to a bit signal of the input digital code value, and the output end of each first XOR gate is coupled to an input end of the OR gate, and the number of the first XOR gates is equal to the number of bits of the first counter; the output end of the OR gate is coupled to the clock end of the first trigger, the input end of the first trigger is respectively coupled to the second output end of the first trigger and the reset end of the second trigger, and the reset end of the first trigger is coupled to the reset end of the first counter; the input end of the second trigger is coupled to the power supply voltage, the clock end of the second trigger is coupled to the clock signal, and the first output end of the second trigger outputs the PWM wave.

2. The digital-to-analog conversion circuit for PWM conversion analog output according to claim 1, characterized in that: The filtering circuit filters the PWM wave through a combination of an RC low-pass filter and a notch filter. The filtering circuit includes: an RC low-pass filter and a notch filter. The input end of the RC low-pass filter is coupled to the PWM wave, the output end of the RC low-pass filter is coupled to the input end of the notch filter, and the output end of the notch filter outputs the analog output signal.

3. The digital-to-analog conversion circuit for PWM conversion analog output according to claim 2, characterized in that: The notch filter includes: two ping-pong mode sampling and holding circuits, a sampling clock generating circuit, wherein a first terminal of the first ping-pong mode sample-and-hold circuit and a second terminal of the second ping-pong mode sample-and-hold circuit are coupled together and are both coupled to the output terminal of the RC low-pass filter; and a second terminal of the first ping-pong mode sample-and-hold circuit and a first terminal of the second ping-pong mode sample-and-hold circuit are coupled together to output the analog output signal; The sampling clock generating circuit provides a sampling clock signal for two ping-pong mode sampling and holding circuits.

4. The digital-to-analog conversion circuit for PWM conversion analog output according to claim 3, characterized in that: The ping-pong mode sampling and holding circuit includes: a first switch, a second switch, and a sampling capacitor. One end of the first switch is coupled to one end of the second switch, the other end of the first switch serves as the first end of the sample-and-hold circuit in the ping-pong mode, and the other end of the second switch serves as the second end of the sample-and-hold circuit in the ping-pong mode; One end of the sampling capacitor is coupled to one end of the first switch and one end of the second switch respectively, and the other end of the sampling capacitor is coupled to the ground.

5. The digital-to-analog conversion circuit for PWM conversion analog output according to claim 3, characterized in that: The sampling clock generating circuit includes: a delay module, a second counter, a second XOR gate, a plurality of third XOR gates, a NOR gate, a third trigger, and a non-overlapping clock generating circuit. Wherein, an input end of the delay module is coupled to the clock signal, and an output end of the delay module is coupled to an input end of the second XOR gate; Another input terminal of the second XOR gate is coupled to the clock signal, and an output terminal of the second XOR gate is coupled to an input terminal of the second counter; A reset terminal of the second counter is coupled to a reset signal, wherein the reset signal is a signal obtained by delaying the output signal of the reset terminal of the first counter by one cycle of the clock signal, each output terminal of the second counter is coupled to an input terminal of a third XOR gate, and the number of bits of the second counter is one greater than the number of bits of the input digital code value; Another input terminal of one of the plurality of third XOR gates is coupled to the ground terminal, and another input terminal of each of the other third XOR gates is coupled to a bit signal of the input digital code value; an output terminal of each third XOR gate is coupled to an input terminal of the NOR gate; The output terminal of the NOR gate is coupled to the clock terminal of the third flip-flop, the input terminal of the third flip-flop is respectively coupled to the second output terminal of the third flip-flop and the input terminal of the non-overlapping clock generating circuit, and the reset terminal of the third flip-flop is coupled to the power supply voltage; The output terminal of the non-overlapping clock generating circuit outputs the sampling clock signal.

6. The digital-to-analog conversion circuit for PWM conversion and analog output according to claim 4, characterized in that: The sampling clock signal includes a first sampling clock signal and a second sampling clock signal; The first sampling clock signal controls the first switch, and the second sampling clock signal controls the second switch.

7. The digital-to-analog conversion circuit for PWM conversion and analog output according to any one of claims 1 to 6, characterized in that: The frequency of the clock signal is 2 times the conversion frequency of the digital-to-analog conversion circuit. N times, where N is the number of bits of the input digital code value.

8. A chip, characterized in that: A digital-to-analog conversion circuit comprising a PWM conversion analog output according to any one of claims 1-7.

9. An electronic device, characterized in that: Comprising the chip according to claim 8.

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