Driving circuit, display device

Abstract

The present application provides a driving circuit and a display device, and relates to the field of display technology. The driving circuit includes: a plurality of driving units arranged in cascade, the driving units are electrically connected to at least one row of sub-pixels, and the driving units include: a starting row control module, which is configured to designate one row of sub-pixels as a switching starting row under the control of a starting row designation signal output by the starting row designation signal line; a latch module, which is configured to latch the starting row designation signal; a starting row trigger module, which is configured to trigger the switching starting row to start scanning under the control of a trigger signal output by the trigger signal line; in this way, when full-screen display is not required or the power of the display device is low, scanning can be realized from any switching starting row, so that the data of some sub-pixels are not updated, local display is realized, and the power consumption of the display is reduced, and the standby time of the display device is extended.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a driving circuit and a display device. Background Art

[0002] With the rapid development of display technology, electronic products are updated very quickly, and are moving towards lighter, thinner, more sophisticated and with ultra-long standby time. In order to improve customer experience, existing electronic products require longer standby time. The driving circuits of current display products are difficult to meet the low power consumption requirements.

[0003] At present, there is an urgent need to provide a display device with strong driving capability, low power consumption and long standby time to meet the development needs of the industry. Summary of the invention

[0004] The embodiments of the present application adopt the following technical solutions:

[0005] In a first aspect, a driving circuit is provided, comprising: a plurality of driving units arranged in cascade, the driving units being electrically connected to at least one row of sub-pixels, the driving units comprising:

[0006] a start row control module, electrically connected to the first signal output terminal, the start row designation signal line and the first node of the driving unit at this stage, and configured to designate one row of the sub-pixels as a switching start row under the control of the start row designation signal output by the start row designation signal line;

[0007] a latch module, electrically connected to the start row designation signal line, the reset signal line, the first level signal line, the second level signal line, the first node and the second node, respectively, and configured to latch the start row designation signal;

[0008] The start row trigger module is electrically connected to the second node, the trigger signal line, the second level signal line and the third node respectively, and is configured to trigger the switching start row to start scanning under the control of the trigger signal output by the trigger signal line.

[0009] In some embodiments of the present application, the driving unit further includes:

[0010] The signal input module is electrically connected to the first control signal line and the second control signal line, respectively, and is configured to input an enable signal to the switching start line under the joint control of the signals output by the first control signal line and the second control signal line, and control the drive circuit to scan starting from the switching start line in the direction of decreasing the number of sub-pixel rows or increasing the number of sub-pixel rows.

[0011] In some embodiments of the present application, the driving unit further includes:

[0012] An end row control module is electrically connected to the third node, the signal input module, the end row designation signal line, the second level signal line and the fifth node, respectively, and is configured to designate one of the multiple rows of sub-pixels as a switching end row under the control of the enable signal output by the signal input module, the signal at the third node position and the end row designation signal input by the end designation signal line.

[0013] In some embodiments of the present application, the driving unit further includes:

[0014] The shift register module is electrically connected to the fifth node, the first clock signal line, the second clock signal line, the reset signal line, the second level signal line, and the first signal output terminal and the second signal output terminal of the driving unit, respectively, and is configured to realize row-by-row scanning between the switching start row and the switching end row under the joint control of the signal at the fifth node position, the first clock signal input by the first clock signal line, and the second clock signal input by the second clock signal line.

[0015] In some embodiments of the present application, the signal input module includes a forward scan input submodule and a reverse scan input submodule; the forward scan input submodule and the reverse scan input submodule are connected together and electrically connected to the end line control module;

[0016] The positive scan input submodule is electrically connected to the positive scan signal line, the first control signal line and the second control signal line respectively, and is configured to output the positive scan signal transmitted by the positive scan signal line under the common control of the first control signal input by the first control signal line and the second control signal input by the second control signal line;

[0017] The reverse sweep input submodule is electrically connected to the reverse sweep signal line, the first control signal line and the second control signal line respectively, and is configured to output the reverse sweep signal transmitted by the reverse sweep signal line under the common control of the first control signal input by the first control signal line and the second control signal input by the second control signal line;

[0018] Wherein, the end row control module is configured to be able to receive the forward scanning signal or the reverse scanning signal, the forward scanning signal is configured to be able to control the driving circuit to scan from the switching starting row along the direction of increasing number of sub-pixel rows, and the reverse scanning signal is configured to be able to control the driving circuit to scan from the switching starting row along the direction of decreasing number of sub-pixel rows.

[0019] In some embodiments of the present application, the start row control module includes a first NAND gate subcircuit and a first inverter;

[0020] The first signal output terminal of the driving unit at this level and the starting row designated signal line are electrically connected to the two input terminals of the first NAND gate sub-circuit respectively, the input terminal of the first inverter is electrically connected to the output terminal of the first NAND gate sub-circuit, and the output terminal of the first inverter is electrically connected to the first node.

[0021] In some embodiments of the present application, the latch module includes a first transistor, a first NOR gate subcircuit, a second transistor, a third transistor, and a fourth transistor;

[0022] The gate of the first transistor is electrically connected to the reset signal line, the source of the first transistor is electrically connected to the start row designation signal line, and the drain of the first transistor is electrically connected to an input terminal of the first NOR gate sub-circuit and the second node respectively;

[0023] Two input terminals of the first NOR gate sub-circuit are electrically connected to the first node and the second node respectively, and an output terminal of the first NOR gate sub-circuit is electrically connected to the gate of the third transistor and the gate of the fourth transistor respectively;

[0024] The gate of the second transistor is electrically connected to the reset signal line, the source of the second transistor is electrically connected to the first level signal line, and the drain of the second transistor is electrically connected to the source of the third transistor;

[0025] The drain of the third transistor, the source of the fourth transistor, and the second node are electrically connected together, and the drain of the fourth transistor is electrically connected to the second level signal line.

[0026] In some embodiments of the present application, the start row trigger module includes a second inverter, a first transmission gate and a fifth transistor;

[0027] An input terminal of the second inverter is electrically connected to the second node, and an output terminal of the second inverter is electrically connected to the gate of the fifth transistor and the first control terminal of the first transmission gate respectively;

[0028] The second control terminal of the first transmission gate is electrically connected to the second node, the input terminal of the first transmission gate is electrically connected to the trigger signal line, and the output terminal of the first transmission gate is electrically connected to the third node;

[0029] A source of the fifth transistor is electrically connected to the second-level signal line, and a drain of the fifth transistor is electrically connected to the third node.

[0030] In some embodiments of the present application, the forward scan input submodule includes a second transmission gate, and the reverse scan input submodule includes a third transmission gate;

[0031] The first control end of the second transmission gate is electrically connected to the first control signal line, the second control end of the second transmission gate is electrically connected to the second control signal line, the input end of the second transmission gate is electrically connected to the positive scan signal line, and the output end of the second transmission gate is connected to the end line control module;

[0032] The first control end of the third transmission gate is electrically connected to the second control signal line, the second control end of the third transmission gate is electrically connected to the first control signal line, the input end of the third transmission gate is electrically connected to the reverse scan signal line, and the output end of the third transmission gate is connected to the end line control module;

[0033] An output terminal of the second transmission gate is connected to an output terminal of the third transmission gate.

[0034] In some embodiments of the present application, the end row control module includes a third inverter, a fourth transmission gate, a sixth transistor, a second NOR gate subcircuit and a fourth inverter;

[0035] The input end of the third inverter is electrically connected to the end row designation signal line and the gate of the sixth transistor, and the output end of the third inverter is electrically connected to the second control end of the fourth transmission gate;

[0036] The first control terminal of the fourth transmission gate is electrically connected to the input terminal of the third inverter, the input terminal of the fourth transmission gate is electrically connected to the signal input module, and the output terminal of the fourth transmission gate is electrically connected to the fourth node;

[0037] A source of the sixth transistor is electrically connected to the second level signal line, and a drain of the sixth transistor is electrically connected to the fourth node;

[0038] Two input terminals of the second NOR gate subcircuit are electrically connected to the third node and the fourth node respectively, an output terminal of the second NOR gate subcircuit is electrically connected to an input terminal of the fourth inverter, and an output terminal of the fourth inverter is electrically connected to the fifth node.

[0039] In some embodiments of the present application, the shift register module includes a fifth inverter, a first tri-state inverter, a second tri-state inverter, a fifth transmission gate, a sixth inverter, a seventh transistor, and an eighth transistor;

[0040] The input end of the fifth inverter is electrically connected to the first clock signal line, and the output end of the fifth inverter is electrically connected to the first control end of the first tri-state inverter and the second control end of the second tri-state inverter respectively;

[0041] The second control terminal of the first tri-state inverter is electrically connected to the first clock signal line, the input terminal of the first tri-state inverter is electrically connected to the fifth node, and the output terminal of the first tri-state inverter is electrically connected to the gate of the seventh transistor and the input terminal of the sixth inverter respectively;

[0042] The first control terminal of the second tri-state inverter is electrically connected to the first clock signal line, the input terminal of the second tri-state inverter is electrically connected to the sixth node, and the output terminal of the second tri-state inverter is electrically connected to the gate of the seventh transistor and the input terminal of the sixth inverter respectively;

[0043] The output end of the sixth inverter is electrically connected to the sixth node and the second signal output end of the driving unit at this stage respectively;

[0044] The first control end of the fifth transmission gate is electrically connected to the output end of the first tri-state inverter and the output end of the second tri-state inverter respectively, the second control end of the fifth transmission gate is electrically connected to the output end of the sixth inverter, the input end of the fifth transmission gate is electrically connected to the second clock signal line, and the output end of the fifth transmission gate is electrically connected to the first signal output end of the driving unit at this stage;

[0045] The source of the seventh transistor is electrically connected to the second-level signal line, and the drain of the seventh transistor is electrically connected to the first signal output terminal of the driving unit at this level; the gate of the eighth transistor is electrically connected to the reset signal line, the source of the eighth transistor is electrically connected to the sixth node, and the drain of the eighth transistor is electrically connected to the second-level signal line.

[0046] In some embodiments of the present application, the latch module includes a first transistor, a second transistor, a third transistor and a fourth transistor; the start line trigger module includes a fifth transistor;

[0047] The first transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor have the same polarity; the second transistor and the third transistor have the same polarity; and the first transistor and the second transistor have opposite polarities.

[0048] In some embodiments of the present application, the first transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor are all N-type transistors, and the second transistor and the third transistor are all P-type transistors.

[0049] In some embodiments of the present application, in the resolution-triggered display frame stage, the signal output by the first signal output terminal of the driving unit connected to the switching start row is consistent with the start row designation signal.

[0050] In some embodiments of the present application, in the resolution switching display frame stage, the signal output by the first signal output terminal of the driving unit connected to the switching start row is consistent with the start row designation signal.

[0051] In some embodiments of the present application, in a resolution switching display frame, the start row designation signal is a low-level signal with a constant voltage.

[0052] In some embodiments of the present application, a falling edge of the trigger signal is aligned with a rising edge of the start row designation signal in the resolution switching display frame phase.

[0053] In some embodiments of the present application, during the resolution switching display frame stage, a signal output from a first signal output terminal of the driving unit connected to the switching end row is consistent with the end row designation signal.

[0054] In some embodiments of the present application, a pulse width of the clock signal in the resolution-triggered display frame phase is smaller than a pulse width of the clock signal in the resolution-switched display frame phase.

[0055] In some embodiments of the present application, the driving units connected to at least two adjacent rows of sub-pixels are electrically connected to the same clock signal line.

[0056] In a second aspect, an embodiment of the present application provides a display device, comprising a driving circuit as described in any one of the first aspects.

[0057] In some embodiments of the present application, when the resolution of the picture displayed in the resolution switching display frame stage is less than or equal to half of the resolution of the picture displayed in the resolution triggering display frame stage, the refresh rate of the resolution switching display frame stage is greater than the refresh rate of the resolution triggering display frame stage.

[0058] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0060] Figure 1 A schematic diagram of a display screen area of ​​a display device provided in an embodiment of the present application;

[0061] Figure 2 A schematic diagram of a region of a partial display screen of a display device provided in an embodiment of the present application;

[0062] Figure 3 A schematic diagram of a region of a partial display screen of another display device provided in an embodiment of the present application;

[0063] Figure 4 A circuit diagram of a driving circuit provided in an embodiment of the present application;

[0064] Figure 5 A circuit diagram of another driving circuit provided in an embodiment of the present application;

[0065] Figure 6 A circuit diagram of another driving circuit provided in an embodiment of the present application;

[0066] Figure 7 A schematic diagram of a cascaded driving circuit provided in an embodiment of the present application;

[0067] Figure 8 A timing diagram of a conventional drive scan of a drive circuit provided in an embodiment of the present application;

[0068] Fig. 9 A timing diagram of resolution switching of a driving circuit provided in an embodiment of the present application;

[0069] Fig.10 A timing diagram of another driving circuit resolution switching provided in an embodiment of the present application;

[0070] Fig.11 A timing diagram of switching the resolution of a driving unit in a row before the switching start row provided in an embodiment of the present application;

[0071] Fig.12 A timing diagram of resolution switching of a driving unit for switching a start row provided in an embodiment of the present application;

[0072] Fig.13 A timing diagram of switching the resolution of a driving unit in a row after switching the starting row provided in an embodiment of the present application;

[0073] Fig.14 A timing diagram of resolution switching of a driving unit of a switching end row provided in an embodiment of the present application;

[0074] Fig.15 A timing diagram of resolution switching of a driving unit in a row after a switching end row provided in an embodiment of the present application;

[0075] Fig.16 A diagram illustrating the relationship between various signals in a timing diagram provided in an embodiment of the present application;

[0076] Fig.17 A schematic diagram of a signal timing for increasing the pulse width of a clock signal in a resolution switching frame stage provided by an embodiment of the present application;

[0077] Fig.18 A schematic diagram of a signal timing for a driving circuit provided in an embodiment of the present application to simultaneously drive two rows of sub-pixels. DETAILED DESCRIPTION

[0078] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0079] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiment", "example", "specific example" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present application. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics described may be included in any one or more embodiments or examples in any appropriate manner.

[0080] In the embodiments of the present application, words such as "first" and "second" are used to distinguish between identical or similar items with basically the same functions and effects. This is only for the purpose of clearly describing the technical solutions of the embodiments of the present application, and shall not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.

[0081] In this specification, "electrical connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0082] In the related art, refer to Figure 1 When the display device is in full screen display, the display area AA is fully displayed, and the driving circuit scans all sub-pixels line by line; when it is necessary to switch the resolution or display partly, refer to Figure 2 When the local area a1 of the display area AA is displayed, all sub-pixels can only be scanned line by line, and the required resolution display is achieved through signal voltage control.

[0083] For example, refer to Figure 3 When the display device only needs to display time, weather or short messages, the local area a1 of the display area AA is small and still needs to be scanned. Figure 3 The pixel row shown in the figure is in the dark state area a2. In this way, the power consumption for realizing local display is relatively large, which seriously reduces the standby time.

[0084] Based on this, the embodiment of the present application provides a driving circuit, referring to Figure 6 As shown, the driving circuit includes: a plurality of driving units arranged in cascade, the driving units being electrically connected to at least one row of sub-pixels, wherein Figure 4 As shown, the drive unit includes:

[0085] The start row control module 1 is electrically connected to the first signal output terminal OUTN of the driving unit at this level, the start row designation signal line CGI line (Control Gate Initial) and the first node A, and is configured to designate one row of sub-pixels as the switching start row under the control of the start row designation signal CGI signal output by the start row designation signal line CGI line;

[0086] The latch module 2 is electrically connected to the start row specifying signal line CGI line, the reset signal line Reset line, the first level signal line (e.g., the VGH line), the second level signal line (e.g., the VGL line), the first node A and the second node B, respectively, and is configured to latch the start row specifying signal CGI signal;

[0087] The start row trigger module 3 is electrically connected to the second node B, the trigger signal line CGS line (Control Gate Start), the second level signal line (for example, the VGL line) and the third node C, respectively, and is configured to trigger the switching of the start row to start scanning under the control of the trigger signal CGS signal output by the trigger signal line CGS line.

[0088] In the embodiment of the present application, the driving circuit is an integrated gate driver circuit (Gate Driver on Array, GOA). The GOA driving circuit technology is to directly manufacture the gate driving circuit on the array substrate to realize the driving mode of progressive scanning, which is used by various display devices. Since the GOA driving circuit can be directly manufactured on the array substrate, the process of driver IC binding is omitted, the dependence of the array substrate on the more expensive driver IC is reduced, the cost is reduced, and the design requirements of narrow frame and low power consumption of display products can also be realized.

[0089] In some embodiments, the driving circuit includes a CMOS (Metal Oxide Semiconductor) gate circuit, and the CMOS gate circuit includes a P-type MOS transistor and an N-type MOS transistor.

[0090] The driving circuit provided in the embodiment of the present application includes a multi-stage cascaded driving unit, referring to Figure 7 , the driving unit includes a cascaded first-level driving unit GOA1, a second-level driving unit GOA2, ..., an N-1-level driving unit GOAN-1 and an N-level driving unit GOAN. Among them, the first-level driving unit is electrically connected to at least one row of sub-pixels in the display area AA1, the second-level driving unit is electrically connected to at least one row of sub-pixels in the display area AA2, ..., the N-1-level driving unit is electrically connected to at least one row of sub-pixels in the display area AAN-1, and the N-level driving unit is electrically connected to at least one row of sub-pixels in the display area AAN. In some embodiments, the driving unit is electrically connected to 1 row of sub-pixels, and one driving unit drives a pixel driving unit of a row of sub-pixels; in some embodiments, the driving unit is electrically connected to two or more rows of sub-pixels, for example, one driving unit can simultaneously drive a pixel driving unit of two rows of sub-pixels, and for another example, one driving unit can simultaneously drive a pixel driving unit of three rows of sub-pixels. In this specification, the example of a first-level driving unit driving a row of sub-pixels is used for explanation, wherein the first-level driving unit includes two driving units.

[0091] It should be noted that Figure 4 In the example of the Nth level drive unit GOA (N), in the positive scanning mode (combined with Figure 7 The connection mode between the positive scanning signal line STVFL and each level of driving units, at this time, the reverse scanning signal line STVBL is disconnected). Figure 4 The Nth level driving unit GOA(N) and the N+1th level driving unit GOA(N+1) are electrically connected. It can be understood that in the reverse scanning mode (combined with Figure 7 The reverse scanning signal line STVBL is connected to each level of driving unit. At this time, the forward scanning signal line STVFL is disconnected. The Nth level driving unit GOA (N) can be electrically connected to the N-1th level driving unit GOA (N-1).

[0092] In the embodiment of the present application, a driving unit is disposed in the peripheral area on at least one side of the display area AA. In some embodiments, a driving unit can be disposed in the peripheral area BB on one side of the display area AA to achieve a lower cost for driving sub-pixels; in other embodiments, referring to Figure 7 , driving units can be respectively arranged in the peripheral areas BB on the left and right sides of the display area AA, so that two driving units at the same level drive a row of sub-pixels at the same time. For large-size display panels, the uniformity of signal transmission can be improved, the brightness uniformity of the display screen can be improved, and the display performance can be improved; the specific requirements can be determined according to the design requirements of the display product.

[0093] The display color of each sub-pixel in the above-mentioned display area AA is not limited here. In some embodiments, the display colors of each sub-pixel in the display area AA can be the same, for example, all sub-pixels display blue, and for another example, all sub-pixels display white. In some other embodiments, the display area AA may include multiple sub-pixels displaying different colors, for example, the display area AA may include three sub-pixels displaying red, blue and green at the same time; for another example, the display area AA may include four sub-pixels displaying red, blue, green and white at the same time.

[0094] In the exemplary embodiment, the first node A, the second node B and the third node C do not actually exist, but are concepts proposed for the convenience of describing the connection relationship of the circuits in the driving unit, and are hereby explained.

[0095] In an exemplary embodiment, the starting row control module 1 of the driving unit is configured to designate one row of sub-pixels as a switching starting row under the control of the starting row designation signal CGI signal output by the starting row designation signal line CGI line. Exemplarily, the starting row designation signal CGI signal is a high-level signal to control the starting row control module 1 to designate one row of sub-pixels as a switching starting row. The switching starting row can be any row of sub-pixels from the 1st row to the Nth row (the last row) of sub-pixels.

[0096] Taking the example that when the CGI signal is a high level signal, the starting row control module 1 can be controlled to designate one row of sub-pixels as the switching starting row, in some embodiments, when the first output signal OUTN signal outputted from the first output terminal OUTN of the N-level driving unit and the CGI signal are both high level signals, the starting row control module 1 can designate a row of sub-pixels electrically connected to the first output terminal OUTN of the N-level driving unit as the switching starting row. For example, when the OUT3 signal outputted from the first output terminal OUT3 of the third-level driving unit and the CGI signal are both high level signals, the starting row control module 1 can designate a row of sub-pixels electrically connected to the first output terminal OUT3 of the third-level driving unit as the switching starting row; since the first-level driving unit drives a row of sub-pixels, the third row of sub-pixels is the switching starting row at this time.

[0097] In the resolution trigger display frame stage, the CGI signal controls the start line control module 1 to specify the start line. It should be noted that, referring to Figure 8 and Fig. 9 ,in, Figure 8 shows a timing diagram of a conventional line-by-line drive scanning of a driving circuit, Fig. 9 The timing and Figure 8 In the resolution triggering display frame stage, each row of sub-pixels in the display area AA is still in the conventional progressive scanning mode.

[0098] The first signal output terminal OUTN of the N-th level driving unit outputs the first output signal OUTN signal. Exemplarily, when the first output signal OUTN signal is a high level signal, the N-th row of sub-pixels can be charged. In the embodiment of the present application, the first output signal OUTN signal of the driving unit is used as one of the input signals of the starting row control module 1 of the same level driving unit.

[0099] The start row designation signal line CGI outputs a start row designation signal CGI signal, and is configured to control the start row control module 1 to designate one row of sub-pixels as a switching start row.

[0100] The first node A is an output node of the start row control module 1 , and the start row control module 1 inputs a signal to the latch module 2 through the first node A.

[0101] In an exemplary embodiment, the latch module 2 is configured to be able to latch the start row designation signal CGI signal, specifically, the start row designation signal CGI signal is latched in the signal at the second node B position, and for example, the start row designation signal CGI signal is latched in the signal at the second node B position in the form of a high level, and in the absence of a reset signal Reset signal input, the signal at the second node B position maintains a high level.

[0102] The reset signal Reset outputted by the reset signal line Reset can control the driving circuit to reset.

[0103] The first level signal line outputs a first level signal, and the second level signal line outputs a second level signal. Exemplarily, the voltage of the first level signal is greater than the voltage of the second level signal. For example, the first level signal may be a high level signal VGH signal, and the second level signal may be a low level signal VGL signal.

[0104] Among them, the latch module 2 inputs a signal to the start row trigger module 3 through the second node B, and the signal at the second node B is related to the signal at the first node A, the reset signal Reset signal, the first level signal (for example, VGH signal) and the second level signal (for example, VGL signal).

[0105] In an exemplary embodiment, the start line trigger module 3 is configured to be able to trigger the switching of the start line to start scanning under the control of the trigger signal CGS signal. Specifically, after the start line control module 1 specifies the switching of the start line, if the trigger signal CGS signal controls the start line trigger module 3 to trigger the switching of the start line to start scanning, the resolution triggers the resolution switching of the next frame of the display frame; if the trigger signal CGS signal does not control the start line trigger module 3 to trigger the switching of the start line to start scanning, in some embodiments, the next frame of the resolution trigger display frame is still in a conventional progressive scanning state, and the resolution remains unchanged.

[0106] In some embodiments, the trigger signal CGS is a high level signal to control the start line trigger module 3 to trigger the switch start line to start scanning;

[0107] For example, refer to Fig. 9 , in the resolution switching display frame stage, the trigger signal CGS signal is a high level signal to trigger the scanning from the third row of sub-pixels;

[0108] For example, refer to Fig.10 In the resolution switching display frame stage, the trigger signal CGS is set to a high level signal to trigger scanning starting from the 5th row of sub-pixels.

[0109] The third node C is an output node of the start row trigger module 3 , and the signal at the third node C is related to the signal at the second node B, the trigger signal CGS signal and the second level signal (eg VGL signal).

[0110] In an embodiment of the present application, in a resolution triggered display frame, the start row control module 1 is configured to designate one row of sub-pixels as a switching start row under the control of a start row designation signal CGI; the latch module 2 is configured to be able to latch the start row designation signal CGI, and in the resolution switching display frame stage, the latch module 2 locks the switching start row to a row of sub-pixels designated by the start row control module 1; the start row trigger module 3 is configured to be able to trigger the switching start row to start scanning under the control of a trigger signal CGS, and in the resolution switching display frame stage, the start row trigger module 3 triggers the switching start row latched by the latch module 2 to start scanning.

[0111] The embodiment of the present application provides a driving circuit, comprising: a plurality of driving units arranged in cascade, the driving units being electrically connected to at least one row of sub-pixels, the driving units comprising: a starting row control module 1, electrically connected to a first signal output terminal OUTN of the driving unit at the same level, a starting row designation signal line CGI line and a first node A, and configured to be able to designate one row of sub-pixels as a switching starting row under the control of a starting row designation signal CGI signal output by the starting row designation signal line CGI line; a latch module 2, electrically connected to the starting row designation signal line CGI line, a reset signal line Reset line, a first level signal line (for example, a VGH line), and a second level signal line (for example, a VGL line) respectively. , the first node A and the second node B are electrically connected, and are configured to be able to latch the start row designation signal CGI signal; the start row trigger module 3 is electrically connected to the second node B, the trigger signal line CGS line, the second level signal line (for example, the VGL line) and the third node C, and is configured to be able to trigger the switching start row to start scanning under the control of the trigger signal CGS signal output by the trigger signal line CGS line; in this way, when full-screen display is not required or the display device has low power, any row of sub-pixels can be designated as the switching start row, and scanning can be started from the designated switching start row, and the data of some sub-pixels will not be updated, thereby reducing the power consumption of the display and extending the standby time of the display device.

[0112] In some embodiments of the present application, reference Figure 4 , the drive unit also includes:

[0113] The signal input module 4 is electrically connected to the first control signal line CNB line and the second control signal line CN line, respectively, and is configured to input an enable signal to the switching start row under the common control of the signals output by the first control signal line CNB line and the second control signal line CN line, and control the driving circuit to scan starting from the switching start row in the direction of decreasing the number of sub-pixel rows or increasing the number of sub-pixel rows.

[0114] In the embodiment of the present application, the enable signal includes the STV signal and the second output signal Sout of the previous or next stage driving unit.

[0115] For example, when scanning in the direction of increasing the number of sub-pixel rows, the enable signal of the first-level driving unit is the STV signal, and the enable signal of the N-th-level driving unit is the second output signal Sout of the N-1-th-level driving unit; when scanning in the direction of decreasing the number of sub-pixel rows, the enable signal of the last-level driving unit is the STV signal, and the enable signal of the N-th-level driving unit is the second output signal Sout of the N+1-th-level driving unit.

[0116] The first control signal line CNB outputs a first control signal CNB, and the second control signal line CN outputs a second control signal CN.

[0117] In some embodiments, when the first control signal CNB is a high level signal and the second control signal CN is a low level signal, the signal input module 4 controls the driving circuit to scan in the direction of increasing sub-pixel rows starting from the switching start row;

[0118] In some embodiments, when the first control signal CNB is a low level signal and the second control signal CN is a high level signal, the signal input module 4 controls the driving circuit to scan in a direction of decreasing sub-pixel rows starting from the switching start row.

[0119] In an embodiment of the present application, in a resolution triggered display frame, the start row control module 1 specifies one row of sub-pixels as a switching start row; in the resolution switching display frame stage, the latch module 2 locks the switching start row to a row of sub-pixels specified by the start row control module 1; in the resolution switching display frame stage, the start row trigger module 3 triggers the switching start row latched by the latch module 2 to start scanning; after the start row trigger module 3 triggers the switching start row to start scanning, the signal input module 4 can control the drive circuit to scan from the switching start row along the direction of decreasing sub-pixel rows or increasing sub-pixel rows.

[0120] In the embodiment of the present application, the driving unit is arranged to also include a signal input module 4, which is electrically connected to the first control signal line CNB line and the second control signal line CN line, respectively, and is configured to input an enable signal to the switching start row under the common control of the signals output by the first control signal line CNB line and the second control signal line CN line, and control the driving circuit to scan in the direction of decreasing sub-pixel rows or increasing sub-pixel rows starting from the switching start row; in this way, the driving circuit is implemented to scan in the direction of decreasing sub-pixel rows or increasing sub-pixel rows starting from the switching start row.

[0121] In some embodiments of the present application, reference Figure 4 , the drive unit also includes:

[0122] The end row control module 5 is electrically connected to the third node C, the signal input module 4, the end row designation signal line CGE line, the second level signal line (for example, the VGL line) and the fifth node E, respectively, and is configured to designate one of the multiple rows of sub-pixels as the switching end row under the control of the enable signal STV signal output by the signal input module 4, the signal at the third node C position and the end row designation signal CGE signal input by the end designation signal line CGE line.

[0123] It should be noted that the fifth node E does not actually exist, but is a concept proposed for the convenience of describing the connection relationship of the circuits in the driving unit, and is hereby explained.

[0124] In an exemplary embodiment, the end row control module 5 is configured to designate one of the multiple rows of sub-pixels as a switching end row, wherein the switching end row is a sub-pixel row where a frame scan ends in the resolution switching display frame phase. After the end row control module 5 designates the switching end row, the driving circuit scans the sub-pixels row by row from the switching start row to the switching end row in the resolution switching display frame phase.

[0125] Among them, multiple rows of sub-pixels that can be designated as the switching end row need to meet certain conditions. Specifically, when scanning in the direction of increasing sub-pixel rows, the number of sub-pixel rows in the switching end row is greater than or equal to the number of sub-pixel rows in the switching start row; when scanning in the direction of decreasing sub-pixel rows, the number of sub-pixel rows in the switching end row is less than or equal to the number of sub-pixel rows in the switching start row.

[0126] The end row designation signal CGE signal inputted by the end designation signal line CGE line includes a high level signal. Exemplarily, the end row designation signal CGE signal can be used as a high level signal to designate one of the multiple rows of sub-pixels as a switching end row;

[0127] For example, refer to Fig. 9, the end row designation signal CGE is set as a high level signal to designate the sub-pixels in the 6th row as the switching end row;

[0128] For example, refer to Fig.10 , the end row designation signal CGE is set as a high level signal to designate the 10th row of sub-pixels as the switching end row.

[0129] The fifth node E is the output node of the end row control module 5 , and the signal at the fifth node E is related to the signal at the third node C, the end row designation signal CGE signal, the second level signal (eg VGL signal) and the signal input by the signal input module 4 .

[0130] In an embodiment of the present application, in a resolution-triggered display frame, the start row control module 1 specifies one row of sub-pixels as a switching start row; in the resolution-switching display frame stage, the latch module 2 locks the switching start row as a row of sub-pixels specified by the start row control module 1; in the resolution-switching display frame stage, the start row trigger module 3 triggers the switching start row latched by the latch module 2 to start scanning; after the start row trigger module 3 triggers the switching start row to start scanning, the signal input module 4 can control the drive circuit to scan from the switching start row in the direction of decreasing sub-pixel rows or in the direction of increasing sub-pixel rows; in the process of the signal input module 4 controlling the drive circuit to scan in the direction of decreasing sub-pixel rows or in the direction of increasing sub-pixel rows, the end row control module 5 specifies one of the multiple rows of sub-pixels as a switching end row, and in one of the frames in the resolution-switching display frame stage, the drive circuit stops scanning after scanning the switching end row.

[0131] In the embodiment of the present application, the driving unit is set to also include an end row control module 5, which is electrically connected to the third node C, the signal input module 4, the end row designation signal line CGE line, the second level signal line (for example, the VGL line) and the fifth node E, respectively, and is configured to designate one of the multiple rows of sub-pixels as the switching end row under the control of the enable signal STV signal output by the signal input module 4, the signal at the position of the third node C, and the end row designation signal CGE signal input by the end designation signal line CGE line; in this way, any row of sub-pixels can be designated as the switching start row through the start row control module 1, and the end row control module 5 designates one of the multiple rows of sub-pixels as the switching end row, so that the driving circuit starts scanning from the switching start row and stops scanning from the switching end row, and the data of some sub-pixels will not be updated, thereby reducing the power consumption of the display and extending the standby time of the display device.

[0132] In some embodiments of the present application, reference Figure 4 , the drive unit also includes:

[0133] The shift register module 6 is electrically connected to the fifth node E, the first clock signal line, the second clock signal line, the reset signal line Reset line, the second level signal line (for example, the VGL line), and the first signal output terminal OUTN and the second signal output terminal Sout of the driving unit, respectively, and is configured to realize row-by-row scanning between the switching start row and the switching end row under the joint control of the signal at the position of the fifth node E, the first clock signal input by the first clock signal line, and the second clock signal input by the second clock signal line.

[0134] The shift register module 6 is configured to implement row-by-row scanning between the switching start row and the switching end row. For example, the second output signal Sout signal output from the second signal output terminal Sout can be used to control whether the next row of sub-pixels is to be scanned. Taking scanning in the direction of increasing number of sub-pixel rows as an example, when the number of sub-pixel rows is greater than or equal to the number of switching start rows and the number of sub-pixel rows is less than the number of switching receiving rows, the driving unit electrically connected to the sub-pixels controls the next-level driving unit to scan the sub-pixel rows through the second output signal Sout signal.

[0135] In some embodiments, the first clock signal line is a CKB line, the first clock signal is a CKB signal, the second clock signal line is a CK line, and the second clock signal is a CK signal; in some embodiments, the first clock signal line is a CK line, the first clock signal is a CK signal, the second clock signal line is a CKB line, and the second clock signal is a CKB signal.

[0136] It should be noted that the pulse widths of the first clock signal and the second clock signal are the same, and when the first clock signal is a high-level signal, the second clock signal is a low-level signal; when the first clock signal is a low-level signal, the second clock signal is a high-level signal.

[0137] In the embodiment of the present application, the first output signal OUTN of the N-th stage driving unit is transmitted to the pixel driving circuit in the N-th stage display area AA.

[0138] Since multiple drive units are cascaded, in the embodiment of the present application:

[0139] In the case of scanning in the direction of increasing number of sub-pixel rows, the second output signal Sout of the Nth stage driving unit can be used as the input signal of the N+1th driving unit. It can be understood that the second signal output terminal Sout of the Nth stage driving unit can be electrically connected to the signal input module 4 of the N+1 driving unit.

[0140] When scanning in the direction of decreasing sub-pixel rows, the second output signal Sout of the Nth level driving unit can be used as the input signal of the N-1th driving unit. It can be understood that the second signal output terminal Sout of the Nth level driving unit can be electrically connected to the signal input module 4 of the N-1 driving unit.

[0141] In an embodiment of the present application, in a resolution-triggered display frame, the start row control module 1 specifies one row of sub-pixels as a switching start row; in the resolution-switching display frame stage, the latch module 2 locks the switching start row as a row of sub-pixels specified by the start row control module 1; in the resolution-switching display frame stage, the start row trigger module 3 triggers the switching start row latched by the latch module 2 to start scanning; after the start row trigger module 3 triggers the switching start row to start scanning, the signal input module 4 can control the drive circuit to scan from the switching start row, along the direction of decreasing sub-pixel rows or increasing sub-pixel rows; in the resolution-switching display frame stage, the end row control module 5 specifies one of the multiple rows of sub-pixels as a switching end row; in the resolution-switching display frame stage, the shift register module 6 implements row-by-row scanning from the switching start row specified by the start row control module 1 to the switching end row specified by the end row control module 5.

[0142] In some embodiments of the present application, the driving unit is set to also include a shift register module 6, which is respectively electrically connected to the fifth node E, the first clock signal line, the second clock signal line, the reset signal line Reset line, the second level signal line (for example, the VGL line) and the first signal output terminal OUTN and the second signal output terminal Sout of the driving unit, and is configured to realize line-by-line scanning between the switching start row and the switching end row under the common control of the signal at the position of the fifth node E, the first clock signal input by the first clock signal line and the second clock signal input by the second clock signal line; in this way, the driving circuit can realize line-by-line scanning between the switching start row and the switching end row, and realize display in a part of the display area AA.

[0143] In some embodiments of the present application, reference Figure 4 The signal input module 4 includes a forward scan input submodule 41 and a reverse scan input submodule 42; the forward scan input submodule 41 and the reverse scan input submodule 42 are connected together and electrically connected to the end line control module 5;

[0144] The positive scan input submodule 41 is electrically connected to the positive scan signal line STVF line, the first control signal line CNB line and the second control signal line CN line respectively, and is configured to output the positive scan signal STVF signal transmitted by the positive scan signal line STVF line under the common control of the first control signal CNB signal input by the first control signal line CNB line and the second control signal CN signal input by the second control signal line CN line;

[0145] The reverse scan input submodule 42 is electrically connected to the reverse scan signal line STVB, the first control signal line CNB and the second control signal line CN respectively, and is configured to output the reverse scan signal STVB transmitted by the reverse scan signal line STVB under the common control of the first control signal CNB input by the first control signal line CNB and the second control signal CN input by the second control signal line CN;

[0146] Among them, the end row control module 5 is configured to be able to receive a forward scanning signal STVF signal or a reverse scanning signal STVB signal. The forward scanning signal STVF signal is configured to be able to control the driving circuit to scan in the direction of increasing sub-pixel rows starting from the switching start row, and the reverse scanning signal STVB signal is configured to be able to control the driving circuit to scan in the direction of decreasing sub-pixel rows starting from the switching start row.

[0147] In an embodiment of the present application, the forward scan input submodule 41 and the reverse scan input submodule 42 are connected together, wherein the connection is different from the electrical connection, the forward scan input submodule 41 and the reverse scan input submodule 42 do not constitute a path, the output signal of the forward scan input submodule 41 will not be transmitted to the reverse scan input submodule 42, and the output signal of the reverse scan input submodule 42 will not be transmitted to the forward scan input submodule 41, and one of the forward scan input submodule 41 and the reverse scan input submodule 42 forms a path with the end row control module 5.

[0148] In some embodiments, when the first control signal CNB is a high-level signal and the second control signal CN is a low-level signal, the forward scan input submodule 41 and the end row control module 5 form a path, and the forward scan input submodule 41 inputs the forward scan signal STVF signal to the end row control module 5; in some embodiments, when the first control signal CNB is a low-level signal and the second control signal CN is a high-level signal, the reverse scan input submodule 42 and the end row control module 5 form a path, and the reverse scan input submodule 42 inputs the reverse scan signal STVF signal to the end row control module 5.

[0149] Among them, the forward scanning signal STVF signal controls the driving circuit to scan from the switching starting line along the direction of increasing sub-pixel rows, which is called the forward scanning mode; the reverse scanning signal STVB controls the driving circuit to scan from the switching starting line along the direction of decreasing sub-pixel rows, which is called the reverse scanning mode.

[0150] In the embodiment of the present application, in the forward scanning mode, the second signal output terminal Sout of the Nth level driving unit is electrically connected to the forward scanning signal line STVF of the N+1th level driving unit; in the reverse scanning mode, the second signal output terminal Sout of the Nth level driving unit is electrically connected to the reverse scanning signal line STVB of the N-1th level driving unit. In an exemplary embodiment, the forward scanning input submodule 41 can control the display panel to scan in the direction of increasing sub-pixel rows, such as scanning row by row from top to bottom; when the display panel has a rotation function and is displayed after rotating about 180°, the reverse scanning input submodule 42 can control the display panel to scan in the direction of decreasing sub-pixel rows, such as scanning row by row from top to bottom, which broadens the application scenarios of the display panel, for example, it can be applied to commercial display products or billboards with a rotation function.

[0151] In the embodiment of the present application, in the resolution trigger display frame, the start row control module 1 specifies one row of sub-pixels as the switching start row; in the resolution switching display frame stage, the latch module 2 locks the switching start row as a row of sub-pixels specified by the start row control module 1; in the resolution switching display frame stage, the start row trigger module 3 triggers the switching start row latched by the latch module 2 to start scanning;

[0152] After the start line trigger module 3 triggers the switching start line to start scanning, the forward scanning input submodule 41 inputs the forward scanning signal STVF signal to the end line control module 5 to control the driving circuit to start from the switching start line and scan in the direction of increasing sub-pixel rows, or the reverse scanning input submodule 42 inputs the reverse scanning signal STVB signal to the end line control module 5 to control the driving circuit to start from the switching start line and scan in the direction of increasing sub-pixel rows;

[0153] In the resolution switching display frame stage, the end row control module 5 specifies one of the multiple rows of sub-pixels as the switching end row; in the resolution switching display frame stage, the shift register module 6 implements row-by-row scanning from the switching start row specified by the start row control module 1 to the switching end row specified by the end row control module 5.

[0154] In the embodiment of the present application, the signal input module 4 is provided to include a forward scan input submodule 41 and a reverse scan input submodule 42; the forward scan input submodule 41 and the reverse scan input submodule 42 are connected together and electrically connected to the end row control module 5; the forward scan input submodule 41 is configured to output the forward scan signal STVF signal transmitted by the forward scan signal line STVF line; the reverse scan input submodule 42 is configured to output the reverse scan signal STVB signal transmitted by the reverse scan signal line STVB line; the forward scan signal STVF is configured to be able to control the driving circuit to scan in the direction of increasing sub-pixel rows starting from the switching start row, and the reverse scan signal STVB is configured to be able to control the driving circuit to scan in the direction of decreasing sub-pixel rows starting from the switching start row; in this way, the driving circuit can realize forward scan or reverse scan from the switching start row to the switching end row.

[0155] In some embodiments of the present application, reference Figure 4 , the starting row control module 1 includes a first NAND gate circuit NAND1 and a first inverter NOT1;

[0156] The first signal output terminal OUTN of the driving unit at this level and the starting row designated signal line CGI are electrically connected to the two input terminals of the first NAND gate sub-circuit NAND1 respectively, the input terminal of the first inverter NOT1 is electrically connected to the output terminal of the first NAND gate sub-circuit NAND1, and the output terminal of the first inverter NOT1 is electrically connected to the first node A.

[0157] The NAND gate circuit NAND includes two input terminals and an output terminal. When the signals input to the two input terminals are both high-level signals, the output terminal outputs a low-level signal. When the signal input to at least one input terminal is a low-level signal, the output terminal outputs a high-level signal.

[0158] Taking the high level signal as 1 and the low level signal as 0 as an example, the truth table of the NAND gate circuit is shown in Table 1:

[0159] Table 1: Truth table of NAND gate circuit

[0160] First input signal Second input signal Output signal 1 1 0 1 0 1 0 1 1 0 0 1

[0161] In the present application, refer to Figure 5 and Figure 6 , the first NAND gate sub-circuit NAND1 includes a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11 and a twelfth transistor T12.

[0162] It should be noted that Figure 5 and Figure 6 Different marks are made for the same figure. Since there are many marks in the figure, in order to avoid unclearness caused by overlapping marks, Figure 5The transistors are marked in Figure 6 The components are marked in .

[0163] The transistor includes an N-type transistor and a P-type transistor. When the gate signal is a high-level signal, the N-type transistor is turned on; when the gate signal is a high-level signal, the N-type transistor is turned off. When the gate signal is a high-level signal, the P-type transistor is turned off; when the gate signal is a high-level signal, the P-type transistor is turned on.

[0164] In the embodiment of the present application, the transistor includes a MOS tube (Metal Oxide Semiconductor, Metal Oxide Semiconductor Field Effect Transistor).

[0165] Among them, the ninth transistor T9 is an N-type MOS transistor, the tenth transistor T10 is an N-type MOS transistor, the eleventh transistor T11 is a P-type MOS transistor, and the twelfth transistor T12 is a P-type MOS transistor;

[0166] The gate of the ninth transistor T9 is electrically connected to the start row designation line CGI line, the drain of the ninth transistor T9 is electrically connected to the second level signal line VGL line, and the source of the ninth transistor T9 is electrically connected to the drain of the tenth transistor T10;

[0167] The gate of the tenth transistor T10 is electrically connected to the first signal output terminal OUTN of the driving unit at this stage, and the source of the tenth transistor T10, the drain of the eleventh transistor T10, the source of the twelfth transistor T12 and the input terminal of the first inverter NOT1 are electrically connected together;

[0168] The gate of the eleventh transistor T11 is electrically connected to the first signal output terminal OUTN of the driving unit at the same stage, and the source of the eleventh transistor T11, the drain of the twelfth transistor T12 and the first level signal line VGH are electrically connected together;

[0169] A gate of the twelfth transistor T12 is electrically connected to the start row designation line CGI line.

[0170] The inverter NOT includes an input terminal and an output terminal. When the signal input to the input terminal is a high-level signal, the inverter outputs a low-level signal; when the signal input to the input terminal is a low-level signal, the inverter outputs a high-level signal.

[0171] The inverters appearing in this specification are NOT referred to here and will not be described in detail.

[0172] In the present application, refer to Figure 5 and Figure 6 , the first inverter NOT1 includes a thirteenth transistor T13 and a fourteenth transistor T14.

[0173] Wherein, the thirteenth transistor T13 is a P-type transistor, and the fourteenth transistor T14 is an N-type transistor;

[0174] The gate of the thirteenth transistor T13, the gate of the fourteenth transistor T14 and the output end of the first NAND gate sub-circuit NAND1 are electrically connected together;

[0175] The source of the thirteenth transistor T13 is electrically connected to the first level signal line VGH, and the drain of the fourteenth transistor T14 is electrically connected to the second level signal line VGL;

[0176] The drain of the thirteenth transistor T13, the source of the fourteenth transistor T14, and the first node A are electrically connected together.

[0177] In the embodiment of the present application, the start row control module 1 includes a P-type MOS tube and an N-type MOS tube. The start row control module 1 outputs both positive voltage and negative voltage without loss. The charging rate is fast and the efficiency is the same when the positive voltage and negative voltage are output, which can enhance the driving force of the driving circuit and thereby improve the display stability of the display device.

[0178] In some embodiments of the present application, reference Figure 4 , the latch module 2 includes a first transistor T1, a first NOR gate circuit NOR1, a second transistor T2, a third transistor T3 and a fourth transistor T4;

[0179] The gate of the first transistor T1 is electrically connected to the reset signal line Reset, the source of the first transistor T1 is electrically connected to the start row designation signal line CGI, and the drain of the first transistor T1 is electrically connected to an input end of the first NOR gate sub-circuit NOR1 and the second node B respectively;

[0180] Two input terminals of the first NOR gate sub-circuit NOR1 are electrically connected to the first node A and the second node B respectively, and the output terminal of the first NOR gate sub-circuit NOR1 is electrically connected to the gate of the third transistor T3 and the gate of the fourth transistor T3 respectively;

[0181] The gate of the second transistor T2 is electrically connected to the reset signal line Reset, the source of the second transistor T2 is electrically connected to the first level signal line VGH, and the drain of the second transistor T2 is electrically connected to the source of the third transistor T3;

[0182] The drain of the third transistor T3, the source of the fourth transistor T4, and the second node B are electrically connected together, and the drain of the fourth transistor T4 is electrically connected to the second level signal line VGL line.

[0183] The NOR gate circuit NOR outputs a high level signal when both input signals are low level signals; and outputs a low level signal when at least one of the input signals is a high level signal.

[0184] Taking the high level signal as 1 and the low level signal as 0 as an example, the truth table of the NOR gate circuit is shown in Table 2:

[0185] Table 2: Truth table of NOR gate circuit

[0186] First input signal Second input signal Output signal 1 1 0 1 0 0 0 1 0 0 0 1

[0187] The NOR gate circuit NOR that appears in this specification refers to the description here and will not be repeated here.

[0188] In the present application, refer to Figure 5 and Figure 6 , the first NOR gate sub-circuit NOR1 includes a fifteenth transistor T15, a sixteenth transistor T16, a seventeenth transistor T17 and an eighteenth transistor T18.

[0189] Among them, the fifteenth transistor T15 is a P-type MOS transistor, the sixteenth transistor T16 is a P-type MOS transistor, the seventeenth transistor T17 is an N-type MOS transistor, and the eighteenth transistor T18 is an N-type MOS transistor;

[0190] The gate of the fifteenth transistor T15 is electrically connected to the first node A, the drain of the fifteenth transistor T15 is electrically connected to the first level signal line VGH line, and the source of the fifteenth transistor T15 is electrically connected to the drain of the sixteenth transistor T16;

[0191] The gate of the sixteenth transistor T16 is electrically connected to the drain of the first transistor T1, and the source of the sixteenth transistor T16, the drain of the seventeenth transistor T17, the source of the eighteenth transistor T18 and the input terminal of the second inverter NOT2 are electrically connected together;

[0192] The gate of the seventeenth transistor T17 is electrically connected to the drain of the first transistor T1, and the source of the seventeenth transistor T17, the drain of the eighteenth transistor T18 and the second level signal line VGL are electrically connected together;

[0193] The gate of the eighteenth transistor T18 is electrically connected to the first node A.

[0194] In the present application, for example, refer to Figure 4 The first transistor T1 is an N-type MOS tube, the second transistor T1 is a P-type MOS tube, the third transistor T1 is a P-type MOS tube, and the fourth transistor T1 is an N-type MOS tube.

[0195] In the embodiment of the present application, the latch module 2 includes a first transistor T1, a first NOR gate circuit NOR1, a second transistor T2, a third transistor T3 and a fourth transistor T4; the latch module 2 includes a P-type MOS tube and an N-type MOS tube, and the latch module 2 outputs both positive voltage and negative voltage without loss. The charging rate is fast and the efficiency is the same when the positive voltage and the negative voltage are output, which can enhance the driving force of the driving circuit, thereby improving the display stability of the display device.

[0196] In some embodiments of the present application, the start row trigger module 3 includes a second inverter NOT2, a first transmission gate TG1 and a fifth transistor T5;

[0197] An input terminal of the second inverter NOT2 is electrically connected to the second node B, and an output terminal of the second inverter NOT2 is electrically connected to the gate of the fifth transistor T5 and the first control terminal of the first transmission gate TG1 respectively;

[0198] The second control terminal of the first transmission gate TG1 is electrically connected to the second node B, the input terminal of the first transmission gate TG1 is electrically connected to the trigger signal line CGS line, and the output terminal of the first transmission gate TG1 is electrically connected to the third node C;

[0199] A source of the fifth transistor T5 is electrically connected to the second level signal line VGL line, and a drain of the fifth transistor is electrically connected to the third node C.

[0200] It should be noted that in this manual, Figure 4 The end marked with a circle on the transmission gate symbol is the first control end of the transmission gate.

[0201] The transmission gate TG includes a first control terminal, a second control terminal, an input terminal and an output terminal.

[0202] When the first control terminal is a low level signal and the second control terminal is a high level signal, the transmission gate TG is opened. If a high level signal is input to the input terminal, the output terminal outputs a high level signal; if a low level signal is input to the input terminal, the output terminal outputs a high level signal.

[0203] When the first control terminal is a high level signal and the second control terminal is a low level signal, the transmission gate TG is closed, and the output terminal of the transmission gate TG does not output a signal.

[0204] The transmission gate TG appearing in this specification refers to the description here and will not be described in detail again.

[0205] In the present application, refer to Figure 5 and Figure 6 , the first transmission gate TG1 includes a nineteenth transistor T19 and a twentieth transistor T20.

[0206] The nineteenth transistor T19 is a P-type MOS transistor, and the twentieth transistor T20 is an N-type MOS transistor;

[0207] The gate of the nineteenth transistor T19 is electrically connected to the second node B, the source of the nineteenth transistor, the third node C and the source of the twentieth transistor T20 are electrically connected, and the drain of the nineteenth transistor, the trigger signal line CGS line and the drain of the twentieth transistor T20 are electrically connected;

[0208] A gate of the twentieth transistor T20 is electrically connected to the output terminal of the second inverter NOT2.

[0209] In the present application, refer to Figure 5 and Figure 6 , the second inverter NOT2 includes a twenty-first transistor T21 and a twenty-second transistor T22.

[0210] Wherein, the twenty-first transistor T21 is an N-type MOS transistor, and the twenty-second transistor T22 is a P-type MOS transistor;

[0211] A gate of the twenty-first transistor T21, a gate of the twenty-second transistor T22 and a second node B are electrically connected together;

[0212] The drain of the twenty-first transistor T21 is electrically connected to the second level signal line VGL, and the source of the twenty-second transistor T22 is electrically connected to the first level signal line VGH;

[0213] The source of the twenty-first transistor T21, the drain of the twenty-second transistor T22, and the gate of the fifth transistor T5 are electrically connected together.

[0214] In the present application, for example, refer to Figure 4 , the fifth transistor T5 is an N-type MOS tube.

[0215] In the embodiment of the present application, the start row trigger module 3 includes a second inverter NOT2, a first transmission gate TG1 and a fifth transistor T5; the start row trigger module 3 includes a P-type MOS tube and an N-type MOS tube, and the start row trigger module 3 outputs both positive voltage and negative voltage without loss. The charging rate is fast and the efficiency is the same when the positive voltage and the negative voltage are output, which can enhance the driving force of the driving circuit, thereby improving the display stability of the display device.

[0216] In some embodiments of the present application, the forward scan input submodule 41 includes a second transmission gate TG2, and the reverse scan input submodule 42 includes a third transmission gate TG3;

[0217] The first control end of the second transmission gate TG2 is electrically connected to the first control signal line CNB, the second control end of the second transmission gate is electrically connected to the second control signal line CN, the input end of the second transmission gate TG2 is electrically connected to the positive scan signal line STVF, and the output end of the second transmission gate TG2 is connected to the end line control module 5;

[0218] The first control end of the third transmission gate TG3 is electrically connected to the second control signal line CN, the second control end of the third transmission gate TG3 is electrically connected to the first control signal line CNB, the input end of the third transmission gate TG3 is electrically connected to the reverse scan signal line STVF, and the output end of the third transmission gate TG3 is connected to the end row control module 5;

[0219] An output terminal of the second transmission gate TG2 is connected to an output terminal of the third transmission gate TG3 .

[0220] In the embodiment of the present application, the output end of the second transmission gate TG2 is connected to the output end of the third transmission gate TG3, wherein the connection is different from the electrical connection, and the output end of the second transmission gate TG2 and the output end of the third transmission gate TG3 do not form a path.

[0221] In the present application, refer to Figure 5 and Figure 6 , the third transmission gate TG3 includes a twenty-third transistor T23 and a twenty-fourth transistor T24;

[0222] Wherein, the twenty-third transistor T23 is an N-type MOS transistor, and the twenty-fourth transistor T24 is a P-type MOS transistor;

[0223] The gate of the twenty-third transistor T23 is electrically connected to the first control signal line CNB, the source of the twenty-third transistor T23 is electrically connected to the source of the twenty-fourth transistor T24, and the drain of the twenty-third transistor T23, the reverse scan signal line STVB and the drain of the twenty-fourth transistor T24 are electrically connected;

[0224] A gate of the twenty-fourth transistor T24 is electrically connected to the second control signal line CN.

[0225] In the present application, refer to Figure 5 and Figure 6 , the second transmission gate TG2 includes a twenty-fifth transistor T25 and a twenty-sixth transistor T26;

[0226] Wherein, the twenty-fifth transistor T25 is a P-type MOS transistor, and the twenty-sixth transistor T26 is an N-type MOS transistor;

[0227] The gate of the twenty-fifth transistor T25 is electrically connected to the first control signal line CNB, the source of the twenty-fifth transistor T25 is electrically connected to the source of the twenty-sixth transistor T26, and the drain of the twenty-fifth transistor T25, the positive scan signal line STVF and the drain of the twenty-sixth transistor T26 are electrically connected;

[0228] The gate of the twenty-sixth transistor T26 is electrically connected to the second control signal line CN. In some embodiments of the present application, the forward scan input submodule 41 includes a second transmission gate TG2, and the reverse scan input submodule 42 includes a third transmission gate TG3; the forward scan input submodule 41 and the reverse scan input submodule 42 include a P-type MOS tube and an N-type MOS tube, and the forward scan input submodule 41 or the reverse scan input submodule 42 outputs positive voltage and negative voltage without loss, and the charging rate is fast and the efficiency is the same when the positive voltage and the negative voltage are output, which can enhance the driving force of the driving circuit, thereby improving the display stability of the display device.

[0229] In some embodiments of the present application, reference Figure 4 , the end row control module 5 includes a third inverter NOT3, a fourth transmission gate TG4, a sixth transistor T6, a second NOR gate sub-circuit NOR2 and a fourth inverter NOT4;

[0230] The input end of the third inverter NOT3 is electrically connected to the end row designation signal line CGE line and the gate of the sixth transistor T6, and the output end of the third inverter NOT3 is electrically connected to the second control end of the fourth transmission gate TG4;

[0231] The first control end of the fourth transmission gate TG4 is electrically connected to the input end of the third inverter NOT3, the input end of the fourth transmission gate TG4 is electrically connected to the signal input module 4, and the output end of the fourth transmission gate TG4 is electrically connected to the fourth node D;

[0232] A source of the sixth transistor T6 is electrically connected to the second level signal line VGL, and a drain of the sixth transistor T6 is electrically connected to the fourth node;

[0233] The two input terminals of the second NOR gate sub-circuit NOR2 are electrically connected to the third node C and the fourth node D respectively, the output terminal of the second NOR gate sub-circuit NOR2 is electrically connected to the input terminal of the fourth inverter NOT4, and the output terminal of the fourth inverter NOT4 is electrically connected to the fifth node E.

[0234] In the present application, refer to Figure 5 and Figure 6 The third inverter NOT3 includes a twenty-seventh transistor T27 and a twenty-eighth transistor T28.

[0235] Wherein, the twenty-seventh transistor T27 is an N-type MOS transistor, and the twenty-eighth transistor T28 is a P-type MOS transistor;

[0236] The gate of the twenty-seventh transistor T27, the gate of the twenty-eighth transistor T28 and the end row designation signal line CGE line are electrically connected together;

[0237] The drain of the twenty-seventh transistor T27 is electrically connected to the second level signal line VGL, and the source of the twenty-eighth transistor T28 is electrically connected to the first level signal line VGH;

[0238] The source of the twenty-seventh transistor T27, the drain of the twenty-eighth transistor T28 and the second control terminal of the fourth transmission gate TG4 are electrically connected together.

[0239] In the present application, refer to Figure 5 and Figure 6 , the fourth transmission gate TG4 includes a twenty-ninth transistor T29 and a thirtieth transistor T30.

[0240]

[0241] It is an N-type MOS tube;

[0242] The gate of the twenty-ninth transistor T29 is electrically connected to the output end of the third inverter NOT3, the source of the twenty-ninth transistor T29, the source of the thirtieth transistor T30 and the fourth node D are electrically connected, and the drain of the twenty-ninth transistor T29, the signal input module 4 and the drain of the thirtieth transistor T30 are electrically connected;

[0243] The gate of the thirtieth transistor T30 is electrically connected to the end row designation signal line CGE. Figure 5 and Figure 6 The second NOR gate sub-circuit NOR2 includes a thirty-first transistor T31, a thirty-second transistor T32, a thirty-third transistor T33 and a thirty-fourth transistor T34.

[0244] Among them, the thirty-first transistor T31 is a P-type MOS transistor, the thirty-second transistor T32 is a P-type MOS transistor, the thirty-third transistor T33 is an N-type MOS transistor, and the thirty-fourth transistor T34 is an N-type MOS transistor;

[0245] The gate of the thirty-first transistor T31 is electrically connected to the third node C, the drain of the thirty-first transistor T31 is electrically connected to the first level signal line VGH line, and the source of the thirty-first transistor T31 is electrically connected to the drain of the thirty-second transistor T32;

[0246] The gate of the 32nd transistor T32 is electrically connected to the fourth node D, and the source of the 32nd transistor T32, the drain of the 33rd transistor T33, the source of the 34th transistor T34 and the input terminal of the fourth inverter NOT4 are electrically connected together;

[0247] The gate of the thirty-third transistor T33 is electrically connected to the fourth node D, and the source of the thirty-third transistor T33, the drain of the thirty-fourth transistor T34 and the second level signal line VGL are electrically connected together;

[0248] The gate of the thirty-fourth transistor T34 is electrically connected to the third node C.

[0249] In the present application, refer to Figure 5 and Figure 6 , the fourth inverter NOT4 includes a thirty-fifth transistor T35 and a thirty-sixth transistor T36.

[0250] Among them, the thirty-fifth transistor T35 is an N-type MOS transistor, and the thirty-sixth transistor T36 is a P-type MOS transistor;

[0251] The gate of the thirty-fifth transistor T35, the gate of the thirty-sixth transistor T36 and the second NOR gate sub-circuit NOR2 are electrically connected together;

[0252] The drain of the thirty-fifth transistor T35 is electrically connected to the second level signal line VGL, and the source of the twenty-eighth transistor T28 is electrically connected to the first level signal line VGH.

[0253] The source of the thirty-fifth transistor T35, the drain of the thirty-sixth transistor T36, and the fifth node E are electrically connected together.

[0254] In the present application, for example, refer to Figure 4 , the fifth transistor T6 is an N-type MOS tube. In the embodiment of the present application, the end row control module 5 includes a third inverter NOT3, a fourth transmission gate TG4, a sixth transistor T6, a second NOR gate sub-circuit NOR2 and a fourth inverter NOT4; the end row control module 5 includes a P-type MOS tube and an N-type MOS tube, and the end row control module 5 outputs both positive and negative voltages without loss. When the positive and negative voltages are output, the charging rate is fast and the efficiency is the same, which can enhance the driving force of the driving circuit, thereby improving the display stability of the display device.

[0255] In some embodiments of the present application, reference Figure 4 , the shift register module 6 includes a fifth inverter NOT5, a first tri-state inverter Tri-Inv1, a second tri-state inverter Tri-Inv2, a fifth transmission gate TG5, a sixth inverter NOT6, a seventh transistor T7 and an eighth transistor T8;

[0256] An input end of the fifth inverter NOT5 is electrically connected to the first clock signal line, and an output end of the fifth inverter NOT5 is electrically connected to a first control end of the first tri-state inverter Tri-Inv1 and a second control end of the second tri-state inverter Tri-Inv2 respectively;

[0257] The second control terminal of the first tri-state inverter Tri-Inv1 is electrically connected to the first clock signal line, the input terminal of the first tri-state inverter Tri-Inv1 is electrically connected to the fifth node E, and the output terminal of the first tri-state inverter Tri-Inv1 is electrically connected to the gate of the seventh transistor T7 and the input terminal of the sixth inverter NOT6 respectively;

[0258] The first control terminal of the second tri-state inverter Tri-Inv2 is electrically connected to the first clock signal line, the input terminal of the second tri-state inverter Tri-Inv2 is electrically connected to the sixth node F, and the output terminal of the second tri-state inverter Tri-Inv2 is electrically connected to the gate of the seventh transistor T7 and the input terminal of the sixth inverter NOT6 respectively;

[0259] The output end of the sixth inverter NOT6 is electrically connected to the sixth node F and the second signal output end Sout of the driving unit at this stage respectively;

[0260] The first control end of the fifth transmission gate TG5 is electrically connected to the output end of the first tri-state inverter Tri-Inv1 and the output end of the second tri-state inverter Tri-Inv1 respectively, the second control end of the fifth transmission gate TG5 is electrically connected to the output end of the sixth inverter NOT6, the input end of the fifth transmission gate TG5 is electrically connected to the second clock signal line, and the output end of the fifth transmission gate TG5 is electrically connected to the first signal output end OUTN of the driving unit at this stage;

[0261] The source of the seventh transistor T7 is electrically connected to the second level signal line VGL line, and the drain of the seventh transistor T7 is electrically connected to the first signal output terminal OUTN of the driving unit at this stage; the gate of the eighth transistor T8 is electrically connected to the reset signal line Reset line, the source of the eighth transistor T8 is electrically connected to the sixth node F, and the drain of the eighth transistor T8 is electrically connected to the second level signal line VGL line.

[0262] It should be noted that in this manual, Figure 4 The end marked with a circle on the three-state inverter symbol is the first control end of the three-state inverter.

[0263] The tri-state inverter Tri-Inv comprises a first control terminal, a second control terminal, an input terminal and an output terminal;

[0264] When the first control terminal is a low level signal and the second control terminal is a high level signal, if the input terminal of the tri-state inverter Tri-Inv inputs a high level signal, the output terminal outputs a low level signal; if the input terminal of the tri-state inverter Tri-Inv inputs a low level signal, the output terminal outputs a high level signal;

[0265] When at least one of the first control terminal is a high level signal or the second control terminal is a low level signal, the tri-state inverter Tri-Inv is turned off.

[0266] In the embodiment of the present application, the first tri-state inverter Tri-Inv1 includes a thirty-ninth transistor T39 , a fortieth transistor T40 , a forty-first transistor T41 , and a forty-second transistor T42 .

[0267] Among them, the 39th transistor T39 is a P-type MOS transistor, the 40th transistor T40 is a P-type MOS transistor, the 41st transistor T41 is an N-type MOS transistor, and the 42nd transistor T42 is an N-type MOS transistor;

[0268] The gate of the thirty-ninth transistor T39 is electrically connected to the output terminal of the fifth inverter NOT5, the source of the thirty-ninth transistor T39 is electrically connected to the first level signal line VGH line, and the drain of the thirty-ninth transistor T39 is electrically connected to the source of the fortieth transistor T40;

[0269] The gate of the 40th transistor T40, the gate of the 41st transistor T41 and the fifth node E are electrically connected together;

[0270] The drain of the 40th transistor T40, the source of the 41st transistor T41 and the input terminal of the sixth inverter NOT6 are electrically connected together;

[0271] The drain of the forty-first transistor T41 is electrically connected to the source of the forty-second transistor T42;

[0272] A gate of the forty-second transistor T42 is electrically connected to the first clock signal line, and a drain of the forty-second transistor T42 is electrically connected to the second level signal line VGL line.

[0273] In the embodiment of the present application, the second three-state inverter Tri-Inv2 includes a forty-third transistor T43, a forty-fourth transistor T44, a forty-fifth transistor T45 and a forty-sixth transistor T46.

[0274] Among them, the forty-third transistor T43 is an N-type MOS transistor, the forty-fourth transistor T44 is an N-type MOS transistor, the forty-fifth transistor T45 is a P-type MOS transistor, and the forty-sixth transistor T46 is a P-type MOS transistor;

[0275] The gate of the forty-third transistor T43 is electrically connected to the output terminal of the fifth inverter NOT5, the drain of the forty-third transistor T43 is electrically connected to the second level signal line VGL line, and the source of the forty-third transistor T43 is electrically connected to the drain of the forty-fourth transistor T44;

[0276] The gate of the forty-fourth transistor T45, the gate of the forty-fifth transistor T45 and the sixth node F are electrically connected together;

[0277] The source of the forty-fourth transistor T45, the drain of the forty-fifth transistor T45 and the input terminal of the sixth inverter NOT6 are electrically connected together;

[0278] The gate of the forty-sixth transistor T46 is electrically connected to the first clock signal line, the source of the forty-sixth transistor T46 is electrically connected to the first level signal line VGH line, and the drain of the forty-sixth transistor T46 is electrically connected to the source of the forty-fifth transistor T45.

[0279] In the present application, refer to Figure 5 and Figure 6 , the fifth inverter NOT5 includes a thirty-seventh transistor T37 and a thirty-eighth transistor T38.

[0280] Among them, the thirty-seventh transistor T37 is a P-type MOS transistor, and the thirty-eighth transistor T38 is an N-type MOS transistor;

[0281] A gate of the thirty-seventh transistor T37, a gate of the thirty-eighth transistor T38 and the first clock signal line are electrically connected together;

[0282] The source of the thirty-seventh transistor T37 is electrically connected to the first level signal line VGH, and the drain of the thirty-eighth transistor T38 is electrically connected to the second level signal line VGL;

[0283] The drain of the thirty-seventh transistor T37 , the source of the thirty-eighth transistor T38 , and the first control terminal of the first tri-state inverter Tri-Inv1 are electrically connected together.

[0284] In the present application, refer to Figure 5 and Figure 6 , the sixth inverter NOT6 includes a forty-seventh transistor T47 and a forty-eighth transistor T48.

[0285] The forty-seventh transistor T47 is a P-type MOS transistor, and the forty-eighth transistor T48 is an N-type MOS transistor;

[0286] The gate of the forty-seventh transistor T47, the gate of the forty-eighth transistor T48 and the output end of the first tri-state inverter Tri-Inv1 are electrically connected together;

[0287] The source of the forty-seventh transistor T47 is electrically connected to the first level signal line VGH, and the drain of the forty-eighth transistor T48 is electrically connected to the second level signal line VGL;

[0288] The drain of the forty-seventh transistor T47, the source of the forty-eighth transistor T48 and the second signal output terminal Sout are electrically connected together.

[0289] In the present application, refer to Figure 5 and Figure 6 , the fifth transmission gate TG5 includes a forty-ninth transistor T49 and a fiftieth transistor T50.

[0290] Among them, the forty-ninth transistor T49 is an N-type MOS transistor, and the fiftieth transistor T50 is a P-type MOS transistor;

[0291] A gate of the forty-ninth transistor T49 is electrically connected to the output terminal of the first tri-state inverter Tri-Inv1.

[0292] The source of the 49th transistor T49, the source of the 50th transistor T50 and the first signal output terminal OUTN of the driving unit at this stage are electrically connected, and the drain of the 49th transistor T49, the drain of the 50th transistor T50 and the second clock signal line are electrically connected;

[0293] The gate of the fiftieth transistor T50 and the sixth node F are electrically connected.

[0294] In the present application, refer to Figure 4 , for example, the seventh transistor T7 includes an N-type MOS tube, and the eighth transistor T8 includes an N-type MOS tube.

[0295] In the embodiment of the present application, the shift register module 6 includes a fifth inverter NOT5, a first three-state inverter Tri-Inv1, a second three-state inverter Tri-Inv2, a fifth transmission gate TG5, a sixth inverter NOT6, a seventh transistor T7 and an eighth transistor T8; the shift register module 6 includes a P-type MOS tube and an N-type MOS tube, and the shift register module 6 outputs both positive voltage and negative voltage without loss. The charging rate is fast and the efficiency is the same when the positive voltage and the negative voltage are output, which can enhance the driving force of the driving circuit, thereby improving the display stability of the display device.

[0296] In some embodiments of the present application, the latch module 2 includes a first transistor T1, a second transistor T2, a third transistor T3 and a fourth transistor T4; the start row trigger module 3 includes a fifth transistor T5; the end row control module 5 includes a sixth transistor T6; the shift register module 6 includes a seventh transistor T7 and an eighth transistor T8;

[0297] The first transistor T1 , the fourth transistor T4 , the fifth transistor T5 , the sixth transistor T6 , the seventh transistor T7 and the eighth transistor T8 have the same polarity; the second transistor T2 and the third transistor T3 have the same polarity; and the first transistor T1 and the second transistor T2 have opposite polarities.

[0298] Below, taking the example that the first transistor T1, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 are all N-type transistors, the second transistor T2 and the third transistor T3 are all P-type transistors, and the third line is selected as the switching start line and the sixth line is selected as the switching end line in the positive scan mode, the working principle of the driving circuit is explained.

[0299] Reference Fig. 9 , wherein, in the resolution trigger display frame stage, the signal outputted from the first signal output terminal OUT3 of the driving unit connected to the third row of sub-pixels is consistent with the start row designation signal CGI;

[0300] In the resolution switching display frame stage, the signal outputted by the first signal output terminal OUT3 of the driving unit connected to the third row of sub-pixels is consistent with the start row designation signal CGI;

[0301] The falling edge of the trigger signal CGS is aligned with the rising edge of the start line designation signal CGI in the resolution switching display frame stage;

[0302] In the resolution switching display frame stage, the signal output by the first signal output terminal OUTN of the driving unit connected to the sixth row of sub-pixels is consistent with the end row designation signal CGE.

[0303] Fig.10 Select the 5th line as the switching start line and the 10th line as the switching end line. The timing rules of each control signal and the working principle of each line are the same as Fig. 9 The process of selecting the 3rd line as the switching start line and the 6th line as the switching end line is similar. For details, please refer to the following Fig. 9 This is just an example and will not be described in detail here.

[0304] For the second-level drive unit (the drive unit connected to the row before the switching start row), refer to Fig.11 :

[0305] The first output signal OUT2 and the switching start row designation signal CGI are not high level signals at the same time, the first NAND sub-circuit NAND1 outputs a high level signal, and the signal at the first node A after passing through the first inverter NOT1 is a low level signal; the reset signal Reset is a low level signal, the first transistor T1 is turned off, the first NOR gate sub-circuit NOR1 has no high level signal input, the first NOR gate sub-circuit NOR1 outputs a high level signal, the fourth transistor T4 is turned on, the third transistor T3 is turned off, and the second node B inputs a low level signal VGL; the first transmission gate TG1 is turned off, the fifth transistor T5 is turned on, and the third node C inputs a second level signal VGL.

[0306] In the resolution trigger display frame stage, the received row designation signal CGE is switched to a low level signal, the fourth transmission gate TG4 is turned on, and the fifth transistor T5 is turned off; the first control signal CNB is a low level signal, the second control signal CN is a high level signal, and the second transmission gate TG2 is turned on; the forward scan signal STVF is a high level signal, and the signal at the fourth node D is a high level signal through the second transmission gate TG2 and the fourth transmission gate TG4; the second NAND gate circuit NOR2 inputs a high level signal, and the second NAND gate circuit NOR2 outputs a low level signal, and the signal at the fifth node E after passing through the fourth inverter NOT4 is a high level signal; the first clock signal of the second row of sub-pixels is the CKB signal, and when the first clock signal CKB is a high level signal, the first three-state inverter Tri-Inv1 is turned on, the second three-state inverter Tri-Inv2 is turned off, the first three-state inverter Tri-Inv1 outputs a low-level signal, and the signal at the sixth node F after passing through the fifth inverter NOT5 is a high-level signal, that is, the second output signal Sout is a high-level signal, and a high-level signal is input to the positive scan signal line STVF connected to the third-level driving unit; when the first clock signal CK is switched to a low-level signal, the first three-state inverter Tri-Inv1 is turned off, the second three-state inverter Tri-Inv2 is turned on, the second three-state inverter Tri-Inv2 outputs a high-level signal, the fifth transmission gate TG5 is turned on, the seventh transistor T7 is turned off, the second clock signal CK is a high-level signal, and the first signal output terminal OUT3 outputs a high-level signal to scan the second row of sub-pixels.

[0307] In the resolution switching display frame stage, when the switching receiving row designation signal CGE signal is a low level signal, the fourth transmission gate TG4 is turned on and the fifth transistor T5 is turned off; the positive scan signal STVF signal is a low level signal, and the signal at the fourth node D is a low level signal through the second transmission gate TG2 and the fourth transmission gate TG4; when the switching receiving row designation signal CGE signal is a high level signal, the fourth transmission gate TG4 is turned off and the fifth transistor T5 is turned on, and the second level signal VGL signal is input at the fourth node D; the signal at the fourth node D remains a low level signal; the second NAND gate circuit NOR2 inputs two low level signals, the second NAND gate circuit NOR2 outputs a high level signal, and the signal at the fifth node E after passing through the fourth inverter NOT4 is a low level signal; the first clock signal CKB signal is high In the case of a first clock signal CKB, the first three-state inverter Tri-Inv1 is turned on, the second three-state inverter Tri-Inv2 is turned off, the first three-state inverter Tri-Inv1 outputs a high-level signal, and the signal at the sixth node F after passing through the fifth inverter NOT5 is a low-level signal, that is, the second output signal Sout is a low-level signal, and a low-level signal is input to the positive scan signal line STVF of the third-level driving unit; in the case of the first clock signal CKB being switched to a low-level signal, the first three-state inverter Tri-Inv1 is turned off, the second three-state inverter Tri-Inv2 is turned on, the second three-state inverter Tri-Inv2 outputs a high-level signal, the fifth transmission gate TG5 is turned off, the seventh transistor T7 is turned on, the first signal output terminal OUT2 outputs the second level signal VGL as a low-level signal, and the data of the second row of sub-pixels is not updated.

[0308] For the third-level driver unit (the driver unit that switches the start line connection), refer to Fig.12 :

[0309] In the resolution trigger display frame stage, the first output signal OUT3 of the third-level driving unit and the start row designation signal CGI are both high-level signals, the first NAND gate sub-circuit NAND1 outputs a low-level signal, and after passing through the first inverter NOT1, the signal at the first node A is a high-level signal; the reset signal Reset signal is a low-level signal, the first transistor T1 is turned off, and the second transistor T2 is turned on; a high-level signal is input to the input end of the first NOR gate sub-circuit NOR1, the first NOR gate circuit NOR1 outputs a low-level signal, the third transistor T3 is turned on, and the first-level signal VGH signal output by the first-level signal line reaches the second node B, and the signal at the second node B is a high-level signal. The first NOR gate sub-circuit NOR1 is connected to the drive unit of the first stage, and the second node B is used as an input terminal of the first NOR gate sub-circuit NOR1. The signal at the position of the first node A is subsequently restored to a low level signal. The first NOR gate sub-circuit NOR1 also has a second node B inputting a high level signal. The first NOR gate sub-circuit NOR1 outputs a low level signal. The second node B of the third-level driving unit is latched as a high level signal at the b1 position; the first transmission gate TG1 is turned on, the fifth transistor T5 is turned off, and the trigger signal CGS signal is input at the third node C position. When the trigger signal CGS signal is a low level signal, the signal at the third node C position is a low level signal; when the trigger signal CGS signal is a high level signal, the signal at the third node C position is a high level signal.

[0310] In the resolution switching display frame stage, the switching receiving row designation signal CGE signal is a low level signal, the fourth transmission gate TG4 is turned on, and the fifth transistor T5 is turned off; the first control signal CNB signal is a low level signal, the second control signal CN signal is a high level signal, and the second transmission gate TG2 is turned on; the positive scan signal STVF signal is a low level signal, and the signal at the fourth node D position is a low level signal through the second transmission gate TG2 and the fourth transmission gate TG4; when the trigger signal CGS signal is a high level signal, the signal at the third node C position is a high level signal, the second NAND gate circuit NOR2 inputs a high level signal, the second NAND gate circuit NOR2 outputs a low level signal, and the signal at the fifth node E position after passing through the fourth inverter NOT4 is a high level signal; the first clock signal of the third row sub-pixel is the CK signal, and after the first clock signal CK signal When the first clock signal CK is switched to a low-level signal, the first three-state inverter Tri-Inv1 is turned off, the second three-state inverter Tri-Inv2 is turned off, the first three-state inverter Tri-Inv1 outputs a low-level signal, and the signal at the sixth node F after passing through the fifth inverter NOT5 is a high-level signal, that is, the second output signal Sout is a high-level signal, and a high-level signal is input to the positive scan signal line STVF of the fourth-stage driving unit; when the first clock signal CK is switched to a low-level signal, the first three-state inverter Tri-Inv1 is turned off, the second three-state inverter Tri-Inv2 is turned on, the second three-state inverter Tri-Inv2 outputs a high-level signal, the fifth transmission gate TG5 is turned on, the seventh transistor T7 is turned off, the second clock signal CKB is a high-level signal, and the first signal output terminal OUT3 outputs a high-level signal to scan the third row of sub-pixels.

[0311] The second node B of the third-stage driving unit is latched as a high-level signal after the first output signal OUT3 and the start row designation signal CGI are both high-level signals for the first time. Therefore, in the resolution switching display frame stage, the start row designation signal CGI includes two situations:

[0312] First, in the resolution switching display frame stage, the signal OUTN outputted from the first signal output terminal of the driving unit connected to the switching start row is consistent with the start row designation signal CGI.

[0313] Second, in the resolution switching display frame stage, the start line designation signal CGI is a low-level signal with a constant voltage.

[0314] For the fourth-level driver unit (the driver unit that switches the start line connection), refer to Fig.13 :

[0315] The first output signal OUT4 and the switching start row designation signal CGI are not high level signals at the same time, the first NAND sub-circuit NAND1 outputs a high level signal, and the signal at the first node A after passing through the first inverter NOT1 is a low level signal; the reset signal Reset is a low level signal, the first transistor T1 is turned off, the first NOR gate sub-circuit NOR1 has no high level signal input, the first NOR gate sub-circuit NOR1 outputs a high level signal, the fourth transistor T4 is turned on, the third transistor T3 is turned off, and the second node B inputs a low level signal VGL; the first transmission gate TG1 is turned off, the fifth transistor T5 is turned on, and the third node C inputs a second level signal VGL.

[0316] In the resolution trigger display frame stage, the received row designation signal CGE is switched to a low level signal, the fourth transmission gate TG4 is turned on, and the fifth transistor T5 is turned off; the first control signal CNB is a low level signal, the second control signal CN is a high level signal, and the second transmission gate TG2 is turned on; the forward scan signal STVF is a high level signal, and the signal at the fourth node D is a high level signal through the second transmission gate TG2 and the fourth transmission gate TG4; the second NAND gate circuit NOR2 inputs a high level signal, and the second NAND gate circuit NOR2 outputs a low level signal, and the signal at the fifth node E after passing through the fourth inverter NOT4 is a high level signal; the first clock signal of the fourth row of sub-pixels is the CKB signal, and when the first clock signal CKB is a high level signal, the first three-state inversion The first three-state inverter Tri-Inv1 is turned on, the second three-state inverter Tri-Inv2 is turned off, the first three-state inverter Tri-Inv1 outputs a low level signal, the signal at the sixth node F after passing through the fifth inverter NOT5 is a high level signal, the second output signal Sout is a high level signal, and a high level signal is input to the positive scan signal line STVF of the fifth-stage driving unit; when the first clock signal CK is switched to a low level signal, the first three-state inverter Tri-Inv1 is turned off, the second three-state inverter Tri-Inv2 is turned on, the second three-state inverter Tri-Inv2 outputs a high level signal, the fifth transmission gate TG5 is turned on, the seventh transistor T7 is turned off, the second clock signal CK is a high level signal, the first signal output terminal OUT4 outputs a high level signal, and the fourth row of sub-pixels is scanned.

[0317] In the resolution switching display frame stage, when the switching receiving row designation signal CGE is a low level signal, the fourth transmission gate TG4 is turned on and the fifth transistor T5 is turned off; when the second output signal Sout signal output by the third-level driving unit is a high level signal, the forward scanning signal STVF signal of the fourth-level driving unit is a high level signal, and the signal at the fourth node D is a high level signal through the second transmission gate TG2 and the fourth transmission gate TG4; the second NAND gate sub-circuit NOR2 inputs a high level signal, and the second NAND gate sub-circuit NOR2 outputs a low level signal, and the signal at the fifth node E after passing through the fourth inverter NOT4 is a high level signal; when the signal at the fifth node E is a high level signal, the second output signal Sout signal is a high level signal, and a high level signal is input to the forward scanning signal line STVF line of the fifth-level driving unit; the first signal output terminal OUT4 outputs a high level signal to scan the fourth row of sub-pixels.

[0318] In this way, the driving circuit starts scanning from the third row of sub-pixels row by row in the direction of increasing number of sub-pixel rows.

[0319] For the sixth-level driver unit (the driver unit that switches the end row connection), refer to Fig.13 :

[0320] The first output signal OUT4 and the switching start row designation signal CGI are not high level signals at the same time, the first NAND sub-circuit NAND1 outputs a high level signal, and the signal at the first node A after passing through the first inverter NOT1 is a low level signal; the reset signal Reset is a low level signal, the first transistor T1 is turned off, the first NOR gate sub-circuit NOR1 has no high level signal input, the first NOR gate sub-circuit NOR1 outputs a high level signal, the fourth transistor T4 is turned on, the third transistor T3 is turned off, and the second node B inputs a low level signal VGL; the first transmission gate TG1 is turned off, the fifth transistor T5 is turned on, and the third node C inputs a second level signal VGL.

[0321] In the resolution switching display frame stage, the sixth-level driving circuit will receive a high-level positive scan signal STVF, the switching end row designation signal CGE is a low-level signal, the fourth transmission gate TG4 is turned on, the sixth transistor T6 is turned off, the signal at the fourth node D is a high-level signal, and the signal at the fifth node E is a high-level signal; when the signal at the fifth node E is a high-level signal, the second output signal Sout is a high-level signal, and a high-level signal is input to the positive scan signal line STVF line of the seventh-level driving unit; the first signal output terminal OUT6 outputs a high-level signal to scan the sixth row of sub-pixels.

[0322] For the seventh-level drive unit (the drive unit of the next row after the switching end row), refer to Fig.14 :

[0323] In the resolution switching display frame, the seventh-level driving unit receives the high-level forward scanning signal STVF signal output by the sixth-level driving unit, the switching row designation signal CGE signal is a high-level signal, the fourth transmission gate TG4 of the seventh-level unit is closed, the sixth transistor T6 is opened, the signal at the fourth node D is a low-level signal, and the signal at the fifth node E is a low-level signal; when the first clock signal CK signal is a high-level signal, the first three-state inverter Tri-Inv1 is opened, the signal at the sixth node F is a low-level signal, and the high-level forward scanning signal STVF signal is not output to the eighth-level driving unit; when the first clock signal CK signal is switched to a low-level signal, the first three-state inverter Tri-Inv1 is closed, the second three-state inverter Tri-Inv2 is opened, the second three-state inverter Tri-Inv2 outputs a high-level signal, the fifth transmission gate TG5 is closed, the seventh transistor T7 is opened, the first signal output terminal OUT7 outputs the second level signal VGL signal as a low-level signal, and the data of the seventh row of sub-pixels is not updated.

[0324] In this way, the driving circuit realizes scanning from the third row of sub-pixels to the sixth row of sub-pixels.

[0325] In some embodiments of the present application, in the resolution-triggered display frame stage, the signal OUTN signal outputted from the first signal output terminal OUTN of the driving unit connected to the switching start row is consistent with the start row designation signal CGI signal.

[0326] Take the resolution of the display device as H*V as an example, where V is the number of rows of pixels and H is the number of columns of pixels. Fig.16 , t is the pulse width of the clock signal, and t1 is the time before the STV signal falls.

[0327] Taking the forward scanning mode as an example, the switching starting line is the mth line. In the resolution trigger display frame stage, the timing of the starting line specifying signal CGI signal is:

[0328] Delay_t1=t1+(m-1)*t (1)

[0329] Wherein, Delay_t1 is the rising timing of the start row designation signal CGI.

[0330] For example, refer to Fig. 9 The switching starting line is the third row of sub-pixels. In the resolution trigger display frame stage, the starting row designation signal CGI signal rises at t1+2*t.

[0331] Since the second node B at the switching start is latched as a high level signal after the first output signal OUTN and the start row designation signal CGI are both high level signals for the first time, the start row designation signal CGI includes two situations in the resolution switching display frame stage:

[0332] First, in the resolution switching display frame stage, the signal OUTN outputted from the first signal output terminal of the driving unit connected to the switching start row is consistent with the start row designation signal CGI.

[0333] Second, in the resolution switching display frame stage, the start line designation signal CGI is a low-level signal with a constant voltage.

[0334] In the first case, taking the normal scanning mode as an example, the switching start line is the mth line, and the switching end line is the nth line. In the resolution switching display frame stage, refer to Fig.16 , the timing of the start line specifying signal CGI signal is:

[0335] Delay_t2=t1+V*t+{m-[Ceil(m / h)-1]*h-1}*t (2)

[0336] T=(n-m+1)*t (3)

[0337] Wherein, T is the period of the start row designation signal CGI, Ceil is the upward rounding function, and h is the number of clock signals. For example, in the present application, h is 2 (CK and CKB).

[0338] For example, refer to Fig. 9 The switching start line is the third row of sub-pixels, and the switching end line is the sixth row of sub-pixels. In the resolution switching display frame stage, the start row designation signal CGI signal rises at t1+12*t and rises once every 4t.

[0339] In some embodiments of the present application, the falling edge of the trigger signal CGS is aligned with the rising edge of the start row designation signal CGI in the resolution switching display frame stage.

[0340] Reference Fig.16 , then in the resolution switching display frame stage, the timing of the trigger signal CGS signal is:

[0341] Delay_t3=Delay_t2-t (4)

[0342] T=(n-m+1)*t (5)

[0343] Wherein, T is the period of the trigger signal CGS.

[0344] For example, refer to Fig. 9 The switching start behavior is the third row of sub-pixels, and the switching end behavior is the sixth row of sub-pixels. The trigger signal CGS rises at t1+11*t and rises once every 4t.

[0345] In some embodiments of the present application, in the resolution switching display frame stage, the signal output from the first signal output terminal OUTN of the driving unit connected to the switching end row is consistent with the end row designation signal CGE.

[0346] Reference Fig.16 , in the resolution switching display frame stage, the timing of the end line specifying signal CGE signal is:

[0347] Delay_t4= Delay_t2+(nm)*t (6)

[0348] T=(n-m+1)*t (7)

[0349] Wherein, T is the period of the end row designation signal CGE.

[0350] For example, refer to Fig. 9 The switching start line is the third row of sub-pixels, the switching end line is the sixth row of sub-pixels, and the end row designation signal CGE rises at t1+15*t and rises once every 4t.

[0351] In some embodiments of the present application, reference Fig.17 , the pulse width t2 of the clock signal in the resolution triggering display frame stage is smaller than the pulse width t3 of the clock signal in the resolution switching display frame stage.

[0352] In the resolution switching display frame stage, since the driving circuit only scans the sub-pixels between the switching start row and the switching end row, the pulse width of the clock signal can be increased without increasing the total time of one frame.

[0353] For example, Fig.17 In the resolution-triggered display frame, the driving circuit scans 12 rows of sub-pixels. In the resolution-switched display frame stage, the driving circuit scans 4 rows of sub-pixels. The pulse width t3 of the clock signal can be increased to be greater than the pulse width t2 of the clock signal of the resolution-triggered display frame. The time of one frame is not increased, and the refresh rate will not be reduced.

[0354] In some embodiments of the present application, the pulse width t2 of the clock signal in the resolution-triggered display frame stage is smaller than the pulse width t3 of the clock signal in the resolution-switched display frame stage; in the resolution-triggered display frame stage, the charging time of each row of sub-pixels can be increased to avoid the problem of insufficient sub-pixel charging time.

[0355] In some embodiments of the present application, the driving units connected to at least two adjacent rows of sub-pixels are electrically connected to the same clock signal line.

[0356] In some embodiments, reference Fig.18 , the driving units connecting two adjacent rows of sub-pixels are electrically connected to the same clock signal line, and the two driving circuits scan two adjacent rows of sub-pixels respectively at the same time; in some embodiments, the driving units connecting three adjacent rows of sub-pixels are electrically connected to the same clock signal line.

[0357] It should be noted that the driving unit connecting two adjacent rows of sub-pixels is different from the pixel driving unit that is electrically connected to the same clock signal line and drives two rows of sub-pixels at the same time with one driving unit. The former has a driving unit for each row of sub-pixels, and the driving unit is electrically connected to the same clock signal; the latter has only one driving unit for two rows of sub-pixels.

[0358] In the embodiment of the present application, the driving units connected to at least two adjacent rows of sub-pixels are electrically connected to the same clock signal line, so that at least two rows of sub-pixels can be simultaneously charged, the resolution of the screen can be reduced, and the pulse width can be increased, thereby increasing the charging time and avoiding the problem of insufficient charging of high-frequency pixel rows.

[0359] An embodiment of the present application provides a display device, comprising the driving circuit as described above.

[0360] The display device provided in the embodiments of the present application may be an LCD (Liquid Crystal Display) display device.

[0361] In addition, the display device may be a display device such as a monitor, as well as any product or component with a display function such as a television, a digital camera, a mobile phone, a tablet computer, etc. that includes these display devices.

[0362] The embodiment of the present application provides a display device, which includes a driving circuit, wherein the driving circuit includes: a plurality of driving units arranged in cascade, wherein the driving units are electrically connected to at least one row of sub-pixels, and wherein the driving units include: a starting row control module 1, which is electrically connected to a first signal output terminal OUTN of the driving unit at this stage, a starting row designation signal line CGI line, and a first node A, and is configured to be able to designate one row of sub-pixels as a switching starting row under the control of a starting row designation signal CGI signal output by the starting row designation signal line CGI line; a latch module 2, which is electrically connected to a starting row designation signal line CGI line, a reset signal line Reset line, a first level signal line (for example, a VGH line), and a second level signal line ( For example, the VGL line), the first node A and the second node B are electrically connected, and are configured to be able to latch the start row designation signal CGI signal; the start row trigger module 3 is electrically connected to the second node B, the trigger signal line CGS line, the second level signal line (for example, the VGL line) and the third node C, respectively, and is configured to be able to trigger the switching start row to start scanning under the control of the trigger signal CGS signal output by the trigger signal line CGS line; in this way, when full-screen display is not required or the display device has low power, any row of sub-pixels can be designated as the switching start row, and scanning can be started from the designated switching start row, and the data of some sub-pixels will not be updated, thereby reducing the power consumption of the display and extending the standby time of the display device.

[0363] In some embodiments of the present application, when the resolution of the picture displayed in the resolution switching display frame stage is less than or equal to half the resolution of the picture displayed in the resolution triggering display frame stage, the refresh rate of the resolution switching display frame stage is greater than the refresh rate of the resolution triggering display frame stage.

[0364] When the resolution of the picture displayed in the resolution switching display frame stage is less than or equal to half of the resolution of the picture displayed in the resolution triggering display frame stage, without changing the pulse width of the clock signal, the time to scan the sub-pixel row is less than or equal to half of the time to scan the full-resolution sub-pixel row, thereby increasing the refresh rate of the resolution switching display frame stage.

[0365] For example, for a display device with a resolution of 1920*1080 in display area AA and a refresh rate of 60 Hz, if after switching the resolution, the resolution of the area of ​​the display screen becomes less than or equal to 960*1080, then the refresh rate can be switched to 120 Hz.

[0366] In some embodiments of the present application, when the resolution of the picture displayed in the resolution switching display frame stage is less than or equal to half of the resolution of the picture displayed in the resolution triggering display frame stage, the refresh rate of the resolution switching display frame stage is greater than the refresh rate of the resolution triggering display frame stage; high refresh rate can be achieved at low resolution, thereby improving picture smoothness.

[0367] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A driving circuit, wherein: include: A plurality of driving units arranged in cascade, wherein the driving units are electrically connected to at least one row of sub-pixels, and the driving units include: a start row control module, electrically connected to the first signal output terminal, the start row designation signal line and the first node of the driving unit at this stage, and configured to designate one row of the sub-pixels as a switching start row under the control of the start row designation signal output by the start row designation signal line; a latch module, electrically connected to the start row designation signal line, the reset signal line, the first level signal line, the second level signal line, the first node and the second node, respectively, and configured to latch the start row designation signal; a start row trigger module, electrically connected to the second node, the trigger signal line, the second level signal line and the third node respectively, and configured to trigger the switching start row to start scanning under the control of the trigger signal output by the trigger signal line; The driving unit further comprises: The signal input module is electrically connected to the first control signal line and the second control signal line, respectively, and is configured to input an enable signal to the switching start line under the joint control of the signals output by the first control signal line and the second control signal line, and control the drive circuit to scan starting from the switching start line in the direction of decreasing the number of sub-pixel rows or increasing the number of sub-pixel rows.

2. The driving circuit according to claim 1, wherein: The driving unit further comprises: An end row control module is electrically connected to the third node, the signal input module, the end row designation signal line, the second level signal line and the fifth node, respectively, and is configured to designate one of the multiple rows of sub-pixels as a switching end row under the control of the enable signal output by the signal input module, the signal at the third node position and the end row designation signal input by the end row designation signal line.

3. The driving circuit according to claim 2, wherein: The driving unit further comprises: The shift register module is electrically connected to the fifth node, the first clock signal line, the second clock signal line, the reset signal line, the second level signal line, and the first signal output terminal and the second signal output terminal of the driving unit, respectively, and is configured to realize row-by-row scanning between the switching start row and the switching end row under the joint control of the signal at the fifth node position, the first clock signal input by the first clock signal line, and the second clock signal input by the second clock signal line.

4. The driving circuit according to claim 3, wherein: The signal input module comprises a forward scan input submodule and a reverse scan input submodule; the forward scan input submodule and the reverse scan input submodule are connected together and electrically connected to the end line control module; The positive scan input submodule is electrically connected to the positive scan signal line, the first control signal line and the second control signal line respectively, and is configured to output the positive scan signal transmitted by the positive scan signal line under the common control of the first control signal input by the first control signal line and the second control signal input by the second control signal line; The reverse sweep input submodule is electrically connected to the reverse sweep signal line, the first control signal line and the second control signal line respectively, and is configured to output the reverse sweep signal transmitted by the reverse sweep signal line under the common control of the first control signal input by the first control signal line and the second control signal input by the second control signal line; Wherein, the end row control module is configured to be able to receive the forward scanning signal or the reverse scanning signal, the forward scanning signal is configured to be able to control the driving circuit to scan from the switching starting row along the direction of increasing number of sub-pixel rows, and the reverse scanning signal is configured to be able to control the driving circuit to scan from the switching starting row along the direction of decreasing number of sub-pixel rows.

5. The driving circuit according to claim 1, wherein: The start row control module includes a first NAND gate circuit and a first inverter; The first signal output terminal of the driving unit at this level and the starting row designated signal line are electrically connected to the two input terminals of the first NAND gate sub-circuit respectively, the input terminal of the first inverter is electrically connected to the output terminal of the first NAND gate sub-circuit, and the output terminal of the first inverter is electrically connected to the first node.

6. The driving circuit according to claim 1, wherein: The latch module includes a first transistor, a first NOR gate subcircuit, a second transistor, a third transistor and a fourth transistor; The gate of the first transistor is electrically connected to the reset signal line, the source of the first transistor is electrically connected to the start row designation signal line, and the drain of the first transistor is electrically connected to an input terminal of the first NOR gate sub-circuit and the second node respectively; Two input terminals of the first NOR gate sub-circuit are electrically connected to the first node and the second node respectively, and an output terminal of the first NOR gate sub-circuit is electrically connected to the gate of the third transistor and the gate of the fourth transistor respectively; The gate of the second transistor is electrically connected to the reset signal line, the source of the second transistor is electrically connected to the first level signal line, and the drain of the second transistor is electrically connected to the source of the third transistor; The drain of the third transistor, the source of the fourth transistor, and the second node are electrically connected together, and the drain of the fourth transistor is electrically connected to the second level signal line.

7. The driving circuit according to claim 1, wherein: The start row trigger module includes a second inverter, a first transmission gate and a fifth transistor; The input terminal of the second inverter is electrically connected to the second node, and the output terminal of the second inverter is electrically connected to the gate of the fifth transistor and the first control terminal of the first transmission gate respectively; The second control terminal of the first transmission gate is electrically connected to the second node, the input terminal of the first transmission gate is electrically connected to the trigger signal line, and the output terminal of the first transmission gate is electrically connected to the third node; A source of the fifth transistor is electrically connected to the second-level signal line, and a drain of the fifth transistor is electrically connected to the third node.

8. The driving circuit according to claim 4, wherein: The forward scan input submodule includes a second transmission gate, and the reverse scan input submodule includes a third transmission gate; The first control end of the second transmission gate is electrically connected to the first control signal line, the second control end of the second transmission gate is electrically connected to the second control signal line, the input end of the second transmission gate is electrically connected to the positive scan signal line, and the output end of the second transmission gate is connected to the end line control module; The first control end of the third transmission gate is electrically connected to the second control signal line, the second control end of the third transmission gate is electrically connected to the first control signal line, the input end of the third transmission gate is electrically connected to the reverse scan signal line, and the output end of the third transmission gate is connected to the end line control module; An output terminal of the second transmission gate is connected to an output terminal of the third transmission gate.

9. The driving circuit according to claim 8, wherein: The end row control module includes a third inverter, a fourth transmission gate, a sixth transistor, a second NOR gate subcircuit and a fourth inverter; The input end of the third inverter is electrically connected to the end row designation signal line and the gate of the sixth transistor, and the output end of the third inverter is electrically connected to the second control end of the fourth transmission gate; The first control terminal of the fourth transmission gate is electrically connected to the input terminal of the third inverter, the input terminal of the fourth transmission gate is electrically connected to the signal input module, and the output terminal of the fourth transmission gate is electrically connected to the fourth node; A source of the sixth transistor is electrically connected to the second level signal line, and a drain of the sixth transistor is electrically connected to the fourth node; Two input terminals of the second NOR gate subcircuit are electrically connected to the third node and the fourth node respectively, an output terminal of the second NOR gate subcircuit is electrically connected to an input terminal of the fourth inverter, and an output terminal of the fourth inverter is electrically connected to the fifth node.

10. The driving circuit according to claim 9, wherein: The shift register module includes a fifth inverter, a first tri-state inverter, a second tri-state inverter, a fifth transmission gate, a sixth inverter, a seventh transistor and an eighth transistor; The input end of the fifth inverter is electrically connected to the first clock signal line, and the output end of the fifth inverter is electrically connected to the first control end of the first tri-state inverter and the second control end of the second tri-state inverter respectively; The second control terminal of the first tri-state inverter is electrically connected to the first clock signal line, the input terminal of the first tri-state inverter is electrically connected to the fifth node, and the output terminal of the first tri-state inverter is electrically connected to the gate of the seventh transistor and the input terminal of the sixth inverter respectively; The first control terminal of the second tri-state inverter is electrically connected to the first clock signal line, the input terminal of the second tri-state inverter is electrically connected to the sixth node, and the output terminal of the second tri-state inverter is electrically connected to the gate of the seventh transistor and the input terminal of the sixth inverter respectively; The output end of the sixth inverter is electrically connected to the sixth node and the second signal output end of the driving unit at this stage respectively; The first control end of the fifth transmission gate is electrically connected to the output end of the first tri-state inverter and the output end of the second tri-state inverter respectively, the second control end of the fifth transmission gate is electrically connected to the output end of the sixth inverter, the input end of the fifth transmission gate is electrically connected to the second clock signal line, and the output end of the fifth transmission gate is electrically connected to the first signal output end of the driving unit at this stage; The source of the seventh transistor is electrically connected to the second-level signal line, and the drain of the seventh transistor is electrically connected to the first signal output terminal of the driving unit at this level; the gate of the eighth transistor is electrically connected to the reset signal line, the source of the eighth transistor is electrically connected to the sixth node, and the drain of the eighth transistor is electrically connected to the second-level signal line.

11. The driving circuit according to claim 10, wherein: The latch module includes a first transistor, a second transistor, a third transistor and a fourth transistor; the start line trigger module includes a fifth transistor; The first transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor have the same polarity; the second transistor and the third transistor have the same polarity; and the first transistor and the second transistor have opposite polarities.

12. The driving circuit according to claim 11, wherein: The first transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor are all N-type transistors, and the second transistor and the third transistor are all P-type transistors.

13. The driving circuit according to claim 2, wherein: In the resolution-triggered display frame stage, the signal outputted by the first signal output terminal of the driving unit connected to the switching start row is consistent with the start row designation signal.

14. The driving circuit according to claim 13, wherein: In the resolution switching display frame stage, the signal outputted by the first signal output terminal of the driving unit connected to the switching start row is consistent with the start row designation signal.

15. The driving circuit according to claim 13, wherein: In the resolution switching display frame, the start line designation signal is a low level signal with a constant voltage.

16. The driving circuit according to claim 14, wherein: The falling edge of the trigger signal is aligned with the rising edge of the start row designation signal in the resolution switching display frame phase.

17. The driving circuit according to claim 16, wherein: In the resolution switching display frame stage, the signal outputted by the first signal output terminal of the driving unit connected to the switching end row is consistent with the end row designation signal.

18. The driving circuit according to claim 14, wherein: The pulse width of the clock signal in the resolution triggering display frame stage is smaller than the pulse width of the clock signal in the resolution switching display frame stage.

19. The driving circuit according to claim 17, wherein: The driving units connected to at least two adjacent rows of sub-pixels are electrically connected to the same clock signal line.

20. A display device, wherein: The invention comprises a driving circuit as claimed in any one of claims 1 to 19.

21. The display device according to claim 20, wherein: The display device includes a resolution triggering display frame stage and a resolution switching display frame stage; When the resolution of the picture displayed in the resolution switching display frame stage is less than or equal to half of the resolution of the picture displayed in the resolution triggering display frame stage, the refresh rate of the resolution switching display frame stage is greater than the refresh rate of the resolution triggering display frame stage.

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