Array substrate and display panel

Abstract

The application provides an array substrate and a display panel. The array substrate comprises a substrate and a thin film transistor, a first insulating layer, a planar layer, a metal conductive layer and a transparent electrode layer which are sequentially formed on one side of the substrate; the first insulating layer and the planar layer cover the thin film transistor; the metal conductive layer forms a metal reflection layer; the first insulating layer has an exposed part covering a channel region of the thin film transistor; a through hole is arranged on the planar layer to at least partially expose the exposed part; a conductive layer which is electrically connected to a gate electrode of the thin film transistor is arranged in the through hole, the conductive layer comprises a metal light shielding layer and / or a transparent conductive layer, and covers the exposed part. The planar layer above the channel region is subjected to a hole digging treatment, so that the planar layer does not shield the channel region, thereby avoiding affecting the performance of the thin film transistor and further avoiding a tailing phenomenon; meanwhile, the conductive layer which is electrically connected to the gate electrode is arranged above the channel region to form a double-gate structure, thereby improving the performance of the thin film transistor.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to an array substrate and a display panel. BACKGROUND

[0002] Electronic paper display technology (E-paper) is a kind of "microcapsule electrophoresis display" (EPD) technology, which has a display effect close to that of natural paper and is free from reading fatigue. Electronic paper is widely used in consumer, industrial, smart home, smart medical and other fields.

[0003] When used as an electronic reader, electronic paper is prone to "trailing" phenomenon, that is, obvious switching traces appear in the picture switching refresh process, which is mainly caused by parasitic capacitance and TFT (thin film transistor) leakage current. In order to reduce the parasitic capacitance, the industry generally uses relatively thick organic materials to make the capacitor medium. However, in the array substrate process, the organic material directly above the TFT will cause the TFT leakage current to increase significantly, resulting in obvious trailing. On the other hand, in the case that the on-state current of the TFT is not large enough, the width of the TFT needs to be increased to ensure sufficient on-state current, but this will affect the planar space of the TFT backplane, resulting in a decrease in storage capacitance or a sacrifice of the resolution of the electronic display. SUMMARY

[0004] The technical problem solved by the present application is to provide an array substrate and a display panel to solve the problem of obvious switching traces in the picture switching refresh process in the prior art.

[0005] To solve the above technical problem, the first technical solution provided by the present application is to provide an array substrate, wherein the array substrate comprises:

[0006] a substrate, a thin film transistor, a first insulating layer, a planar layer, a metal conductive layer and a transparent electrode layer formed in sequence on one side of the substrate; the first insulating layer and the planar layer both cover the thin film transistor; the metal conductive layer forms a metal reflection layer; and the transparent electrode layer forms a pixel electrode.

[0007] The first insulating layer has an exposed part covering a channel region of the thin film transistor; the planar layer is provided with a through hole to at least partially expose the exposed part; and the through hole is provided with a conductive layer electrically connected with the gate of the thin film transistor, the conductive layer comprising a metal light shielding layer and / or a transparent conductive layer and covering the exposed part.

[0008] In the direction perpendicular to the substrate, the part of the active layer of the thin film transistor that does not overlap with the source and the drain of the thin film transistor is defined as the channel region; and the exposed part is located between the source and the drain and completely covers the channel region.

[0009] The through hole is a necked structure, and the cross-sectional area of the through hole gradually decreases in the direction towards the substrate; the through hole has oppositely arranged first and second apertures, the cross-sectional area of the first aperture is greater than that of the second aperture; the orthographic projection of the first aperture on the exposed portion is located within the exposed portion.

[0010] The conductive layer is located at the second aperture of the through hole and covers the second aperture.

[0011] The thin film transistor is of a bottom gate structure.

[0012] The metal reflective layer is arranged on the side surface of the planar layer away from the substrate, and the pixel electrode covers the metal reflective layer.

[0013] The conductive layer is arranged in insulation with the pixel electrode and in insulation with the metal reflective layer.

[0014] The conductive layer includes the metal light shielding layer, the metal light shielding layer is formed on the metal conductive layer, and is electrically connected with the gate electrode;

[0015] Or, the conductive layer includes the transparent conductive layer, the transparent conductive layer is formed on the transparent electrode layer, and is electrically connected with the gate electrode;

[0016] Or, the conductive layer includes the metal light shielding layer and the transparent conductive layer, the transparent conductive layer is arranged on the side of the metal light shielding layer away from the substrate, and covers the metal light shielding layer.

[0017] Further comprising a second insulating layer, the second insulating layer is arranged in the through hole and covers the conductive layer.

[0018] To solve the above technical problems, the second technical solution provided by the present application is to provide a display panel, wherein the display panel comprises the array substrate.

[0019] The beneficial effects of the present application: Different from the prior art, the present application provides an array substrate and a display panel, the array substrate comprising a substrate and a thin film transistor, a first insulating layer, a planar layer, a metal conductive layer and a transparent electrode layer formed in sequence on one side of the substrate; the first insulating layer and the planar layer both cover the thin film transistor; the metal conductive layer forms a metal reflection layer; the transparent electrode layer forms a pixel electrode; wherein the first insulating layer has an exposed part covering a channel region of the thin film transistor; the planar layer is provided with a through hole to at least partially expose the exposed part; the through hole is provided with a conductive layer electrically connected with the gate of the thin film transistor, the conductive layer comprising a metal light shielding layer and / or a transparent conductive layer, and covering the exposed part. By digging the hole in the planar layer above the channel region, the planar layer is prevented from shielding the channel region to affect the performance of the thin film transistor, thereby avoiding the tailing phenomenon; at the same time, the conductive layer electrically connected with the gate is arranged above the channel region to form a double-gate structure, thereby improving the performance of the thin film transistor. BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort.

[0021] Figure 1 is a structural schematic diagram of the first embodiment of the array substrate provided by the present application;

[0022] Figure 2 is a structural schematic diagram of the second embodiment of the array substrate provided by the present application;

[0023] Figure 3 is a structural schematic diagram of the third embodiment of the array substrate provided by the present application;

[0024] Figure 4 is a structural schematic diagram of the fourth embodiment of the array substrate provided by the present application;

[0025] Figure 5 is a structural schematic diagram of the fifth embodiment of the array substrate provided by the present application;

[0026] Figure 6 is a structural schematic diagram of the sixth embodiment of the array substrate provided by the present application.

[0027] Explanation of reference numerals:

[0028] Array substrate-100, substrate-10, thin film transistor-20, active layer-21, channel region-210, ohmic contact layer-22, first insulating layer-30, exposed part-31, planar layer-40, via-41, first aperture-411, second aperture-412, metal conductive layer-50, metal reflective layer-51, transparent electrode layer-60, pixel electrode-61, conductive layer-70, metal light shielding layer-71, transparent conductive layer-72, second insulating layer-80, first metal layer-101, gate-23, gate insulating layer-102, second metal layer-103, source-24, drain-25. DETAILED DESCRIPTION

[0029] The technical solutions in the embodiments of the present application will be described below in detail with reference to the accompanying drawings.

[0030] In the following description, specific details are set forth, such as particular system configurations, interfaces, techniques, in order to provide a thorough understanding of the present application. However, techniques, apparatuses and systems that are known in the art can not have been described in detail in order to avoid unnecessarily obscuring the present application.

[0031] The technical solutions in the embodiments of the present application will be described below in detail with reference to the accompanying drawings.

[0032] The terms "first", "second", "third" in the present application are only used for descriptive purpose, and can not be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second", "third" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise specifically limited. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present application are only used to explain the relative position relationship, movement condition, etc. between the components in a certain posture (as shown in the drawings), and if the certain posture changes, the directional indications also change accordingly. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units is not limited to the listed steps or units, but can optionally include steps or units not listed, or can optionally include other steps or units inherent to the process, method, product or device.

[0033] Reference to“an embodiment” herein means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase“in an embodiment” in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily all directed to the same embodiment, nor are they necessarily all mutually exclusive or alternative embodiments.

[0034] Reference will now be made to Figure 1 , Figure 1 is a structural schematic diagram of a first embodiment of an array substrate provided by the application.

[0035] The application provides an array substrate 100, which comprises a substrate 10 and a thin film transistor 20, a first insulating layer 30, a planar layer 40, a metal conductive layer 50 and a transparent electrode layer 60 formed in sequence on one side of the substrate 10. The first insulating layer 30 and the planar layer 40 both cover the thin film transistor 20 and the substrate 10.

[0036] The first insulating layer 30 can be an inorganic insulating material such as silicon nitride or silicon dioxide, which is not limited here and can be selected according to actual needs.

[0037] The thickness of the planar layer 40 is greater than that of the first insulating layer 30. The planar layer 40 can be an organic insulating material such as PFA (Polymer Filmon Array), which is not limited here and can be selected according to actual needs.

[0038] The metal conductive layer 50 forms a metal reflection layer 51 for reflecting ambient light irradiated onto the metal reflection layer 51. The metal reflection layer 51 is arranged on the side surface of the planar layer 40 away from the substrate 10.

[0039] The transparent electrode layer 60 forms a pixel electrode 61, which covers the metal reflection layer 51 to protect the metal reflection layer 51 from being eroded by electrophoretic fluid. The material of the transparent electrode layer 60 is indium tin oxide (ITO), which can also be other transparent conductive materials, which are not limited here and can be selected according to actual needs.

[0040] The thin film transistor 20 is of a bottom gate structure. Specifically, the array substrate 100 further comprises a first metal layer 101, a gate insulating layer 102 and a second metal layer 103 arranged in sequence. The first metal layer 101 is arranged on the side surface of the substrate 10, the second metal layer 103 is arranged on the side of the first insulating layer 30 close to the substrate 10, and the first insulating layer 30 covers the second metal layer 103.

[0041] The first metal layer 101 forms a scan line (not shown), a substrate common electrode trace (not shown), and a gate 23 of a thin film transistor 20.

[0042] The second metal layer 103 forms a data line (not shown), a source 24 and a drain 25 of the thin film transistor 20.

[0043] The thin film transistor 20 further includes an active layer 21. The active layer 21 is disposed between the gate insulating layer 102 and the second metal layer 103, and corresponds to the gate 23. The active layer 21 is provided with two spaced apart ohmic contact layers 22 on the side away from the substrate 10. One ohmic contact layer 22 is disposed corresponding to the source 24 and is located between the source 24 and the active layer 21, and the other ohmic contact layer 22 is disposed corresponding to the drain 25 and is located between the drain 25 and the active layer 21.

[0044] The thin film transistor 20 serves as a switching device in a display panel, the gate 23 of the thin film transistor 20 is connected to a scan line of the display panel, and is connected to a gate scanning circuit (not shown) via the scan line. The source 24 of the thin film transistor 20 is connected to a data line, and is connected to a driving chip (not shown) or a flexible circuit board (not shown) via the data line. The drain 25 of the thin film transistor 20 is connected to a pixel electrode 61, and a voltage is loaded to the pixel electrode 61 through the data line. The substrate common electrode trace is connected to a common electrode (not shown), so that an electric field is formed between the pixel electrode 61 and the common electrode to drive the electrophoretic particles in the electrophoretic fluid to move.

[0045] Further, the first insulating layer 30 has an exposed portion 31 covering a channel region 210 of the thin film transistor 20. The flat layer 40 is provided with a through hole 41 to at least partially expose the exposed portion 31.

[0046] Specifically, in a direction perpendicular to the substrate 10, the part of the active layer 21 of the thin film transistor 20 that does not overlap with the source 24 and the drain 25 of the thin film transistor 20 is defined as the channel region 210. The exposed portion 31 is located between the source 24 and the drain 25 and completely covers the channel region 210. That is, in a direction parallel to the substrate 10, the exposed portion 31 is disposed staggered with respect to the source 24 and the drain 25, respectively. Secondly, the exposed portion 31 covers the channel region 210, and the cross-sectional area of the exposed portion 31 is greater than or equal to the cross-sectional area of the channel region 210. The exposed portion 31 is disposed overlapping with the source 24 or the drain 25, so that the flat layer 40 does not completely shield the source 24 and the drain 25 from light, the cross-sectional area of the flat layer 40 is reduced, and the source 24 and the drain 25 cannot be better protected; secondly, since the metal reflective layer 51 is disposed on the surface of the flat layer 40 away from the substrate 10, the area of the metal reflective layer 51 will also be reduced, which will reduce the utilization rate of the external environmental light irradiating to the array substrate 100.

[0047] In the embodiment, the exposed portion 31 covers the channel region 210, and the cross-sectional area of the exposed portion 31 is greater than that of the channel region 210, facilitating the subsequent arrangement of the through hole 41 to avoid the flat layer 40 from shielding the channel region 210, thereby affecting the performance of the thin film transistor 20.

[0048] The orthographic projection of the through hole 41 on the exposed portion 31 is located in the exposed portion 31. That is, the maximum cross-sectional area of the through hole 41 in the direction parallel to the substrate 10 is less than or equal to the cross-sectional area of the exposed portion 31. In this design, the flat layer 40 above the channel region 210 can make the area of the metal reflective layer 51 as large as possible without affecting the performance of the thin film transistor 20, which can reflect more ambient light and improve the utilization of ambient light, effectively improving the display effect of the display panel.

[0049] The through hole 41 has a first aperture 411 and a second aperture 412 arranged opposite in the direction perpendicular to the substrate 10. The first aperture 411 is defined at the end of the through hole 41 away from the substrate 10, and the second aperture 412 is defined at the end of the through hole 41 close to the substrate 10. The through hole 41 can be a rectangular hole, a cylindrical hole, or a tapered hole, or other irregular structures, which are not limited here and can be selected according to actual needs.

[0050] When the cross-sectional area of the first aperture 411 is equal to that of the second aperture 412, the through hole 41 is a straight hole, and the cross-sectional area of the through hole 41 does not change in the direction toward the substrate 10. When the cross-sectional area of the first aperture 411 is greater than that of the second aperture 412, the through hole 41 is a tapered hole, and the cross-sectional area of the through hole 41 gradually decreases in the direction toward the substrate 10.

[0051] In the embodiment, the through hole 41 is a tapered hole, which facilitates the preparation of the through hole 41 and the subsequent preparation of the conductive layer 70. The cross-sectional area of the first aperture 411 is greater than that of the second aperture 412. The orthographic projection of the first aperture 411 on the exposed portion 31 is located in the exposed portion 31.

[0052] Furthermore, the through hole 41 is provided with a conductive layer 70 electrically connected to the gate 23 of the thin film transistor 20. The conductive layer 70 is insulated from the pixel electrode 61 and the metal reflective layer 51. The conductive layer 70 can be connected to the gate 23 through a via hole lead, or can be electrically connected in other ways, which are not limited here and can be selected according to actual needs.

[0053] Specifically, the conductive layer 70 is located at and covers the second aperture 412 of the via hole 41. The flat layer 40 has a height such that the first aperture 411 and the second aperture 412 have a height difference. The conductive layer 70 is located at the second aperture 412 of the via hole 41, and the thickness of the conductive layer 70 is less than half of the thickness of the flat layer 40, and the first aperture 411 is arranged close to the pixel electrode 61 and the metal reflective layer 51, so that the conductive layer 70 can be arranged to be insulated from the pixel electrode 61 and the metal reflective layer 51 respectively, and the structural design is simple. Here, the height of the flat layer 40 is not limited and can be selected according to actual needs. It should be understood that the cross-sectional area of the conductive layer 70 can also be smaller than the area of the second aperture 412, that is, the conductive layer 70 can also not completely cover the second aperture 412.

[0054] The orthographic projection of the second aperture 412 on the active layer 21 at least partially overlaps the channel region 210, so as to ensure that the conductive layer 70 can at least partially overlap the channel region 210 in the direction perpendicular to the substrate 10.

[0055] The conductive layer 70 is electrically connected to the gate 23, so that the thin film transistor 20 can be changed from a bottom gate structure to a dual-gate structure. Through the dual-gate structure, the stability of the thin film transistor 20 can be improved, the electron mobility of the thin film transistor 20 can be improved, and a higher on-state current can be obtained. At the same time, when ensuring the same on-state current, the width of the thin film transistor 20 can be reduced, thereby increasing the storage capacitance and improving the resolution of the display panel.

[0056] Further, the conductive layer 70 includes a metal light shielding layer 71 and / or a transparent conductive layer 72 (as shown in FIG. 2B), and covers the exposed part 31. Figure 2

[0057] In an embodiment, the conductive layer 70 includes the metal light shielding layer 71, and the metal light shielding layer 71 is connected to the gate 23 to form a dual-gate structure. The metal light shielding layer 71 covers the channel region 210, so as to avoid that the channel region 210 is affected by light to affect the performance of the thin film transistor 20. The material of the metal light shielding layer 71 can be the same as or different from the material of the metal conductive layer 50, which is not limited here and can be selected according to actual needs.

[0058] In another embodiment, the conductive layer 70 includes the transparent conductive layer 72, and the transparent conductive layer 72 is connected to the gate 23 to form a dual-gate structure. The material of the transparent conductive layer 72 can be the same as or different from the material of the transparent electrode layer 60, which is not limited here and can be selected according to actual needs.

[0059] ​In another embodiment, the conductive layer 70 includes a metal light shielding layer 71 and a transparent conductive layer 72. The transparent conductive layer 72 is disposed on the side of the metal light shielding layer 71 away from the substrate 10 and covers the metal light shielding layer 71 to protect the metal light shielding layer 71. The metal light shielding layer 71 is connected to the gate 23, and the metal light shielding layer 71 is in contact with the transparent conductive layer 72, so that the metal light shielding layer 71 and the transparent conductive layer 72 together form another gate 23 of the dual-gate structure.

[0060] It should be understood that in other embodiments, the transparent conductive layer 72 can also not completely cover the metal light shielding layer 71. When the conductive layer 70 includes the metal light shielding layer 71 and the transparent conductive layer 72, the transparent conductive layer 72 can be connected to the gate 23, or the metal light shielding layer 71 and the transparent conductive layer 72 can be connected to the gate 23 respectively.

[0061] In an embodiment, the array substrate 100 further includes a second insulating layer 80 disposed in the via hole 41 and covering the conductive layer 70 to insulate and protect the conductive layer 70. The material of the second insulating layer 80 is different from that of the planarization layer 40, and the second insulating layer 80 is an inorganic insulating layer. The thickness of the second insulating layer 80 is less than that of the planarization layer 40, and the height of the surface of the second insulating layer 80 away from the substrate 10 is less than that of the first aperture 411, so as to protect the performance of the thin film transistor 20 from being affected. The material of the second insulating layer 80 can be the same as or different from that of the first insulating layer 30, which is not limited here and can be selected according to actual needs.

[0062] In the embodiment, the conductive layer 70 includes the metal light shielding layer 71, which is formed on the metal conductive layer 50 and connected to the gate 23. The metal light shielding layer 71 completely covers the second aperture 412, and the orthographic projection of the metal light shielding layer 71 on the active layer 21 is located in the channel region 210. The metal light shielding layer 71 and the metal reflective layer 51 are patterned by the same metal conductive layer 50, which can simplify the preparation process. In addition, the metal light shielding layer 71 can also play a light shielding role to protect the channel region 210 of the thin film transistor 20 from light.

[0063] Please refer to Figure 1 and Figure 2 , Figure 2 is a structural schematic diagram of the second embodiment of the array substrate provided in the present application.

[0064] The second embodiment of the array substrate 100 provided in the present application is basically the same as the first embodiment of the array substrate 100 provided in the present application, and the difference lies in that the conductive layer 70 includes the transparent conductive layer 72.

[0065] In the embodiment, the conductive layer 70 includes a transparent conductive layer 72, which is formed on the transparent electrode layer 60 and connected with the gate electrode 23. The transparent conductive layer 72 completely covers the second aperture 412, and the orthogonal projection of the transparent conductive layer 72 on the active layer 21 is located in the channel region 210. The transparent conductive layer 72 is patterned with the same transparent electrode layer 60 as the pixel electrode 61, which can simplify the manufacturing process.

[0066] Referring to Figure 1 and Figure 3 , Figure 3 is a structural schematic diagram of the third embodiment of the array substrate provided in the application.

[0067] The third embodiment of the array substrate 100 provided in the application has substantially the same structure as the first embodiment of the array substrate 100 provided in the application, except that the conductive layer 70 includes the metal light shielding layer 71 and the transparent conductive layer 72.

[0068] In the embodiment, the conductive layer 70 includes the metal light shielding layer 71 and the transparent conductive layer 72, the metal light shielding layer 71 is formed on the metal conductive layer 50, and the transparent conductive layer 72 is formed on the transparent electrode layer 60. This design can simplify the manufacturing process.

[0069] Referring to Figure 1 and Figure 4 , Figure 4 is a structural schematic diagram of the fourth embodiment of the array substrate provided in the application.

[0070] The fourth embodiment of the array substrate 100 provided in the application has substantially the same structure as the first embodiment of the array substrate 100 provided in the application, except that the array substrate 100 further includes a second insulating layer 80.

[0071] In the embodiment, the conductive layer 70 includes the metal light shielding layer 71, which is formed on the metal conductive layer 50. The second insulating layer 80 is arranged in the through hole 41 and located on the side of the metal light shielding layer 71 away from the substrate 10. The second insulating layer 80 covers the metal light shielding layer 71 to insulate and protect the metal light shielding layer 71. The material of the second insulating layer 80 is the same as that of the first insulating layer 30, and the thickness of the second insulating layer 80 is the same as that of the first insulating layer 30.

[0072] Referring to Figures 1 to 6 , Figure 5 is a structural schematic diagram of the fifth embodiment of the array substrate provided in the application, Figure 6 is a structural schematic diagram of the sixth embodiment of the array substrate provided in the application.

[0073] In other embodiments, the conductive layer 70 can include a transparent conductive layer 72 formed on the transparent electrode layer 60 and connected with the gate 23. The second insulating layer 80 is arranged in the through hole 41 and located on the side of the transparent conductive layer 72 away from the substrate 10 and covers the transparent conductive layer 72 to protect the transparent conductive layer 72. Alternatively, the conductive layer 70 includes a metal light shielding layer 71 and a transparent conductive layer 72. The transparent conductive layer 72 is arranged on the side of the metal light shielding layer 71 away from the substrate 10 and covers the metal light shielding layer 71 to protect the metal light shielding layer 71. The metal light shielding layer 71 is connected with the gate 23 and is in contact with the transparent conductive layer 72. The metal light shielding layer 71 is formed on the metal conductive layer 50 and the transparent conductive layer 72 is formed on the transparent electrode layer 60. The second insulating layer 80 is arranged in the through hole 41 and located on the side of the transparent conductive layer 72 away from the substrate 10 and covers the transparent conductive layer 72 to insulate and protect the conductive layer 70.

[0074] The application provides an array substrate 100, which includes a substrate 10, a thin film transistor 20, a first insulating layer 30, a planar layer 40, a metal conductive layer 50 and a transparent electrode layer 60 formed on one side of the substrate 10 in sequence; the first insulating layer 30 and the planar layer 40 both cover the thin film transistor 20; the metal conductive layer 50 forms a metal reflection layer 51; the transparent electrode layer 60 forms a pixel electrode 61; wherein the first insulating layer 30 has an exposed part 31 covering a channel region 210 of the thin film transistor 20; the planar layer 40 is provided with a through hole 41 to at least partially expose the exposed part 31; the through hole 41 is provided with a conductive layer 70 electrically connected with a gate 23 of the thin film transistor 20, the conductive layer 70 includes a metal light shielding layer 71 and / or a transparent conductive layer 72 and covers the exposed part 31. The planar layer 40 above the channel region 210 is processed by hole digging to avoid the planar layer 40 from shielding the channel region 210 to affect the performance of the thin film transistor 20, thereby avoiding the tailing phenomenon; meanwhile, the conductive layer 70 connected with the gate 23 is arranged above the channel region 210 to form a double-gate 23 structure, thereby improving the performance of the thin film transistor 20.

[0075] The application also provides a display panel applied to an electrophoretic display device. The display panel includes the array substrate 100 described above. The display panel can be an electronic paper (E-paper).

[0076] The above is only the implementation of the application, and does not limit the patent protection scope of the application. Any equivalent structure or equivalent process transformation using the content of the specification and drawings, or direct or indirect application in other related technical fields, is also included in the patent protection scope of the application.

Claims

1. An array substrate, comprising: a substrate and, sequentially formed on one side of the substrate, a thin film transistor, a first insulating layer, a planarization layer, a metal conductive layer, and a transparent electrode layer; the first insulating layer and the planarization layer both cover the thin film transistor; the metal conductive layer forms a metal reflective layer; and the transparent electrode layer forms a pixel electrode; characterized in that the first insulating layer has an exposed portion covering a channel region of the thin film transistor; the planarization layer is provided with a via hole to at least partially expose the exposed portion; and the via hole is provided with a conductive layer electrically connected to a gate electrode of the thin film transistor, the conductive layer comprising a metal light shielding layer and / or a transparent conductive layer and covering the exposed portion.

2. The array substrate of claim 1, wherein, In a direction perpendicular to the substrate, a portion of the active layer of the thin film transistor that does not overlap with a source electrode and a drain electrode of the thin film transistor defines a channel region; and the exposed portion is located between the source electrode and the drain electrode and completely covers the channel region.

3. The array substrate of claim 2, wherein, The via hole is of a necked structure, and in a direction towards the substrate, the cross-sectional area of the via hole gradually decreases; the via hole has oppositely arranged first and second apertures, the cross-sectional area of the first aperture being larger than that of the second aperture; and a normal projection of the first aperture on the exposed portion is located within the exposed portion.

4. The array substrate of claim 3, wherein, The conductive layer is located at the second aperture of the via hole and covers the second aperture.

5. The array substrate of claim 1, wherein, The thin film transistor is of a bottom-gate structure.

6. The array substrate of claim 5, wherein, The metal reflective layer is arranged on a side surface of the planarization layer away from the substrate, and the pixel electrode covers the metal reflective layer.

7. The array substrate of claim 6, wherein, The conductive layer is arranged to be insulated from the pixel electrode and from the metal reflective layer.

8. The array substrate of claim 6, wherein, The conductive layer comprises the metal light shielding layer, which is formed on the metal conductive layer and electrically connected to the gate electrode; or, the conductive layer comprises the transparent conductive layer, which is formed on the transparent electrode layer and electrically connected to the gate electrode; or, the conductive layer comprises the metal light shielding layer and the transparent conductive layer, the transparent conductive layer being arranged on a side of the metal light shielding layer away from the substrate and covering the metal light shielding layer.

9. The array substrate of claim 1, wherein, Further comprising a second insulating layer arranged in the via hole and covering the conductive layer.

10. A display panel, characterized by, The display panel comprises the array substrate of any one of claims 1 to 9.

Images