Adaptive power regulation circuit, computing system and electronic device

Abstract

Provided are an adaptive power regulation circuit, computing system, and electronic device. The circuit includes: multiple power sensing units for sensing the power consumed by corresponding input power rails on a processor system board; a summer for summing the power to obtain a total power; multiple first conversion units and second conversion units, each first conversion unit for converting power into a first bit sequence, and each second conversion unit for converting the total power into a second bit sequence; and a logic operation unit for performing a logical OR operation on the first and second bit sequences to generate a final bit sequence, which is transmitted to a processor, and the processor adaptively performs power regulation based on the final bit sequence. The present invention uses a hardware circuit to adaptively adjust the clock frequency, enabling rapid response to power changes, resulting in better performance, saving cost and PCB area, helping to optimize the input power distribution network, and being capable of being used simultaneously on multiple processing unit circuit boards.

Description

Technical Field

[0001] The present invention relates to the field of computers, and more particularly, to an adaptive power regulation circuit, a computing system, and an electronic device. Background Art

[0002] Individual processing units in a computing system, such as the CPU and GPU, consume significantly different amounts of power when running the same or different applications due to differences in parameters such as operating speed, leakage current, and load. To ensure that different processing units achieve the highest possible performance under various conditions, one solution is to use dynamic overclocking (GPU boost) and power capping in the computing system to ensure that the processing units can run at higher clock frequencies without exceeding their power or thermal limits, thereby ensuring safer operation.

[0003] There are two existing solutions for implementing dynamic overclocking and power capping methods: one is to first sense the power of each power rail on the processing system board and then control the power through I 2 The other method is to sense the voltage and current of each power rail on the processing system board, and feed back analog signals such as voltage and current to the processing unit, which is further processed by the analog-to-digital converter (ADC) in the processing unit.

[0004] The above two solutions have at least the following disadvantages:

[0005] 1. The sensing devices used in the above two solutions cannot be shared between different processing units. Therefore, each processing unit needs to be equipped with a sensing device, which increases the cost and causes waste of PCB (printed circuit board) area.

[0006] 2. Both of the above solutions require low-level software to calculate the clock frequency, which depends on the real-time core power value. Therefore, both solutions require additional current sensing circuits to sense the real-time power value, which increases cost and wastes PCB area. In addition, some power rails need to be monitored separately. The power topology always splits a single power rail into two or more power rails for power sensing, so the input power distribution network is not optimal.

[0007] 3. Both of the above solutions use software-based calculations to increase or decrease clock speeds. This calculation assumes the workload at the current time is the same as the workload at the previous time. In reality, however, the workloads are often different. This requires several iterations, making power capping ineffective.

[0008] Therefore, a new type of adaptive power regulation circuit, computing system and electronic device is needed to solve the above problems and other problems. Summary of the Invention

[0009] The present invention is proposed to solve the above-mentioned problems. According to one aspect of the present invention, an adaptive power regulation circuit is provided, the circuit comprising: a plurality of power sensing units, each power sensing unit being configured to sense the power consumed by a corresponding input power rail among a plurality of input power rails on a processor system board; a summer being configured to sum the power consumed by each of the sensed input power rails to obtain the total power consumed by the plurality of input power rails; a plurality of first conversion units and second conversion units, each first conversion unit being configured to convert the power consumed by the corresponding input power rail sensed into a first bit sequence, and the second conversion unit being configured to convert the total power consumed by the plurality of input power rails into a second bit sequence; and a logic operation unit being configured to perform a logical OR operation on the first bit sequence and the second bit sequence to generate a final bit sequence, wherein the final bit sequence is transmitted to a processor on the processor system board, and the processor adaptively performs power regulation based on the final bit sequence.

[0010] In one embodiment, the power sensing unit includes a voltage and current monitor and a multiplier. The voltage and current monitor is used to sense the voltage and current on a corresponding input power rail among the plurality of input power rails. The multiplier is used to convert the sensed voltage and current into power consumed by the corresponding input power rail.

[0011] In one embodiment, each first conversion unit converts the power consumed by the corresponding input power rail into the first bit sequence by comparing the power consumed by the corresponding input power rail with a corresponding target power for the input power rail in a step-by-step manner.

[0012] In one embodiment, the second conversion unit converts the total power into the second bit sequence by comparing the total power consumed by the multiple input power rails with the total target power in a step-by-step manner.

[0013] In one embodiment, the circuit further comprises: a clock control unit, configured to generate a bit sequence clock signal, wherein the bit sequence clock signal is configured to control the transmission of the final bit sequence to the processor.

[0014] In one embodiment, the circuit further includes: a parallel-to-serial conversion unit, configured to perform parallel-to-serial conversion on the final bit sequence before the final bit sequence is transmitted to the processor, wherein the converted final bit sequence is transmitted to the processor, and the processor adaptively performs power regulation based on the converted final bit sequence.

[0015] In one embodiment, the clock control unit is further configured to generate a packet clock signal, which is configured to control the packetization of the converted final bit sequence into a plurality of data packets, so that the converted final bit sequence is transmitted to the processor in the form of data packets.

[0016] In one embodiment, the first conversion unit and the second conversion unit both include multi-stage comparators.

[0017] In one embodiment, the first conversion unit and the second conversion unit each include an analog-to-digital converter.

[0018] In one embodiment, the processor comprises a graphics processing unit.

[0019] According to another aspect of the present invention, a computing system is provided, comprising: a processor; and an adaptive power regulation circuit, comprising: a plurality of power sensing units, each power sensing unit configured to sense power consumed by a corresponding input power rail among a plurality of input power rails on a processor system board; a summer configured to sum the sensed power consumed by each input power rail to obtain a total power consumed by the plurality of input power rails; a plurality of first conversion units and second conversion units, each first conversion unit configured to convert the sensed power consumed by the corresponding input power rail into a first bit sequence, and each second conversion unit configured to convert the total power consumed by the plurality of input power rails into a second bit sequence; and a logic operation unit configured to perform a logical OR operation on the first bit sequence and the second bit sequence to generate a final bit sequence, wherein the final bit sequence is transmitted to the processor on the processor system board, and the processor adaptively performs power regulation based on the final bit sequence.

[0020] In one embodiment, the power sensing unit includes a voltage and current monitor and a multiplier. The voltage and current monitor is used to sense the voltage and current on a corresponding input power rail among the plurality of input power rails. The multiplier is used to convert the sensed voltage and current into power consumed by the corresponding input power rail.

[0021] In one embodiment, each first conversion unit converts the power consumed by the corresponding input power rail into the first bit sequence by comparing the power consumed by the corresponding input power rail with a corresponding target power for the input power rail in a step-by-step manner.

[0022] In one embodiment, the second conversion unit converts the total power into the second bit sequence by comparing the total power consumed by the multiple input power rails with the total target power in a step-by-step manner.

[0023] In one embodiment, the adaptive power regulation circuit further comprises: a clock control unit, configured to generate a bit sequence clock signal, wherein the bit sequence clock signal is used to control the transmission of the final bit sequence to the processor.

[0024] In one embodiment, the adaptive power regulation circuit further includes: a parallel-to-serial conversion unit, configured to perform parallel-to-serial conversion on the final bit sequence before the final bit sequence is transmitted to the processor, the converted final bit sequence being transmitted to the processor, and the processor adaptively performing power regulation based on the converted final bit sequence.

[0025] In one embodiment, the clock control unit is further configured to generate a packet clock signal, which is configured to control the packetization of the converted final bit sequence into a plurality of data packets, so that the converted final bit sequence is transmitted to the processor in the form of data packets.

[0026] In one embodiment, the first conversion unit and the second conversion unit both include multi-stage comparators.

[0027] In one embodiment, the first conversion unit and the second conversion unit each include an analog-to-digital converter.

[0028] In one embodiment, the processor comprises a graphics processing unit.

[0029] According to yet another aspect of the present invention, an electronic device is provided, comprising the adaptive power regulation circuit as described above.

[0030] The adaptive power regulation circuit, computing system, and electronic device of the embodiments of the present invention use hardware circuits to adaptively adjust clock frequency without the need for additional current sensing devices or splitting a single power rail. They can quickly respond to power changes, thereby improving clock boosting and power capping performance, saving costs and PCB area, helping to optimize the input power distribution network, and can be used simultaneously on multiple processing unit circuit boards. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other objects, features, and advantages of the present invention will become more apparent through a more detailed description of the embodiments of the present invention with reference to the accompanying drawings. The accompanying drawings are provided to provide a further understanding of the embodiments of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and are not intended to limit the present invention. In the drawings, the same reference numerals generally represent the same components or steps.

[0032] Figure 1 A schematic structural diagram of an exemplary adaptive power regulation circuit according to an embodiment of the present invention is shown.

[0033] Figure 2 FIG. 4 shows a table of a final bit sequence obtained through OR operation according to an embodiment of the present invention.

[0034] Figure 3 A schematic diagram showing output signals of three pins of an adaptive power regulation circuit according to an embodiment of the present invention is shown.

[0035] Figure 4 FIG. 4 shows a bit sequence received by a processor according to an embodiment of the present invention.

[0036] Figure 5 FIG. 4 shows a bit sequence received by a processor according to another embodiment of the present invention.

[0037] Figure 6 A schematic structural block diagram of a computing system according to an embodiment of the present invention is shown.

[0038] Figure 7 A block diagram of an example electronic device suitable for implementing at least some embodiments of the present disclosure is shown.

[0039] Figure 8 Example operating environments are shown in which electronic devices may operate. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solutions and advantages of the present invention more apparent, exemplary embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments of the present invention, and it should be understood that the present invention is not limited to the exemplary embodiments described herein. Based on the embodiments of the present invention described in the present invention, all other embodiments obtained by those skilled in the art without creative work should fall within the scope of protection of the present invention.

[0041] Existing solutions for implementing dynamic overclocking and power capping methods are based on software iterative calculations and have the above-mentioned shortcomings. To address the above-mentioned problems, an embodiment of the present invention provides an adaptive power regulation circuit, comprising: a plurality of power sensing units, each of which is configured to sense the power consumed by a corresponding input power rail among a plurality of input power rails in a processor; a summer configured to sum the sensed power consumed by each input power rail to obtain the total power consumed by the plurality of input power rails; a plurality of first conversion units and second conversion units, each of which is configured to convert the sensed power consumed by the corresponding input power rail into a first bit sequence, and the second conversion unit is configured to convert the total power consumed by the plurality of input power rails into a second bit sequence; and a logic operation unit configured to perform a logical OR operation on the first bit sequence and the second bit sequence to generate a final bit sequence, wherein the final bit sequence is transmitted to the processor, and the processor adaptively performs power regulation based on the final bit sequence.

[0042] The adaptive power regulation circuit of an embodiment of the present invention uses a hardware circuit to adaptively adjust the clock frequency. It does not require an additional current sensing device or the splitting of a single power rail. It can respond quickly to power changes, thereby improving the performance of clock boosting and power capping, saving costs and PCB area, helping to optimize the input power distribution network, and can be used simultaneously on multiple processing unit circuit boards.

[0043] The solution of the present invention is described in detail below with reference to specific embodiments.

[0044] In one embodiment of the present invention, an adaptive power regulation circuit is provided. Figure 1 , Figure 1 FIG. 1 shows a schematic structural diagram of an exemplary adaptive power regulation circuit 10 according to an embodiment. Figure 1 As shown, the adaptive power regulation circuit 10 may include a plurality of power sensing units 20, a summer 30, a plurality of first conversion units 40 and second conversion units 50, and a logic operation unit (not shown).

[0045] Each power sensing unit 20 is used to sense the power consumed by a corresponding input power rail among multiple input power rails on the processor system board. Therefore, a number of power sensing units corresponding to the number of input power rails may be provided, each power sensing unit sensing the power consumed by a corresponding input power rail.

[0046] Exemplarily, the processor system board in this article is used to refer to various system boards that consume power, such as a central processing unit (CPU) system board, a graphics processing unit (GPU) system board, etc., and the present invention is not limited to this.

[0047] The power consumed by the input power rail can be obtained by measuring the voltage and current. For example, the power sensing unit 20 may include a voltage and current monitor 22 and a multiplier 24. The voltage and current monitor 22 is configured to sense the voltage and current on a corresponding input power rail among the multiple input power rails, and the multiplier 24 is configured to convert the sensed voltage and current into the power consumed by the corresponding input power rail.

[0048] In one embodiment, the voltage and current monitor 22 can be any device, equipment, chip, etc. known in the art that can monitor voltage and current, such as a power detector, a voltage and current sampling device, etc., and the present invention is not limited to this.

[0049] The summer 30 is configured to sum the sensed powers consumed by the various input power rails to obtain the total power consumed by the multiple input power rails.

[0050] Each of the plurality of first conversion units 40 is configured to convert the sensed power consumed by the corresponding input power rail into a first bit sequence. A plurality of first conversion units may be provided corresponding to the number of input power rails, and each first conversion unit is connected to a corresponding power sensing unit 20 to convert the power consumed by the corresponding input power rail into a first bit sequence.

[0051] In one embodiment, the first conversion unit 40 may convert the power of the corresponding input power rail into a first bit sequence by comparing the power consumed by the corresponding input power rail with the corresponding target power for the input power rail in a stepwise manner. In one embodiment, the first bit sequence may be a binary bit sequence consisting of 0s and 1s.

[0052] In one embodiment, the first conversion unit 40 may include a multi-stage comparator (comparator ladder), such as Figure 1 In another embodiment, the first conversion unit 40 may include an analog-to-digital converter (ADC).

[0053] In one embodiment, the corresponding target power for the input power rail can be obtained by I 2 C port and stored in the register.

[0054] The second conversion unit 50 may be connected to the summer 30 and configured to convert the total power consumed by the plurality of input power rails into a second bit sequence. In one embodiment, the second bit sequence may be a binary bit sequence consisting of 0s and 1s.

[0055] In one embodiment, the second conversion unit 50 converts the total power into a second bit sequence by comparing the total power consumed by the plurality of input power rails with the total target power in a step-by-step manner.

[0056] In one embodiment, the second conversion unit 50 may include a multi-stage comparator, such as Figure 1 In another embodiment, the second conversion unit 50 may include an analog-to-digital converter (ADC).

[0057] In one embodiment, the total target power can be calculated by I 2 C port and stored in the register.

[0058] See also Figure 1 For example, in a multi-stage comparator, resistors equal in number to the number of bits in the bit sequence can be connected in series to form a resistor ladder. Each resistor divides the sensed power into multiple steps, which are then compared with the target power. The corresponding bits are output based on the comparison results, and the bits output by each comparator form a bit sequence. The target power can be set at the middle of the resistor ladder.

[0059] The first and second bit sequences can be represented by [dm,…,d1,d0,u0,u1,…,un], where dx represents the high-order bit and ux represents the low-order bit. When all dx bits in the bit sequence are 0 and all ux bits are 1, the corresponding power is at the target power. If any low-order ux bit in the bit sequence is 0, the corresponding power is lower than the target power. In this case, the clock frequency should be increased to increase the power so that the real-time power equals the target power. If any high-order dx bit in the bit sequence is 1, the corresponding power is higher than the target power. In this case, the clock frequency should be decreased to reduce the power so that the real-time power equals the target power.

[0060] The logic operation unit is used to perform a logical OR operation on the first bit sequence and the second bit sequence to generate a final bit sequence. This final bit sequence can be directly transmitted to the processor, which then adaptively performs power regulation based on this final bit sequence. This triggers power regulation if the power consumed by any input power rail, or the total power consumed by all power rails, exceeds its target power, thereby improving processor performance.

[0061] refer to Figure 2 , Figure 2 FIG. 4 shows a table of obtaining a final bit sequence through OR operation according to an embodiment of the present invention. Figure 2 As shown, taking three power rails as an example, the dm bits of the three powers of the three power rails are ORed with the dm bit of the total power to obtain the dm bit of the final bit sequence, and the other bits of the final bit sequence are obtained similarly. Figure 2The final bit sequence obtained as shown in is [0, 0, 0, 0, 1, 1, 1, 1, 1, 1], that is, the d0 bit is 1, indicating that the real-time power is higher than the target power. At this time, the clock frequency should be reduced to reduce the real-time power so that the real-time power is equal to the target power.

[0062] In one embodiment, the adaptive power regulation circuit 10 may further include a clock control unit 60 for generating a bit sequence clock signal, where the bit sequence clock signal is used to control the transmission of the final bit sequence to the processor.

[0063] In order to reduce the number of pins of the processor to receive the final bit sequence, in one embodiment, the adaptive power regulation circuit 10 may also include a parallel-serial conversion unit 70, which is used to perform parallel-to-serial conversion on the final bit sequence before the final bit sequence is transmitted to the processor, convert the generated parallel bit sequence into a serial bit sequence, and then transmit the converted final bit sequence to the processor, and the processor adaptively performs power regulation based on the converted final bit sequence.

[0064] In one embodiment, the logic operation unit may be included in the parallel-serial conversion unit 70 or may be a separate device, which is not limited in the present invention.

[0065] In one embodiment, the clock control unit 60 is also used to generate a packet clock signal, which is used to control the packaging of the converted final bit sequence into multiple data packets, and then transmit the converted final bit sequence to the processor in the form of data packets. The processor adaptively performs power regulation based on the converted final bit sequence in the form of data packets. The processor will use the bit sequence clock signal and the packet clock signal to ensure that the bit sequence is received correctly. Therefore, the connection between the adaptive power regulation circuit 10 and the processor only requires 3 pins, namely the power bit sequence pin Pin1, the bit sequence clock pin Pin2 and the packet clock pin Pin3, wherein the power bit sequence pin Pin1 is used to output the final bit sequence to the processor, the bit sequence clock pin Pin2 is used to output the bit sequence clock signal to the processor, and the packet clock pin Pin3 is used to output the packet clock signal to the processor. Reference Figure 3 , Figure 3 A schematic diagram showing output signals of three pins of an adaptive power regulation circuit according to an embodiment of the present invention is shown.

[0066] Since the bit sequence is generated by comparing the power with the target power in a step-by-step manner, the amount of adjusting the clock frequency can be determined based on the pattern of the bit sequence. Figure 4 , Figure 4 FIG. 4 shows a bit sequence received by a processor according to an embodiment of the present invention. Figure 4As shown, the low bit ux contains 0, indicating that the power is lower than the target power. At this time, the clock frequency should be increased to improve the power. In addition, the two low bits u0 and u1 are both 0, so the clock frequency should be increased by 2 steps. Figure 5 , Figure 5 FIG. 2 shows a bit sequence received by a processor according to another embodiment of the present invention. Figure 5 As shown, the high bit dx contains 1, indicating that the power is higher than the target power. In this case, the clock frequency should be reduced to reduce power. And only one low bit d0 is 1, so the clock frequency should be reduced by one step. In other words, the greater the difference between the power and the target power, the more steps the clock frequency should be adjusted.

[0067] The adaptive power regulation circuit of an embodiment of the present invention uses a hardware circuit to adaptively adjust the clock frequency. It does not require an additional current sensing device or the splitting of a single power rail. It can respond quickly to power changes, thereby improving the performance of clock boosting and power capping, saving costs and PCB area, helping to optimize the input power distribution network, and can be used simultaneously on multiple processing unit circuit boards.

[0068] In another embodiment of the present invention, a computing system is provided. Figure 6 , Figure 6 FIG. 6 shows a schematic structural block diagram of a computing system 600 according to an embodiment of the present invention. Figure 6 As shown, computing system 600 may include a processor 610 and an adaptive power regulation circuit 620 .

[0069] The processor 610 may be various power-consuming components, such as a central processing unit (CPU), a graphics processing unit (GPU), etc., and may also be used to refer to a circuit board including the processor, such as a graphics card.

[0070] The adaptive power regulation circuit 620 may be the adaptive power regulation circuit 10 described above. The following only shows the main structure of the adaptive power regulation circuit 620, and for the sake of brevity, the specific details are not repeated here.

[0071] The adaptive power regulation circuit 620 may include a plurality of power sensing units, a summer, a plurality of first conversion units and second conversion units, and a logic operation unit.

[0072] Each power sensing unit is used to sense the power consumed by a corresponding input power rail among multiple input power rails on the processor system board. Therefore, a number of power sensing units corresponding to the number of input power rails may be provided, each power sensing unit sensing the power consumed by a corresponding input power rail.

[0073] The power consumed by the input power rail can be obtained by measuring voltage and current. Exemplarily, the power sensing unit may include a voltage and current monitor and a multiplier. The voltage and current monitor is configured to sense the voltage and current on a corresponding input power rail among the multiple input power rails, and the multiplier is configured to convert the sensed voltage and current into the power consumed by the corresponding input power rail.

[0074] In one embodiment, the voltage and current monitor may be any device, equipment, chip, etc. known in the art that can monitor voltage and current, such as a power detector, a voltage and current sampling device, etc., and the present invention is not limited thereto.

[0075] The summer is configured to sum the sensed powers consumed by the various input power rails to obtain the total powers consumed by the multiple input power rails.

[0076] Each of the plurality of first conversion units is configured to convert the sensed power consumed by the corresponding input power rail into a first bit sequence. A plurality of first conversion units may be provided corresponding to the number of input power rails, and each first conversion unit is connected to a corresponding power sensing unit to convert the power consumed by the corresponding input power rail into the first bit sequence.

[0077] In one embodiment, the first conversion unit may convert the power of the corresponding input power rail into a first bit sequence by comparing the power consumed by the corresponding input power rail with the corresponding target power for the input power rail in a stepwise manner. In one embodiment, the first bit sequence may be a binary bit sequence consisting of 0s and 1s.

[0078] The second conversion unit may be connected to the summer, and configured to convert the total power consumed by the plurality of input power rails into a second bit sequence. In one embodiment, the second bit sequence may be a binary bit sequence consisting of 0s and 1s.

[0079] In one embodiment, the second conversion unit converts the total power into the second bit sequence by comparing the total power consumed by the plurality of input power rails with the total target power in a step-by-step manner.

[0080] In one embodiment, the adaptive power regulation circuit 620 may further include a clock control unit for generating a bit sequence clock signal, where the bit sequence clock signal is used to control the transmission of the final bit sequence to the processor.

[0081] In order to reduce the number of pins of the processor to receive the final bit sequence, in one embodiment, the adaptive power regulation circuit may also include a parallel-to-serial conversion unit for performing parallel-to-serial conversion on the final bit sequence before the final bit sequence is transmitted to the processor, converting the generated parallel bit sequence into a serial bit sequence, and then transmitting the converted final bit sequence to the processor, and the processor adaptively performs power regulation based on the converted final bit sequence.

[0082] In one embodiment, the logic operation unit may be included in the parallel-serial conversion unit, or may be a separate device, which is not limited in the present invention.

[0083] In one embodiment, the clock control unit is further used to generate a packet clock signal, which is used to control the packaging of the converted final bit sequence into multiple data packets, and then transmit the converted final bit sequence to the processor in the form of data packets. The processor adaptively adjusts power based on the converted final bit sequence in the form of data packets.

[0084] Since the bit sequence is generated by comparing the power with the target power in a step-by-step manner, the amount of adjusting the clock frequency can be determined according to the pattern of the bit sequence.

[0085] The computing system of an embodiment of the present invention includes an adaptive power regulation circuit that uses a hardware circuit to adaptively adjust the clock frequency without the need for an additional current sensing device or the splitting of a single power rail. It can quickly respond to power changes, thereby improving the performance of clock boosting and power capping, saving costs and PCB area, helping to optimize the input power distribution network, and can be used simultaneously on multiple processing unit circuit boards.

[0086] This embodiment provides an electronic device. By way of example, the electronic device may include any electronic device known in the art having more than one circuit board, such as a desktop computer, a laptop computer, a tablet computer, a smart home device, a mobile phone, a robot, etc., although the present invention is not limited thereto. The electronic device of this embodiment may include the circuit board according to the embodiment of the present invention described above.

[0087] Now refer to Figure 7 , Figure 77 is a block diagram of an example electronic device 700 suitable for implementing at least some embodiments of the present disclosure. The electronic device 700 may include a bus 702 that directly or indirectly couples the following devices: a memory 704, one or more central processing units (CPUs) 706, one or more graphics processing units (GPUs) 708, a communication interface 710, input / output (I / O) ports 712, input / output (I / O) components 714, a power supply 716, and one or more presentation components 718 (e.g., one or more displays).

[0088] although Figure 7 The various blocks of FIG706 are shown as being connected to each other via bus 702, but this is not intended to be limiting and is provided for clarity. For example, in some embodiments, presentation component 718 (e.g., a display device) may be considered an I / O component 714 (e.g., if the display is a touch screen). As another example, CPU 706 and / or GPU 708 may include memory (e.g., memory 704 may represent a storage device in addition to the memory of GPU 708, CPU 706, and / or other components). In other words, Figure 7 The electronic devices listed are illustrative only. No distinction is made between categories such as "workstations," "servers," "laptops," "desktops," "tablets," "client devices," "mobile devices," "handheld devices," "gaming consoles," "electronic control units (ECUs)," "virtual reality systems," "robotic devices," and / or other device or system types, as all categories are in the Figure 7 considered within the scope of electronic equipment.

[0089] The bus 702 may represent one or more buses, such as an address bus, a data bus, a control bus, or a combination thereof. The bus 702 may include one or more bus types, such as an Industry Standard Architecture (ISA) bus, an Extended Industry Standard Architecture (EISA) bus, a Video Electronics Standard Association (VESA) bus, a Peripheral Component Interconnect (PCI) bus, a Peripheral Component Interconnect Express (PCIe) bus, and / or other types of buses.

[0090] The memory 704 may include any of a variety of computer-readable media. Computer-readable media may be any available media that can be accessed by the electronic device 700. Computer-readable media may include volatile and non-volatile media, as well as removable and non-removable media. For example, and without limitation, computer-readable media may include computer storage media and communication media.

[0091] Computer storage media can include volatile and nonvolatile media and / or removable and non-removable media implemented in any method or technology for storing information, such as computer-readable instructions, data structures, program modules, and / or other data types. For example, memory 704 can store computer-readable instructions (e.g., instructions representing one or more programs and / or one or more program elements, such as an operating system). Computer storage media can include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by the electronic device 700. As used herein, computer storage media does not itself contain signals.

[0092] Communication media may contain computer-readable instructions, data structures, program modules, and / or other data types in a modulated data signal such as a carrier wave or other transport mechanism, and include any information delivery media. The term "modulated data signal" may refer to a signal that has one or more of its characteristics set or changed in such a way as to encode information into the signal. By way of example, and not limitation, communication media may include wired media such as a wired network or a direct wired connection, and wireless media such as acoustic, radio frequency, infrared, and other wireless media. Combinations of any of the above are also intended to be included within the scope of computer-readable media.

[0093] One or more CPUs 706 may be configured to execute computer-readable instructions to control one or more components of the electronic device 700 to perform one or more methods and / or processes described herein. Each of the one or more CPUs 706 may include one or more cores (e.g., one, two, four, eight, twenty-eight, seventy-two, etc.) that are capable of processing multiple software threads simultaneously. The one or more CPUs 706 may include any type of processor, and may include different types of processors, depending on the type of electronic device 700 implemented (e.g., a processor with fewer cores for a mobile device and a processor with more cores for a server). For example, depending on the type of electronic device 700, the processor may be an ARM processor implemented using Reduced Instruction Set Computing (RISC), or an x86 processor implemented using Complex Instruction Set Computing (CISC). In addition to one or more microprocessors or auxiliary coprocessors, such as a math coprocessor, the electronic device 700 may also include one or more CPUs 706.

[0094] The electronic device 700 may use one or more GPUs 708 to render graphics (e.g., 3D graphics). The one or more GPUs 708 may include hundreds or thousands of cores that can process hundreds or thousands of software threads simultaneously. The one or more GPUs 708 may generate pixel data for an output image in response to a rendering command (e.g., a rendering command received from one or more CPUs 706 via a host interface). The one or more GPUs 708 may include graphics memory, such as display memory, for storing pixel data. The display memory may be included as part of the memory 704. The one or more GPUs 708 may include two or more GPUs running in parallel (e.g., by linking). When combined, each GPU 708 may generate pixel data for different parts of an output image or different output images (e.g., a first GPU for a first image and a second GPU for a second image). Each GPU may include its own memory or may share memory with other GPUs.

[0095] In examples where the electronic device 700 does not include one or more GPUs 708, one or more CPUs 706 may be used to render graphics.

[0096] The communication interface 710 may include one or more receivers, transmitters, and / or transceivers that enable the electronic device 700 to communicate with other electronic devices via an electronic communication network (including wired and / or wireless communications). The communication interface 710 may include components and functionality to enable communication via any number of different networks, such as wireless networks (e.g., Wi-Fi, Z-wave, Bluetooth, Bluetooth LE, ZigBee, etc.), wired networks (e.g., communication via Ethernet), low-power wide-area networks (e.g., LoRaWAN, SigFox, etc.), and / or the Internet.

[0097] The I / O ports 712 may enable the electronic device 700 to be logically coupled to other devices, including an I / O component 714, one or more presentation components 718, and / or other components, some of which may be built into (e.g., integrated into) the electronic device 700. Illustrative I / O components 714 include a microphone, a mouse, a keyboard, a joystick, a game pad, a game controller, a satellite dish, a scanner, a printer, a wireless device, and the like. The I / O components 714 may provide a natural user interface (NUI) that processes user-generated air gestures, voice, or other physiological input. In some cases, the input may be transmitted to an appropriate network element for further processing. The NUI may implement voice recognition, stylus recognition, facial recognition, biometric recognition, gesture recognition on and near the screen, air gestures, head and eye tracking, and touch recognition associated with the display of the electronic device 700 (described in more detail below). The electronic device 700 may include a depth camera (e.g., a stereo camera system), an infrared camera system, an RGB camera system, touch screen technology, and combinations thereof for gesture detection and recognition. Additionally, the electronic device 700 may include an accelerometer or gyroscope (e.g., as part of an inertial measurement unit (IMU)) for detecting motion. In some examples, the output of the accelerometer or gyroscope may be used by the electronic device 700 to present immersive augmented reality or virtual reality.

[0098] The power supply 716 may include a hard-wired power supply, a battery power supply, or a combination thereof. The power supply 716 may provide power to the electronic device 700 so that the components of the electronic device 700 can operate.

[0099] The one or more presentation components 718 may include a display (e.g., a monitor, a touch screen, a television screen, a heads-up display (HUD), other display types, or a combination thereof), speakers, and / or other presentation components. The one or more presentation components 718 may receive data from other components (e.g., one or more GPUs 708, one or more CPUs 706, etc.) and output data (e.g., images, video, sound, etc.).

[0100] Sample operating environment

[0101] According to some embodiments of the present disclosure, the electronic device 700 may be Figure 8 is implemented in the example operating environment 800 of .

[0102] In addition to other components not shown, the operating environment 800 includes one or more client devices 820, one or more networks 840, one or more server devices 860, and one or more data stores 850. It should be understood that Figure 8 Operating environment 800 shown in FIG. 8 is an example of a suitable operating environment. Figure 8Each component shown in can be implemented via any type of computing device, such as, for example, a computer system in conjunction with Figure 5 One or more electronic devices 700 described herein. These components can communicate with each other via a network 840, which can be wired, wireless, or both. The network 840 can include multiple networks or a network of networks, but is shown in a simplified form so as not to obscure aspects of the present disclosure. For example, the network 840 can include one or more wide area networks (WANs), one or more local area networks (LANs), one or more public networks such as the Internet, and / or one or more private networks. In the case where the network 840 includes a wireless telecommunications network, components such as base stations, communication towers, or even access points (and other components) can provide wireless connections.

[0103] It should be understood that within the scope of the present disclosure, any number of client devices 820, server devices 860, and data stores 850 may be employed within operating environment 800. Each may be configured as a single device or as multiple devices cooperating in a distributed environment.

[0104] One or more client devices 820 may include the Figure 5 At least some of the components, features, and functionality of the described example electronic device 700. By way of example and not limitation, the client device 820 may be embodied as a personal computer (PC), a laptop computer, a mobile device, a smartphone, a tablet computer, a smartwatch, a wearable computer, a personal digital assistant (PDA), an MP3 player, a global positioning system (GPS) or device, a video player, a handheld communication device, a gaming device or system, an entertainment system, an in-vehicle computer system, an embedded system controller, a remote control, an appliance, a consumer electronic device, a workstation, any combination of these depicted devices, or any other suitable device.

[0105] One or more client devices 820 may include one or more processors and one or more computer-readable media. The computer-readable media may include computer-readable instructions that can be executed by one or more processors. These instructions, when executed by one or more processors, may cause one or more processors to perform desired functions.

[0106] One or more server devices 860 may also include one or more processors and one or more computer-readable media. The computer-readable media may include computer-readable instructions that can be executed by one or more processors. These instructions, when executed by one or more processors, may cause one or more processors to perform desired functions.

[0107] The one or more data stores 850 may include one or more computer-readable media. The computer-readable media may include computer-readable instructions that can be executed by one or more processors. These instructions, when executed by one or more processors, may cause the one or more processors to perform desired functions. The one or more data stores 850 (or computer data storage devices) are depicted as a single component, but may be embodied as one or more data stores (e.g., databases) and may be at least partially located in the cloud.

[0108] Although depicted as being external to the one or more server devices 860 and the one or more client devices 820, the one or more data stores 850 may be implemented at least in part on any combination of the one or more server devices 860 and / or the one or more client devices 820 (e.g., implemented as Figure 5 Memory 504). For example, some information may be stored on one or more client devices 820, and other and / or duplicate information may be stored externally (e.g., on one or more server devices 860). Thus, it should be appreciated that the information in the one or more data stores 850 may be distributed across one or more data stores for storage (which may be hosted externally) in any suitable manner. For example, the one or more data stores 850 may include at least some of the one or more computer-readable media of the one or more server devices 860 and / or at least some of the one or more computer-readable media of the one or more client devices 820.

[0109] Although example embodiments have been described herein with reference to the accompanying drawings, it should be understood that the above example embodiments are merely illustrative and are not intended to limit the scope of the present invention. Various changes and modifications may be made therein by those skilled in the art without departing from the scope and spirit of the present invention. All such changes and modifications are intended to be included within the scope of the present invention as claimed in the appended claims.

[0110] In the description provided herein, numerous specific details are described. However, it is understood that embodiments of the present invention may be practiced without these specific details. In some instances, well-known methods, structures, and techniques are not shown in detail so as not to obscure the understanding of this description.

[0111] Similarly, it should be understood that in order to streamline the present invention and aid in understanding one or more of the various inventive aspects, in the description of exemplary embodiments of the present invention, the various features of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof. However, this approach to the present invention should not be interpreted as reflecting the intention that the claimed invention requires more features than those explicitly recited in each claim. More precisely, as reflected in the corresponding claims, the inventive point is that the corresponding technical problem can be solved with fewer features than all the features of a single disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into the detailed description, with each claim itself serving as a separate embodiment of the present invention.

[0112] It will be understood by those skilled in the art that, except where mutually exclusive, all features disclosed in this specification (including the accompanying claims, abstract, and drawings) and all processes or units of any method or apparatus disclosed herein may be combined in any combination. Unless expressly stated otherwise, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) may be replaced by an alternative feature providing the same, equivalent, or similar purpose.

[0113] Furthermore, those skilled in the art will appreciate that although some embodiments described herein include certain features included in other embodiments but not other features, combinations of features from different embodiments are intended to be within the scope of the present invention and to form different embodiments. For example, in the claims, any of the claimed embodiments may be used in any combination.

[0114] It should be noted that the above embodiments illustrate rather than limit the invention, and that those skilled in the art may devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between brackets should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The present invention may be implemented by means of hardware comprising several different elements and by means of appropriately programmed computers. In a unit claim enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third etc. does not indicate any order. These words may be interpreted as names.

[0115] The foregoing description is merely a specific embodiment of the present invention or an illustration of a specific embodiment. The scope of protection of the present invention is not limited thereto. Any modifications or substitutions that can be readily conceived by a person skilled in the art within the technical scope disclosed in the present invention are intended to be encompassed by the scope of protection of the present invention. The scope of protection of the present invention shall be subject to the scope of protection of the claims.

Claims

1. An adaptive power regulation circuit, characterized in that: The circuit comprises: a plurality of power sensing units, each power sensing unit being configured to sense power consumed by a corresponding input power rail among a plurality of input power rails on the processor system board; a summer, configured to sum the sensed powers consumed by the respective input power rails to obtain a total power consumed by the plurality of input power rails; a plurality of first conversion units and second conversion units, each first conversion unit being configured to convert the sensed power consumed by a corresponding input power rail into a first bit sequence, and the second conversion unit being configured to convert the total power consumed by the plurality of input power rails into a second bit sequence; a logic operation unit, configured to perform a logic OR operation on the first bit sequence and the second bit sequence to generate a final bit sequence, The final bit sequence is transmitted to the processor on the processor system board, and the processor adaptively performs power adjustment based on the final bit sequence.

2. The circuit according to claim 1, wherein: The power sensing unit includes a voltage and current monitor for sensing a voltage and a current on a corresponding input power rail among the plurality of input power rails, and a multiplier for converting the sensed voltage and current into power consumed by the corresponding input power rail.

3. The circuit according to claim 1, wherein: Each first conversion unit converts the power consumed by the corresponding input power rail into the first bit sequence by performing a step-by-step comparison between the power consumed by the corresponding input power rail and the corresponding target power for the input power rail.

4. The circuit according to claim 1, wherein: The second conversion unit converts the total power into the second bit sequence by performing a step-by-step comparison between the total power consumed by the multiple input power rails and the total target power.

5. The circuit according to claim 1, wherein: The circuit further comprises a clock control unit for generating a bit sequence clock signal, wherein the bit sequence clock signal is used to control the transmission of the final bit sequence to the processor.

6. The circuit according to claim 5, characterized in that The circuit further includes: a parallel-to-serial conversion unit for performing parallel-to-serial conversion on the final bit sequence before the final bit sequence is transmitted to the processor. The converted final bit sequence is transmitted to the processor, and the processor adaptively performs power adjustment based on the converted final bit sequence.

7. The circuit according to claim 6, characterized in that The clock control unit is further configured to generate a packet clock signal, wherein the packet clock signal is configured to control the packetization of the converted final bit sequence into a plurality of data packets, so that the converted final bit sequence is transmitted to the processor in the form of data packets.

8. The circuit according to claim 1, wherein: The first conversion unit and the second conversion unit each include a multi-stage comparator.

9. The circuit according to claim 1, wherein: The first conversion unit and the second conversion unit each include an analog-to-digital converter.

10. The circuit according to claim 1, wherein: The processor includes a graphics processing unit.

11. A computing system, characterized in that: The computing system includes: processor; and An adaptive power regulation circuit, comprising: a plurality of power sensing units, each power sensing unit being configured to sense power consumed by a corresponding input power rail among a plurality of input power rails on the processor system board; a summer, configured to sum the sensed powers consumed by the respective input power rails to obtain a total power consumed by the plurality of input power rails; a plurality of first conversion units and second conversion units, each first conversion unit being configured to convert the sensed power consumed by a corresponding input power rail into a first bit sequence, and the second conversion unit being configured to convert the total power consumed by the plurality of input power rails into a second bit sequence; a logic operation unit, configured to perform a logic OR operation on the first bit sequence and the second bit sequence to generate a final bit sequence, The final bit sequence is transmitted to the processor on the processor system board, and the processor adaptively performs power adjustment based on the final bit sequence.

12. The computing system according to claim 11, wherein: The power sensing unit includes a voltage and current monitor for sensing a voltage and a current on a corresponding input power rail among the plurality of input power rails, and a multiplier for converting the sensed voltage and current into power consumed by the corresponding input power rail.

13. The computing system according to claim 11, wherein: Each first conversion unit converts the power consumed by the corresponding input power rail into the first bit sequence by performing a step-by-step comparison between the power consumed by the corresponding input power rail and the corresponding target power for the input power rail.

14. The computing system according to claim 11, wherein: The second conversion unit converts the total power into the second bit sequence by performing a step-by-step comparison between the total power consumed by the multiple input power rails and the total target power.

15. The computing system according to claim 11, wherein: The adaptive power regulation circuit further includes: a clock control unit, configured to generate a bit sequence clock signal, wherein the bit sequence clock signal is used to control the transmission of the final bit sequence to the processor.

16. The computing system according to claim 15, wherein: The adaptive power regulation circuit also includes: a parallel-to-serial conversion unit, which is used to convert the final bit sequence from parallel to serial before the final bit sequence is transmitted to the processor. The converted final bit sequence is transmitted to the processor, and the processor adaptively performs power regulation based on the converted final bit sequence.

17. The computing system according to claim 16, wherein: The clock control unit is further configured to generate a packet clock signal, wherein the packet clock signal is configured to control the packetization of the converted final bit sequence into a plurality of data packets, so that the converted final bit sequence is transmitted to the processor in the form of data packets.

18. The computing system according to claim 11, wherein: The first conversion unit and the second conversion unit each include a multi-stage comparator.

19. The computing system according to claim 11, wherein: The first conversion unit and the second conversion unit each include an analog-to-digital converter.

20. The computing system according to claim 11, wherein: The processor includes a graphics processing unit.

21. An electronic device, characterized in that: The electronic device comprises the adaptive power regulation circuit according to any one of claims 1 to 10.

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