IGBT Devices

Abstract

The invention belongs to the technical field of semiconductor power devices, and specifically discloses an IGBT device, comprising a plurality of gate grooves in an n-type semiconductor layer, a shielding gate located in the lower part of the gate groove, a gate located in the upper part of the gate groove, the gate, the shielding gate and the n-type semiconductor layer being insulated and isolated from each other; part of the shielding gate being externally connected to a gate voltage and defined as a first shielding gate, the remaining shielding gate being externally connected to an emitter voltage and defined as a second shielding gate, the first shielding gate and the second shielding gate being alternately arranged; a p-type body region being located in the n-type semiconductor layer and between adjacent gate grooves, the p-type body region comprising a first p-type body region and a second p-type body region, the first p-type body region being located on a side close to the adjacent first shielding gate, the second p-type body region being located on a side close to the adjacent second shielding gate, and the doping concentration of the first p-type body region being less than the doping concentration of the second p-type body region.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor power devices, and in particular relates to an IGBT device. Background Art

[0002] The Insulated Gate Bipolar Transistor (IGBT) device is a device composed of a Metal Oxide Semiconductor (MOS) transistor and a bipolar transistor. The input pole of the IGBT device is a MOS transistor, and the output pole is a PNP transistor. It combines the advantages of these two transistor devices, and has the advantages of low driving power and fast switching speed of MOS transistors, as well as the advantages of low saturation voltage drop and large capacity of bipolar transistors. Due to the low hole injection efficiency at the junction of the p-type body region and the n-type drift region of the IGBT device, the carrier concentration distribution is very low, resulting in an increase in the saturation voltage drop. When turned off, a large number of minority carriers are stored in the n-type drift region, resulting in a serious tailing phenomenon of the IGBT device's turn-off current and large turn-off losses. Summary of the invention

[0003] In view of this, an object of the present invention is to provide an IGBT device to reduce the turn-off loss of the IGBT device.

[0004] In order to achieve the above-mentioned object of the present invention, the present invention provides an IGBT device, comprising:

[0005] p-type collector region;

[0006] an n-type semiconductor layer located above the p-type collector region;

[0007] A plurality of gate trenches located in the n-type semiconductor layer, a shielding gate located in the lower part of the gate trench, and a gate located in the upper part of the gate trench, wherein the gate, the shielding gate and the n-type semiconductor layer are insulated and isolated from each other;

[0008] Part of the shielding gates are externally connected to a gate voltage and are defined as first shielding gates, and the remaining shielding gates are externally connected to an emitter voltage and are defined as second shielding gates, and the first shielding gates and the second shielding gates are alternately arranged;

[0009] A p-type body region is located in the n-type semiconductor layer and between adjacent gate trenches, the p-type body region includes a first p-type body region and a second p-type body region, the first p-type body region is located on a side close to the adjacent first shielding gate, the second p-type body region is located on a side close to the adjacent second shielding gate, n-type emitter regions are provided in the first p-type body region and the second p-type body region, and the doping concentration of the first p-type body region is less than the doping concentration of the second p-type body region.

[0010] Optionally, the shielding gate extends upward from the lower portion of the gate trench to the upper portion of the gate trench.

[0011] Optionally, the width of the upper portion of the gate trench is greater than the width of the lower portion of the gate trench.

[0012] Optionally, it further includes an n-type charge storage region located in the n-type semiconductor layer, and the n-type charge storage region is located below the gate.

[0013] Optionally, it further comprises an n-type collector region, wherein the n-type collector region is located below the n-type semiconductor layer and is alternately arranged with the p-type collector region.

[0014] Optionally, an n-type field stop region is further included, and the n-type field stop region is located between the p-type collector region and the n-type semiconductor layer.

[0015] The IGBT device of the present invention combines a low threshold voltage Vth1 with a large gate charge Qg1, and a high threshold voltage Vth2 with a small gate charge Qg2. In the process from on to off of the IGBT device, the current channel in the region where the high Vth2 and small Qg2 are combined will be quickly turned off, while the current channel in the region where the low Vth1 and large Qg1 are combined will be turned off later. Therefore, when the current channel in the region where the high Vth2 and small Qg2 are combined is just turned off, the current channel in the region where the low Vth1 and large Qg1 are combined is still in the on state. As the gate voltage Vg is further reduced, the current channel in the region where the low Vth1 and large Qg1 are combined is turned off. Therefore, the IGBT device externally shows the turn-off loss of the region where the low Vth1 and large Qg1 are combined, and the turn-off loss of the region where the high Vth2 and small Qg2 are combined is reduced, thereby reducing the turn-off loss of the IGBT device as a whole. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solution of the exemplary embodiment of the present invention, the following briefly introduces the drawings required for describing the embodiment.

[0017] Figure 1 It is a schematic cross-sectional structure diagram of a first embodiment of an IGBT device provided by the present invention;

[0018] Figure 2 It is a schematic cross-sectional structure diagram of a second embodiment of the IGBT device provided by the present invention. DETAILED DESCRIPTION

[0019] The following will be combined with the drawings in the embodiments of the present invention to fully describe the technical solution of the present invention in a specific manner. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. At the same time, in order to clearly illustrate the specific implementation methods of the present invention, the schematic diagrams listed in the drawings of the specification magnify the thickness of the layers and regions described in the present invention, and the size of the listed graphics does not represent the actual size.

[0020] Figure 1 FIG. 1 is a schematic cross-sectional view of a first embodiment of an IGBT device provided by the present invention. Figure 1 As shown, the IGBT device of the present invention includes a p-type collector region 20 and an n-type semiconductor layer 21 located above the p-type collector region 20 .

[0021] A plurality of gate trenches are located in the n-type semiconductor layer 21, a gate 25 is located in the upper part of the gate trench, and a shielding gate 27 is located in the lower part of the gate trench. The shielding gate 27 can be located only in the lower part of the gate trench, so that the gate 25 and the shielding gate 27 are an upper and lower structure. Optionally, the shielding gate 27 can also be located in the lower part of the gate trench and extend upward to the upper part of the gate trench. Figure 1 The shield gate 27 is located in the lower part of the gate trench and extends upward to the upper part of the gate trench as an example. At the same time, the width of the upper part of the gate trench can be greater than, equal to, or less than the width of the lower part of the gate trench. Figure 1 In the figure, it is shown that the width of the upper portion of the gate trench is greater than the width of the lower portion of the gate trench.

[0022] The gate 25, the shielding gate 27 and the n-type semiconductor layer 21 are insulated from each other. Figure 1 In the embodiment, the gate 25 is insulated and isolated from the n-type semiconductor layer 21 by the gate dielectric layer 24 , and the shielding gate 27 is isolated from the gate 25 and the n-type semiconductor layer 21 by the field oxide layer 26 . Usually, the thickness of the field oxide layer 26 is greater than that of the gate dielectric layer 24 .

[0023] In the IGBT device of the present invention, part of the shield gate 27 is connected to the gate voltage G and is defined as the first shield gate 27a, and the remaining shield gate 27 in the gate trench is connected to the emitter voltage ( Figure 1 The first shielding grid 27a and the second shielding grid 27b are alternately arranged.

[0024] The IGBT device of the present invention further includes a p-type body region 22 located in the n-type semiconductor layer 21 and between adjacent gate trenches, the p-type body region 22 includes a first p-type body region 22a and a second p-type body region 22b, the first p-type body region 22a is located on a side close to the adjacent first shielding gate 27a, and the second p-type body region 22b is located on a side close to the adjacent second shielding gate 27b. An n-type emitter region 23 is provided in both the first p-type body region 22a and the second p-type body region 22b. The doping concentration of the first p-type body region 22a is less than the doping concentration of the second p-type body region 22b.

[0025] For example, Figure 1 Only four p-type body regions 22 are shown, and only the middle two p-type body regions 22 completely show the first p-type body region 22a and the second p-type body region 22b, while the two side p-type body regions 22 only show the second p-type body region 22b.

[0026] In the IGBT device of the present invention, the threshold voltage Vth1 of the current channel in the first p-type body region 22a is less than the threshold voltage Vth2 of the current channel in the second p-type body region 22b. When the shielding gate 27 is connected to a gate voltage, the gate 25 in the gate trench has a larger gate charge Qg1; when the shielding gate 27 is connected to an emitter voltage, the gate 25 in the gate trench has a smaller gate charge Qg2. The first p-type body region 22a and the first shield gate 27a are arranged adjacent to each other, and the second p-type body region 22b and the second shield gate 27b are arranged adjacent to each other, so that low Vth1 and large Qg1 are combined, and high Vth2 and small Qg2 are combined, so that in the process from on to off of the IGBT device, the current channel in the region where high Vth2 and small Qg2 are combined will be quickly turned off, while the current channel in the region where low Vth1 and large Qg1 are combined will be turned off later, so that when the current channel in the region where high Vth2 and small Qg2 are combined is just turned off, the current channel in the region where low Vth1 and large Qg1 are combined is still in the on state, and as the gate voltage Vg is further reduced, the current channel in the region where low Vth1 and large Qg1 are combined is turned off. Therefore, the IGBT device is externally manifested as the turn-off loss of the region where low Vth1 and large Qg1 are combined, and the turn-off loss of the region where high Vth2 and small Qg2 are combined is reduced, thereby reducing the turn-off loss of the IGBT device as a whole.

[0027] Figure 2 is a schematic cross-sectional structure diagram of a second embodiment of an IGBT device provided by the present invention, such as Figure 2 As shown, in Figure 1On the basis of the IGBT device structure shown in the figure, the IGBT device of the present invention further includes an n-type charge storage region 32 located in the n-type semiconductor layer 21, and the n-type charge storage region 32 is located below the gate 25. The IGBT device of the present invention further includes an n-type collector region 30, and the n-type collector region 30 is located below the n-type semiconductor layer 21 and is alternately arranged with the p-type collector region 20. Optionally, the IGBT device of the present invention may also include an n-type field stop region 31, and the n-type field stop region 31 is between the p-type collector region 20 and the n-type semiconductor layer 21. The n-type charge storage region 32, the n-type field stop region 31 and the n-type collector region 30 are all known technologies and will not be described in detail in the embodiments of the present invention.

[0028] The above specific implementation methods and examples are specific supports for the technical ideas of the present invention, and cannot be used to limit the protection scope of the present invention. Any equivalent changes or equivalent modifications made on the basis of this technical solution in accordance with the technical ideas proposed by the present invention still fall within the scope of protection of the technical solution of the present invention.

Claims

1. IGBT device, characterized in that include: p-type collector region; an n-type semiconductor layer located above the p-type collector region; A plurality of gate trenches located in the n-type semiconductor layer, a shielding gate located in the lower part of the gate trench, and a gate located in the upper part of the gate trench, wherein the gate, the shielding gate and the n-type semiconductor layer are insulated and isolated from each other; Part of the shielding gates are externally connected to a gate voltage and are defined as first shielding gates, and the remaining shielding gates are externally connected to an emitter voltage and are defined as second shielding gates, and the first shielding gates and the second shielding gates are alternately arranged; A p-type body region is located in the n-type semiconductor layer and between adjacent gate trenches, the p-type body region includes a first p-type body region and a second p-type body region, the first p-type body region is located on a side close to the adjacent first shielding gate, the second p-type body region is located on a side close to the adjacent second shielding gate, n-type emitter regions are provided in the first p-type body region and the second p-type body region, and the doping concentration of the first p-type body region is less than the doping concentration of the second p-type body region.

2. The IGBT device according to claim 1, characterized in that: The shielding gate extends upward from the lower portion of the gate trench to the upper portion of the gate trench.

3. The IGBT device according to claim 2, characterized in that: The width of the upper portion of the gate trench is greater than the width of the lower portion of the gate trench.

4. The IGBT device according to claim 3, characterized in that: The invention also includes an n-type charge storage region located in the n-type semiconductor layer, wherein the n-type charge storage region is located below the gate.

5. The IGBT device according to claim 1, characterized in that: It also includes an n-type collector region, which is located below the n-type semiconductor layer and is alternately arranged with the p-type collector region.

6. The IGBT device according to claim 1, characterized in that: The invention also includes an n-type field stop region, wherein the n-type field stop region is located between the p-type collector region and the n-type semiconductor layer.

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