Off-chip capacitor-free LDO based on hybrid nonlinear slew rate enhancement and chip

Abstract

The invention relates to an off-chip capacitor-free LDO (Low Dropout Regulator) based on hybrid nonlinear slew rate enhancement and a chip, which are characterized in that nonlinear amplification of a dynamic alternating-current small signal is realized with relatively low static power consumption based on a push-pull low-power-consumption operational amplifier structure and a nonlinear slew rate enhancement structure provided by a transient slew rate enhancement circuit; the slew rate of the grid voltage of the power adjusting tube along with the change of the load current is greatly improved, so that the transient response speed of the LDO without the off-chip capacitor is greatly improved; in addition, the zero compensation circuit in the off-chip capacitor-free LDO adopts zero injection and an active capacitance multiplication technology to ensure the loop stability of the circuit of the off-chip capacitor-free LDO during light load, and the actual application requirements are well met.

Description

Technical Field

[0001] The invention belongs to the technical field of power management circuits and relates to an LDO without external capacitor based on hybrid nonlinear slew rate enhancement and a chip. Background Art

[0002] LDO (Low Dropout Regulator, a DC linear voltage regulator whose main function is to convert input voltage into a stable output voltage) is often used in power management chips due to its low cost, small size and good noise performance. A microfarad-level off-chip capacitor is required at the output end of the traditional LDO circuit to ensure the stability of the LDO and reduce the fluctuation of the output voltage with the load. With the rapid development of SOC (system-on-chip), removing the off-chip capacitor to reduce the cost of output PAD (pin pad) and PCB (printed circuit board) is an important research direction for fully integrated LDO circuits without off-chip capacitors that power digital circuit modules in SOC.

[0003] The output capacitance of the traditional LDO circuit is in the microfarad level, and its output port provides a main pole. A buffer is added to the output end of the operational amplifier to separate the main and secondary poles to ensure the stability of the LDO. When the load changes greatly, the large external capacitor is used to reduce the undershoot and overshoot of the output voltage.

[0004] In the LDO that powers the digital circuit module in the SOC, the load range requirement of the digital circuit module is not particularly large, but because the digital circuit performs circuit processing operations based on the clock edge, there is usually a fast load change at a certain clock edge, which brings great challenges to the design of LDO without external capacitors: because it is necessary to achieve circuit stability compensation and transient response optimization with low static power consumption and no external large capacitors, the key technologies here include low power frequency compensation technology and transient enhancement circuits. However, the transient response speed of traditional LDO circuits is still difficult to support the above application requirements. Summary of the invention

[0005] In view of the problems existing in the above-mentioned traditional methods, the present invention proposes a LDO without external capacitor based on hybrid nonlinear slew rate enhancement and a power management chip, which can effectively improve the transient response speed of the LDO.

[0006] In order to achieve the above objectives, the embodiments of the present invention adopt the following technical solutions:

[0007] On the one hand, a non-chip capacitor-free LDO based on hybrid nonlinear slew rate enhancement is provided, comprising a bias circuit, a transconductance amplifier, a power adjustment tube, a transient slew rate enhancement circuit, a zero point compensation circuit and a feedback resistor; the zero point compensation circuit comprises a Miller zero point compensation unit and a feedforward zero point compensation unit;

[0008] The output end of the bias circuit is respectively connected to the bias input end of the transconductance amplifier and the bias input end of the transient slew rate enhancement circuit, the inverting input end of the transconductance amplifier is connected to the reference voltage, the non-inverting input end of the transconductance amplifier is connected to the output end of the transient slew rate enhancement circuit through a feedforward zero compensation unit, the output end of the transconductance amplifier is respectively connected to the input end of the transient slew rate enhancement circuit and the gate of the power adjustment tube, the source of the power adjustment tube is used to connect to the power supply, the drain of the power adjustment tube is connected to the output end of the transient slew rate enhancement circuit as a voltage output end, the Miller zero compensation unit is connected across the input end and the output end of the transient slew rate enhancement circuit, one end of the feedback resistor is connected to the non-inverting input end of the transconductance amplifier, and the other end of the feedback resistor is grounded;

[0009] The bias circuit is used to provide a bias output according to a reference current, a push-pull circuit structure is provided inside the transconductance amplifier, a linear transient enhancement network and a nonlinear transient enhancement network are provided inside the transient slew rate enhancement circuit, the linear transient enhancement network is used to perform slew rate enhancement of overshoot and undershoot, the nonlinear transient enhancement network is used to perform current nonlinear amplification, and the zero-point compensation circuit is used to provide on-chip zero-pole compensation.

[0010] On the other hand, a power management chip is also provided, comprising a chip body and the above-mentioned LDO without external capacitor based on hybrid nonlinear slew rate enhancement.

[0011] One of the above technical solutions has the following advantages and beneficial effects:

[0012] The above-mentioned LDO and chip without external capacitor based on hybrid nonlinear slew rate enhancement, through a low-power operational amplifier structure based on push-pull (push-pull circuit) and a nonlinear slew rate enhancement structure provided by a transient slew rate enhancement circuit, realizes nonlinear amplification of dynamic AC small signals with relatively small static power consumption, greatly improves the slew rate of the gate voltage of the power adjustment tube as the load current changes, thereby greatly improving the transient response speed of the LDO without external capacitor; in addition, the zero-point compensation circuit in the LDO without external capacitor adopts zero-point injection and active capacitance multiplication technology to ensure the loop stability of the circuit of the LDO without external capacitor under light load, which well meets the actual application needs. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0014] Figure 1 Schematic diagram of the overall circuit framework of an LDO without external capacitor based on hybrid nonlinear slew rate enhancement in one embodiment;

[0015] Figure 2 It is a schematic diagram of a partial circuit structure of an LDO without external capacitor based on hybrid nonlinear slew rate enhancement in one embodiment;

[0016] Figure 3 It is a schematic diagram of a partial circuit structure of an LDO without external capacitor based on hybrid nonlinear slew rate enhancement in another embodiment;

[0017] Figure 4 A schematic diagram of loop stability simulation of an LDO without external capacitor based on hybrid nonlinear slew rate enhancement in one embodiment;

[0018] Figure 5 FIG. 1 is a transient simulation diagram of an embodiment without a transient slew rate enhancement circuit, wherein (a) is a case where the load current I is switched from 10 mA to 40 mA with a change time of 1 ns, and (b) is a case where the load current I is switched back from 40 mA to 10 mA with a change time of 1 ns;

[0019] Figure 6 Schematic diagram of transient simulation with a transient slew rate enhancement circuit in one embodiment, wherein (a) is the case when the load current I switches from 10mA to 40mA with a change time of 1ns, and (b) is the case when the load current I switches back from 40mA to 10mA with a change time of 1ns. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0022] It should be noted that the reference to "embodiment" in this article means that the specific features, structures or characteristics described in conjunction with the embodiment may be included in at least one embodiment of the present invention. The presentation of this phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It will be understood by those skilled in the art that the embodiments described herein may be combined with other embodiments. The term "and / or" used in the specification of the present invention and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations. "Connection" can be a direct connection between two devices, or it can be an indirect connection between two devices through other devices.

[0023] The following will describe the implementation of the present invention in detail with reference to the accompanying drawings in the embodiment diagram of the present invention.

[0024] In one embodiment, Figure 1 As shown, a non-chip capacitor-free LDO based on hybrid nonlinear slew rate enhancement is provided, which may include a bias circuit ( Figure 1 ), a transconductance amplifier 12, a power adjustment tube MP7, a transient slew rate enhancement circuit 13, a zero compensation circuit 14 and a feedback resistor R3. The zero compensation circuit 14 includes a Miller zero compensation unit and a feedforward zero compensation unit.

[0025] The output end of the bias circuit is connected to the bias input end of the transconductance amplifier 12 and the bias input end of the transient slew rate enhancement circuit 13. The inverting input end of the transconductance amplifier 12 is connected to the reference voltage V REF The non-inverting input terminal of the transconductance amplifier 12 is connected to the output terminal of the transient slew rate enhancement circuit 13 through the feedforward zero compensation unit, and the output terminal of the transconductance amplifier 12 is respectively connected to the input terminal of the transient slew rate enhancement circuit 13 and the gate of the power adjustment tube MP7. The source of the power adjustment tube MP7 is used to connect the power supply (AVDD), and the drain of the power adjustment tube MP7 is connected to the output terminal of the transient slew rate enhancement circuit 13 as the voltage output terminal (OUT, the corresponding output voltage is recorded as V OUT The Miller zero compensation unit is connected between the input and output of the transient slew rate enhancement circuit 13. One end of the feedback resistor R3 is connected to the non-inverting input of the transconductance amplifier 12, and the other end of the feedback resistor R3 is grounded (AVSS). The feedback voltage connected to the non-inverting input of the transconductance amplifier 12 can be recorded as V FB .

[0026] The bias circuit is used to provide a bias output according to the reference current (IBIAS). A push-pull circuit structure is provided inside the transconductance amplifier 12. The transient slew rate enhancement circuit 13 is a circuit (gm_sre) that adopts a nonlinear transient enhancement active capacitance multiplication technology, and a linear transient enhancement network and a nonlinear transient enhancement network are provided inside it. The linear transient enhancement network is used to enhance the slew rate of overshoot and undershoot, and the nonlinear transient enhancement network is used to perform nonlinear current amplification. The zero point compensation circuit 14 is used to provide on-chip zero-pole compensation.

[0027] It can be understood that the bias circuit can provide the bias required for normal operation of other circuit units in the LDO without external capacitors according to the reference current given by the SOC. The gate of the power adjustment tube MP7 is connected to the output terminal V GATE The source of the power adjustment tube MP7 is connected to the power supply AVDD, and the drain of the power adjustment tube MP7 is used as the output voltage V of the LDO without external capacitor. OUT Output terminal, in the circuit of LDO without external capacitor, the transconductance amplifier 12 is used to amplify the difference between the reference voltage and the feedback voltage of the output port, and is used to control the gate voltage of the power adjustment tube to ensure that the output voltage is stable under different load conditions.

[0028] The above-mentioned LDO without external capacitor based on hybrid nonlinear slew rate enhancement realizes nonlinear amplification of dynamic AC small signals with relatively small static power consumption through a low-power operational amplifier structure based on push-pull (push-pull circuit) and combined with a nonlinear slew rate enhancement structure provided by a transient slew rate enhancement circuit 13, thereby greatly improving the slew rate of the gate voltage of the power adjustment tube MP7 as the load current changes, thereby greatly improving the transient response speed of the LDO without external capacitor; in addition, the zero-point compensation circuit 14 in the LDO without external capacitor adopts zero-point injection and active capacitance multiplication technology to ensure the loop stability of the circuit of the LDO without external capacitor under light load, which well meets the actual application needs.

[0029] It should be noted that the transistors MN in this specification refer to NMOS transistors, and the transistors MP refer to PMOS transistors. The transconductance amplifier 12, the transient slew rate enhancement circuit 13, and the zero compensation circuit 14 can all be constructed by using transistors, resistors, capacitors and other devices according to the basic principles of circuit design in this field according to the functions to be realized.

[0030] In one embodiment, Figure 2As shown, the bias circuit includes a reference current source IBIAS, a transistor MN1, a transistor MN2 and a transistor MP1. The positive end of the reference current source IBIAS is used to connect to the power supply AVDD, and the negative end of the reference current source IBIAS is respectively connected to the drain and gate of the transistor MN1. The gate of the transistor MN2 is connected to the gate of the transistor MN1, the source of the transistor MN1 and the source of the transistor MN2 are both grounded to AVSS, the drain of the transistor MN2 is respectively connected to the drain and gate of the transistor MP1, and the source of the transistor MP1 is used to connect to the power supply AVDD. The gate of the transistor MN1 leads to a first bias output terminal (whose bias voltage is recorded as V BN ), the drain of transistor MP1 leads to the second bias output terminal (its bias voltage is recorded as V BP ).

[0031] The bias circuit adopts the above circuit structure, which can achieve an efficient and stable bias function with a relatively simple and reliable circuit structure.

[0032] In one embodiment, Figure 2 As shown, the transconductance amplifier 12 includes a transistor MP2, a transistor MP3, a transistor MP4, a transistor MP5, a transistor MP6, a transistor MN3, a transistor MN4, a transistor MN5 and a transistor MN6. The sources of the transistors MP2, MP3 and MP6 are used to connect to the power supply AVDD, the gate of the transistor MP6 is respectively connected to the gate and drain of the transistor MP2, the drain of the transistor MP6 is respectively connected to the drain of the transistor MN6 and the gate of the power adjustment tube MP7, and the drain of the transistor MP2 is connected to the drain of the transistor MN3. The gate of the transistor MP3 is connected to the second bias output terminal, the drain of the transistor MP3 is respectively connected to the source of the transistor MP4 and the source of the transistor MP5, and the gate of the transistor MP4 is connected to the reference voltage V REF , the gate of transistor MP5 is connected to one end of feedback resistor R3. The drain of transistor MP4 is connected to the drain and gate of transistor MN4 respectively, and the drain of transistor MP5 is connected to the drain and gate of transistor MN5 respectively. The source of transistor MN3, the source of transistor MN4, the source of transistor MN5 and the source of transistor MN6 are all grounded to AVSS. The gate of transistor MN3 is connected to the drain of transistor MN4, and the gate of transistor MN6 is connected to the drain of transistor MN5.

[0033] It can be understood that the transistor MP3 is used as the tail current source of the transconductance amplifier 12. The transistor MP5 is used as a common-mode amplifier, and its gate is connected to the feedback voltage V FB Transistor MP4 is used as an inverting amplifier, and its gate is connected to the reference voltage V REFThe inverting amplifier MP4 forms an inverting amplifier path through transistors MN3, MN4, MP2 and MP6; the non-inverting amplifier MP5 forms a non-inverting amplifier path through transistors MN5 and MN6. The non-inverting amplifier path and the inverting amplifier path form a push-pull structure, forming a gate control signal V of the power adjustment tube MP7 at the output end of the transconductance amplifier 12. GATE The transconductance amplifier 12 amplifies the reference voltage V REF The feedback voltage V FB The difference between them is used to control the gate voltage of the power adjustment tube MP7 to ensure the output voltage V OUT Stable under different load conditions.

[0034] In one embodiment, Figure 2 As shown, the Miller zero compensation unit includes a resistor R1 and a capacitor C1. The feedforward zero compensation unit includes a resistor R2 and a capacitor C2. One end of the resistor R1 is connected to the input end of the transient slew rate enhancement circuit 13, and the other end of the resistor R1 is connected to the output end of the transient slew rate enhancement circuit 13 through the capacitor C1. One end of the resistor R2 is connected to the non-inverting input end of the transconductance amplifier 12, and the other end of the resistor R2 is connected to the output end of the transient slew rate enhancement circuit 13. The capacitor C2 is connected in parallel to both ends of the resistor R2.

[0035] It can be understood that in this embodiment, the resistor R1 and the capacitor C1 cooperate with the power adjustment tube MP7 to form the Miller zero compensation, and the resistor R2 and the capacitor C2 cooperate with the feedback resistor R3 to form the feedforward zero compensation. The off-chip capacitor LDO does not require an off-chip microfarad capacitor, so the on-chip zero-pole compensation method is adopted, including zero compensation and the active capacitor multiplication compensation described later. About zero compensation: The compensation zero point z1 of the Miller zero compensation part:

[0036]

[0037] The zero-pole compensation provided by the feedforward zero compensation has a compensation zero point z2:

[0038]

[0039] The introduced pole p1 is:

[0040]

[0041] Among them, R1 represents the resistance value of the resistor R1, gmp7 represents the on-resistance value of the power adjustment tube MP7, C1 represents the capacitance value of the capacitor C1, R2 represents the resistance value of the resistor R2, C2 represents the capacitance value of the capacitor C2, and R3 represents the resistance value of the feedback resistor R3.

[0042] In one embodiment, Figure 3 As shown, the nonlinear transient enhancement network includes a resistor R4, a resistor R5, a resistor R6, a resistor R7, a capacitor C3, a capacitor C4, a transistor MN7, a transistor MN8, a transistor MN9, a transistor MN10, a transistor MP8, a transistor MP9, a transistor MP10 and a transistor MP11. One end of the resistor R4 is connected to the second bias output end of the bias circuit. The other end of the resistor R4 is respectively connected to one end of the capacitor C3, the gate of the transistor MP8 and the gate of the transistor MP9. The source of the transistor MP8, the source of the transistor MP9 and the source of the transistor MP11 are all used to connect to the power supply. The source of the transistor MP10 is used to connect to the power supply AVDD through the resistor R6. The drain of the transistor MP8 is respectively connected to the drain of the transistor MN7, the drain of the transistor MN9 and the gate of the transistor MN10. The drain of the transistor MN9 is connected to the gate, and the drain of the transistor MP9 is respectively connected to the drain of the transistor MN8, the drain of the transistor MP10 and the gate of the transistor MP11. The drain of the transistor MP10 is connected to the gate. The drain of the transistor MP11 is connected to the drain of the transistor MN10 and is also connected to the gate of the power adjustment tube MP7.

[0043] One end of the resistor R5 is connected to the first bias output end of the bias circuit, and the other end of the resistor R5 is respectively connected to one end of the capacitor C4, the gate of the transistor MN7, and the gate of the transistor MN8. The other end of the capacitor C3 and the other end of the capacitor C4 are both connected to the drain of the power adjustment tube MP7. The source of the transistor MN7, the source of the transistor MN8, and the source of the transistor MN10 are all grounded to AVSS, and the source of the transistor MN9 is grounded to AVSS through the resistor R7.

[0044] It can be understood that the output voltage V OUT Through capacitors C3 and C4, coupled to the ends A and B, the gate of the power adjustment tube MP7 is connected to the common end B of the capacitor C4 and the resistor R5 in series, and the gate of the transistor MP8 is connected to the common end A of the capacitor C3 and the resistor R4 in series. The source of MP8 is connected to the power supply AVDD, the source of the transistor MN7 is connected to the ground AVSS, and the drains of the transistors MN7 and MP8 are connected to the gates of the transistors MN9 and MN10. The gates of the transistors MN8 and MP9 are connected to the B end and the A end respectively, and their drains are short-circuited and connected to the gates of the transistors MP10 and MP11. The source of the transistor MN8 is connected to the ground AVSS. The source of the transistor MP9 is connected to the power supply AVDD, the source of the transistor MN9 is connected to the ground AVSS through the resistor R7, and the source of the transistor MP10 is connected to the power supply AVDD through the resistor R6. The sources of the transistors MN10 and MP11 are connected to the ground AVSS and the power supply AVDD respectively, and their drains are connected to V GATE Short circuit.

[0045] In one embodiment, Figure 3 As shown, the linear transient enhancement network includes a resistor R8, a resistor R9, a capacitor C5, a capacitor C6, a transistor MN11, a transistor MN12, a transistor MN13, a transistor MN14, a transistor MN15, a transistor MP12, a transistor MP13, a transistor MP14, a transistor MP15 and a transistor MP16. The source of transistor MP12 and the source of transistor MP13 are both used to connect to the power supply AVDD, the gate of transistor MP12 is connected to the gate of transistor MP13, the drain of transistor MP12 is connected to the drain of transistor MN14 and connected to the gate of power adjustment tube MP7. The drain of transistor MP13 is respectively connected to the gate of transistor MP12 and the drain of transistor MN12, and the source of transistor MN12 is grounded to AVSS. The gate of transistor MN12 is respectively connected to one end of resistor R8 and one end of capacitor C5, the other end of resistor R8 is respectively connected to the gate of transistor MN11 and the drain of transistor MP14, and the source of transistor MP14 is grounded to AVSS. The gate of the transistor MP14 is connected to the second bias output terminal of the bias circuit, the drain of the transistor MN11 is connected to the drain of the transistor MP14, and the drain of the transistor MN11 is grounded to AVSS.

[0046] The source of transistor MN14 and the source of transistor MN15 are both grounded to AVSS. The gate of transistor MN14 is respectively connected to the gate of transistor MN15 and the drain of transistor MP16. The drain of transistor MN15 is connected to the drain of transistor MP16, the source of transistor MP16 is grounded to AVSS, and the gate of transistor MP16 is respectively connected to one end of resistor R9 and one end of capacitor C6. The other end of resistor R9 is respectively connected to the gate of transistor MP15 and the drain of transistor MN13. The source of transistor MP15 is grounded to AVSS, and the drain of transistor MP15 is connected to the drain of transistor MN13. The source of transistor MN13 is grounded to AVSS, and the gate of transistor MN13 is connected to the first bias output terminal of the bias circuit. The other end of capacitor C5 and the other end of capacitor C6 are both connected to the drain of power adjustment tube MP7.

[0047] It can be understood that the output voltage V OUTThrough capacitors C5 and C6, it is coupled to the E and F terminals. The E terminal is connected to the gate of transistor MN12 and one end of resistor R8, and the other end of resistor R8 is connected to transistor MN11; the F terminal is connected to the gate of transistor MP16 and one end of resistor R9, and the other end of resistor R9 is connected to transistor MP15. The drain of transistor MN12 is connected to transistor MP13, and the source of transistor MN12 is grounded to AVSS. The drain of transistor MP16 is connected to transistor MN15. The gates of transistor MN15 and transistor MP13 are connected to the gates of transistor MN14 and transistor MP12 respectively. The drains of transistor MN14 and transistor MP12 are connected to V GATE The source terminals are connected to AVSS and AVDD respectively.

[0048] Resistor R4 and capacitor C3, resistor R5 and capacitor C4, resistor R8 and capacitor C5, resistor R9 and capacitor C6 form a first-order RC high-pass network, which affects the output voltage V OUT The high-frequency overshoot and undershoot voltage are nonlinearly amplified. The width-to-length ratio of transistor MP8 to transistor MP9 is 1:K1. The width-to-length ratio of transistor MN7 to transistor MN8 is K1:1. Transistor MN7, transistor MN8, transistor MP8 and transistor MP9 constitute a current difference circuit, and the difference of the currents is converted into current voltage to provide differential voltage output signals at the drains of transistor MN7 and transistor MN8 respectively.

[0049] The width-to-length ratio of transistor MN9 to transistor MN10 is 1:K2. The width-to-length ratio of transistor MP10 to transistor MP11 is 1:K2. The output signals of the previous current difference circuit are connected to the gates of transistor MN9 and transistor MP10 respectively, and after being proportionally amplified, push-pull output is performed at the drains of transistor MP11 and transistor MN10. The drains of transistor MP11 and transistor MN10 are connected to the output stage V GATE The transistor MN11, the transistor MN12, the transistor MN13, the transistor MN14, the transistor MN15, the transistor MP12, the transistor MP13, the transistor MP14, the transistor MP15, the transistor MP16, the capacitor C5 and the capacitor C6 are components of the active capacitance multiplication compensation circuit, which has an output voltage V OUT With V GATE Active capacitance multiplication compensation is achieved between the output voltage V OUT The high-frequency overshoot and undershoot voltages are linearly transmitted through the active capacitor multiplication compensation circuit and are connected to V by transistors MP12 and MN14. GATE Push-pull output.

[0050] Specifically, the transient slew rate enhancement circuit 13 performs linear and nonlinear superposition amplification through a dual loop to enhance VGATE In a linear transient enhancement network, the change in output voltage caused by load jump is ΔV OUT Through the high-pass network of capacitor C6 and resistor R9, the slew rate of the undershoot is enhanced through transistor MP16, transistor MN15 and transistor MN14, and the enhanced small signal current I MN14 as follows:

[0051]

[0052] ΔV OUT Through the high-pass network of capacitor C5 and resistor R8, and then through transistor MN12, transistor MP13 and transistor MN12, the overshoot slew rate is enhanced, and the enhanced small signal current I MP12 as follows:

[0053]

[0054] Among them, gmp16 represents the on-resistance value of transistor MP16, gmn14 represents the on-resistance value of transistor MN14, gmn15 represents the on-resistance value of transistor MN15, gmn12 represents the on-resistance value of transistor MN12, gmp12 represents the on-resistance value of transistor MP12, and gmp13 represents the on-resistance value of transistor MP13. The above two loops constitute a push-pull structure for ΔV OUT Perform linear amplification and change the V GATE The charge and discharge current increases the slew rate during load switching.

[0055] In nonlinear transient enhancement networks, ΔV OUT The current difference is calculated through transistors MN7, MN8, MP8 and MP9, and then injected into transistors MN9 and MP10 respectively, and finally amplified through transistors MN10 and MP11; the push-pull structure is used to enhance the V GATE The nonlinear charging and discharging capability, nonlinear current I MN10 and I MP11 The size is expressed as follows:

[0056]

[0057] Where W and L represent the gate width and gate length of the transistor respectively, unC OX ( ) represents the product of the mobility of the transistor and the gate oxide capacitance per unit area, I MN9 represents the current flowing through transistor MN9, I MP10 represents the current flowing through transistor MN9, R6 represents the resistance value of resistor R6, R7 represents the resistance value of resistor R7,

[0058] The linear transient enhancement network also uses active capacitance multiplication technology to amplify the capacitor C6. The amplified equivalent capacitance can be expressed by the following formula:

[0059]

[0060] Where An is the gain of the feedback pull path. The equivalent capacitance after amplification of capacitor C5 can be expressed as follows:

[0061]

[0062] Wherein, Ap is the gain of the feedback push path. Wherein, sC5 represents the admittance of capacitor C5, sC6 represents the admittance of capacitor C6, gmn11 represents the on-resistance value of transistor MN11, gmp15 represents the on-resistance value of transistor MP15, R9 represents the resistance value of resistor R9, and R8 represents the resistance value of resistor R8.

[0063] In one embodiment, the loop stability simulation of the LDO without external capacitor based on hybrid nonlinear slew rate enhancement is as follows: Figure 4 As shown in the figure, in the load range of 0nA to 40mA, the phase margin of the LDO without external capacitor is always greater than 30°, and the gain margin is always greater than 9.5dB.

[0064] Figure 5 The transient simulation diagram without the transient slew rate enhancement circuit 13 of the present invention is shown in FIG. Figure 5 (a) When the load current I switches from 10mA to 40mA with a change time of 1ns, the output voltage V0 undershoots 185mV, the response time is 159.5ns, and the recovery time is 1.502us. At this time, the positive slew rate of the gate of the power regulator MP7 is 0.518V / us. Figure 5 (b) When the load current I switches back from 40mA to 10mA with a change time of 1ns, the response time is 165.8ns, the output voltage V0 overshoots 165mV, the response time is 165.8ns, and the recovery time is 1.91us. At this time, the negative slew rate of the gate of the power regulator MP7 is 0.683V / us.

[0065] Figure 6 FIG. 1 shows a transient simulation diagram of the transient slew rate enhancement circuit 13 of the present invention, see FIG. Figure 6 (a) When the load current I switches from 10mA to 40mA with a change time of 1ns, the output voltage V0 undershoots 92mV, the response time is 38.7ns, and the recovery time is 210.3ns. At this time, the positive slew rate of the gate of the power regulator MP7 is 13.499V / us. Figure 6(b) When the load current I switches from 40mA to 10mA with a change time of 1ns, the output voltage V0 overshoots 90mV, the response time is 43.27ns, and the recovery time is 297.79ns. At this time, the positive slew rate of the gate of the power regulator MP7 is 17.061V / us. Where VC represents Figure 3 The voltage at point C, VD represents Figure 3 The voltage at point D, VE represents Figure 3 The voltage at point E, VF represents Figure 3 The voltage at point F, VG, represents the gate voltage of the power adjustment tube MP7.

[0066] During load switching, Figure 3 The C and D terminals in the transient slew rate enhancement circuit 13 are nonlinearly amplified, and the C terminal is reduced from 2.945V to 1.5663V; the D terminal is increased from 35.759mV to 595.55mV. The transient slew rate enhancement circuit 13 pushes and pulls the charging and discharging of the gate capacitance.

[0067] In one embodiment, a power management chip is further provided, comprising a chip body and the LDO without external capacitor based on hybrid nonlinear slew rate enhancement in any of the above embodiments.

[0068] It can be understood that for the specific explanation of the LDO without external capacitor based on hybrid nonlinear slew rate enhancement in the power management chip embodiment, please refer to the corresponding explanation of the various embodiments of the LDO without external capacitor based on hybrid nonlinear slew rate enhancement in the above text, which will not be repeated here. In addition to the chip body and the LDO without external capacitor based on hybrid nonlinear slew rate enhancement, the above-mentioned power management chip can also include other existing auxiliary modules in the field, which can be understood in the same way as the existing structures of various types of power management chips in the field. The chip body refers to the circuit of the remaining chip components in the power management chip except the LDO without external capacitor, and the electrical connection between the LDO without external capacitor and the chip body can be understood in the same way as the existing connection method when the LDO without external capacitor is applied to the power management chip in the field.

[0069] The above-mentioned power management chip, by applying the above-mentioned LDO without external capacitor based on hybrid nonlinear slew rate enhancement, a low-power operational amplifier structure based on push-pull (push-pull circuit) and a nonlinear slew rate enhancement structure provided by the transient slew rate enhancement circuit 13, realizes nonlinear amplification of dynamic AC small signals with relatively small static power consumption, greatly improves the slew rate of the gate voltage of the power adjustment tube MP7 as the load current changes, thereby greatly improving the transient response speed of the LDO without external capacitor; in addition, the zero-point compensation circuit 14 in the LDO without external capacitor adopts zero-point injection and active capacitance multiplication technology to ensure the loop stability of the circuit of the LDO without external capacitor under light load, which well meets the actual application needs.

[0070] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0071] The above embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of protection of the invention. It should be pointed out that, for a person of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present application, and all of them belong to the scope of protection of the present application. Therefore, the scope of protection of the present application shall be subject to the attached claims.

Claims

1. A LDO without external capacitor based on hybrid nonlinear slew rate enhancement, characterized in that: It includes a bias circuit, a transconductance amplifier, a power adjustment tube, a transient slew rate enhancement circuit, a zero point compensation circuit and a feedback resistor; the zero point compensation circuit includes a Miller zero point compensation unit and a feedforward zero point compensation unit; The output end of the bias circuit is respectively connected to the bias input end of the transconductance amplifier and the bias input end of the transient slew rate enhancement circuit, the inverting input end of the transconductance amplifier is connected to the reference voltage, the non-inverting input end of the transconductance amplifier is connected to the output end of the transient slew rate enhancement circuit through the feedforward zero compensation unit, the output end of the transconductance amplifier is respectively connected to the input end of the transient slew rate enhancement circuit and the gate of the power adjustment tube, the source of the power adjustment tube is used to connect to the power supply, the drain of the power adjustment tube is connected to the output end of the transient slew rate enhancement circuit as a voltage output end, the Miller zero compensation unit is connected across the input end and the output end of the transient slew rate enhancement circuit, one end of the feedback resistor is connected to the non-inverting input end of the transconductance amplifier, and the other end of the feedback resistor is grounded; The bias circuit is used to provide a bias output according to a reference current, a push-pull circuit structure is provided inside the transconductance amplifier, a linear transient enhancement network and a nonlinear transient enhancement network are provided inside the transient slew rate enhancement circuit, the linear transient enhancement network is used to perform slew rate enhancement of overshoot and undershoot, the nonlinear transient enhancement network is used to perform current nonlinear amplification, and the zero-point compensation circuit is used to provide on-chip zero-pole compensation.

2. The hybrid nonlinear slew rate enhanced LDO without external capacitor according to claim 1, characterized in that: The bias circuit includes a reference current source IBIAS, a transistor MN1, a transistor MN2 and a transistor MP1, wherein the positive end of the reference current source IBIAS is used to connect to a power supply, the negative end of the reference current source IBIAS is respectively connected to the drain and the gate of the transistor MN1, the gate of the transistor MN2 is connected to the gate of the transistor MN1, the source of the transistor MN1 and the source of the transistor MN2 are both grounded, the drain of the transistor MN2 is respectively connected to the drain and the gate of the transistor MP1, and the source of the transistor MP1 is used to connect to a power supply; the gate of the transistor MN1 leads to a first bias output terminal, and the drain of the transistor MP1 leads to a second bias output terminal.

3. The LDO without external capacitor based on hybrid nonlinear slew rate enhancement according to claim 2, characterized in that: The transconductance amplifier includes a transistor MP2, a transistor MP3, a transistor MP4, a transistor MP5, a transistor MP6, a transistor MN3, a transistor MN4, a transistor MN5 and a transistor MN6; The sources of the transistors MP2, MP3 and MP6 are used to connect to a power source, the gate of the transistor MP6 is respectively connected to the gate and drain of the transistor MP2, the drain of the transistor MP6 is respectively connected to the drain of the transistor MN6 and the gate of the power adjustment tube, and the drain of the transistor MP2 is connected to the drain of the transistor MN3; The gate of the transistor MP3 is connected to the second bias output terminal, the drain of the transistor MP3 is respectively connected to the source of the transistor MP4 and the source of the transistor MP5, the gate of the transistor MP4 is connected to the reference voltage, the gate of the transistor MP5 is connected to one end of the feedback resistor, the drain of the transistor MP4 is respectively connected to the drain and gate of the transistor MN4, and the drain of the transistor MP5 is respectively connected to the drain and gate of the transistor MN5; The source of the transistor MN3, the source of the transistor MN4, the source of the transistor MN5 and the source of the transistor MN6 are all grounded, the gate of the transistor MN3 is connected to the drain of the transistor MN4, and the gate of the transistor MN6 is connected to the drain of the transistor MN5.

4. The LDO without external capacitor based on hybrid nonlinear slew rate enhancement according to any one of claims 1 to 3, characterized in that: The Miller zero compensation unit includes a resistor R1 and a capacitor C1, and the feedforward zero compensation unit includes a resistor R2 and a capacitor C2, one end of the resistor R1 is connected to the input end of the transient slew rate enhancement circuit, and the other end of the resistor R1 is connected to the output end of the transient slew rate enhancement circuit through the capacitor C1, one end of the resistor R2 is connected to the non-inverting input end of the transconductance amplifier, and the other end of the resistor R2 is connected to the output end of the transient slew rate enhancement circuit, and the capacitor C2 is connected in parallel to both ends of the resistor R2.

5. The LDO without external capacitor based on hybrid nonlinear slew rate enhancement according to claim 4, characterized in that: The nonlinear transient enhancement network includes a resistor R4, a resistor R5, a resistor R6, a resistor R7, a capacitor C3, a capacitor C4, a transistor MN7, a transistor MN8, a transistor MN9, a transistor MN10, a transistor MP8, a transistor MP9, a transistor MP10 and a transistor MP11; One end of the resistor R4 is connected to the second bias output end of the bias circuit, and the other end of the resistor R4 is respectively connected to one end of the capacitor C3, the gate of the transistor MP8 and the gate of the transistor MP9, the source of the transistor MP8, the source of the transistor MP9 and the source of the transistor MP11 are all used to connect to a power supply, the source of the transistor MP10 is used to connect to a power supply through the resistor R6, the drain of the transistor MP8 is respectively connected to the drain of the transistor MN7, the drain of the transistor MN9 and the gate of the transistor MN10, the drain of the transistor MN9 is connected to the gate, the drain of the transistor MP9 is respectively connected to the drain of the transistor MN8, the drain of the transistor MP10 and the gate of the transistor MP11, the drain of the transistor MP10 is connected to the gate, the drain of the transistor MP11 is connected to the drain of the transistor MN10 and connected to the gate of the power adjustment tube; One end of the resistor R5 is connected to the first bias output end of the bias circuit, the other end of the resistor R5 is respectively connected to one end of the capacitor C4, the gate of the transistor MN7 and the gate of the transistor MN8, the other end of the capacitor C3 and the other end of the capacitor C4 are both connected to the drain of the power adjustment tube, the source of the transistor MN7, the source of the transistor MN8 and the source of the transistor MN10 are all grounded, and the source of the transistor MN9 is grounded through the resistor R7.

6. The LDO without external capacitor based on hybrid nonlinear slew rate enhancement according to claim 4, characterized in that: The linear transient enhancement network includes a resistor R8, a resistor R9, a capacitor C5, a capacitor C6, a transistor MN11, a transistor MN12, a transistor MN13, a transistor MN14, a transistor MN15, a transistor MP12, a transistor MP13, a transistor MP14, a transistor MP15 and a transistor MP16; The source of the transistor MP12 and the source of the transistor MP13 are both used to connect to a power supply, the gate of the transistor MP12 is connected to the gate of the transistor MP13, the drain of the transistor MP12 is connected to the drain of the transistor MN14 and to the gate of the power adjustment tube, the drain of the transistor MP13 is respectively connected to the gate of the transistor MP12 and the drain of the transistor MN12, and the source of the transistor MN12 is grounded; The gate of the transistor MN12 is respectively connected to one end of the resistor R8 and one end of the capacitor C5, the other end of the resistor R8 is respectively connected to the gate of the transistor MN11 and the drain of the transistor MP14, the source of the transistor MP14 is grounded, the gate of the transistor MP14 is connected to the second bias output end of the bias circuit, the drain of the transistor MN11 is connected to the drain of the transistor MP14, and the drain of the transistor MN11 is grounded; The source of the transistor MN14 and the source of the transistor MN15 are both grounded, the gate of the transistor MN14 is respectively connected to the gate of the transistor MN15 and the drain of the transistor MP16, the drain of the transistor MN15 is connected to the drain of the transistor MP16, the source of the transistor MP16 is grounded, the gate of the transistor MP16 is respectively connected to one end of the resistor R9 and one end of the capacitor C6, the other end of the resistor R9 is respectively connected to the gate of the transistor MP15 and the drain of the transistor MN13, the source of the transistor MP15 is grounded, the drain of the transistor MP15 is connected to the drain of the transistor MN13, the source of the transistor MN13 is grounded, the gate of the transistor MN13 is connected to the first bias output end of the bias circuit, and the other end of the capacitor C5 and the other end of the capacitor C6 are both connected to the drain of the power adjustment tube.

7. A power management chip, characterized in that: The invention comprises a chip body and a LDO without external capacitor based on hybrid nonlinear slew rate enhancement as claimed in any one of claims 1 to 6.

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